diff options
| author | Francisco Jerez <currojerez@riseup.net> | 2021-12-20 00:20:38 -0800 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-01-25 22:40:44 +0000 |
| commit | bdf8ac246603c2ac90abb83ff091aeb662abff77 (patch) | |
| tree | 418137d35b6e9749c66e5428173d7fa50954a6cf | |
| parent | 6c8782c135cdc02b91e5c3899dce097650f756fb (diff) | |
intel/fs: Honor strided source regions specified by the IR for CLUSTER_BROADCAST.
This fixes a bug in the CLUSTER_BROADCAST code generation that causes
the original IR region to be ignored, this will be a problem when we
start lowering 64-bit CLUSTER_BROADCAST instructions at the IR level,
since it will lead to instructions with non-trivial regioning.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 339c8c6265b..5bea405469c 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2469,7 +2469,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, assert(src[2].type == BRW_REGISTER_TYPE_UD); const unsigned component = src[1].ud; const unsigned cluster_size = src[2].ud; - unsigned vstride = cluster_size; + assert(inst->src[0].file != ARF && inst->src[0].file != FIXED_GRF); + const unsigned s = inst->src[0].stride; + unsigned vstride = cluster_size * s; unsigned width = cluster_size; /* The maximum exec_size is 32, but the maximum width is only 16. */ @@ -2478,7 +2480,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, width = 1; } - struct brw_reg strided = stride(suboffset(src[0], component), + struct brw_reg strided = stride(suboffset(src[0], component * s), vstride, width, 0); if (type_sz(src[0].type) > 4 && (devinfo->platform == INTEL_PLATFORM_CHV || |