diff options
| author | Jonathan Marek <jonathan@marek.ca> | 2020-12-03 00:05:37 -0500 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2020-12-09 19:14:10 -0800 |
| commit | b9dbeb597f3d3d2c32863a59003821a9f61a957e (patch) | |
| tree | a01c6841e84c767c092ad514dceb92d7d7e73182 | |
| parent | e9407a0a4f8dfe5f22ba466169c4b1c9e6f77730 (diff) | |
turnip: always set LRZ registers to zero for 3d clear/blit
Apparently LRZ will be read/written regardless of depth being enabled or
not, so we have to make sure these registers are zero.
Fixes: 1d83f5ae8435 ("turnip: disable LRZ on vkCmdClearattachments() 3D fallback path")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7899>
(cherry picked from commit fa16e66a3f4bf6f7eaef82c1770239be9dd824da)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/freedreno/vulkan/tu_clear_blit.c | 9 |
2 files changed, 6 insertions, 5 deletions
diff --git a/.pick_status.json b/.pick_status.json index d5c7c387fd8..93cc6a1a810 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -742,7 +742,7 @@ "description": "turnip: always set LRZ registers to zero for 3d clear/blit", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "1d83f5ae8435c428a20fa947d6a2b22ae453e80c" }, diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index c1169ab25dc..a19f91cf77b 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -785,6 +785,9 @@ r3d_setup(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_RB_SRGB_CNTL(vk_format_is_srgb(vk_format))); tu_cs_emit_regs(cs, A6XX_SP_SRGB_CNTL(vk_format_is_srgb(vk_format))); + tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); + tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); + if (cmd->state.predication_active) { tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_LOCAL, 1); tu_cs_emit(cs, 0); @@ -1905,10 +1908,8 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd, .component_enable = COND(clear_rts & (1 << i), 0xf))); } - if (z_clear) { - tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); - tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); - } + tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); + tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); tu_cs_emit_regs(cs, A6XX_RB_DEPTH_PLANE_CNTL()); tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL( |