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authorAlyssa Rosenzweig <alyssa@rosenzweig.io>2022-01-18 09:48:36 -0500
committerMarge Bot <emma+marge@anholt.net>2022-02-06 15:02:39 +0000
commitb459473bb973d4593f0533a975984aa288e8e275 (patch)
tree57123c49c1cd6f22c6d04d89419136b4f4a356df
parente2903f66ecad4c0ef899fd74c995a4174e88c00f (diff)
agx: Implement nir_op_txb
Like explicit LODs, biases must be 16-bit, so add a lowering rule for this. With the LOD mode selection updated for txb, we can then ingest biases like explicit LODs and allowlist txb. Passes: dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2d_bias dEQP-GLES2.functional.texture.mipmap.2d.bias.* Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14899>
-rw-r--r--src/asahi/compiler/agx_compile.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 9b0789fb8e1..15ab0857251 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -801,6 +801,7 @@ agx_emit_tex(agx_builder *b, nir_tex_instr *instr)
switch (instr->op) {
case nir_texop_tex:
case nir_texop_txl:
+ case nir_texop_txb:
break;
default:
unreachable("Unhandled texture op");
@@ -821,10 +822,10 @@ agx_emit_tex(agx_builder *b, nir_tex_instr *instr)
break;
case nir_tex_src_lod:
+ case nir_tex_src_bias:
lod = index;
break;
- case nir_tex_src_bias:
case nir_tex_src_ms_index:
case nir_tex_src_offset:
case nir_tex_src_comparator:
@@ -1481,7 +1482,8 @@ agx_compile_shader_nir(nir_shader *nir,
};
nir_tex_src_type_constraints tex_constraints = {
- [nir_tex_src_lod] = { true, 16 }
+ [nir_tex_src_lod] = { true, 16 },
+ [nir_tex_src_bias] = { true, 16 },
};
NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);