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authorDaniel Schürmann <daniel@schuermann.dev>2020-05-07 18:19:54 +0100
committerMarge Bot <eric+marge@anholt.net>2020-05-12 15:59:31 +0000
commita5fc96b533418dc2d68f17f3f19ac5f82d59b978 (patch)
treec2aa4c70444bfac0f1e5a273cb3276aa73d8439d
parent38cc649fcb54baf87a974ca2dc29d92b50c86cfa (diff)
aco: coalesce parallelcopies during register allocation
These are the result of lowering to CSSA, and should be removed if possible Totals from affected shaders: (VEGA) SGPRS: 544544 -> 544544 (0.00 %) VGPRS: 418224 -> 418224 (0.00 %) Spilled SGPRs: 141826 -> 141826 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 65853740 -> 64703380 (-1.75 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 13669 -> 13669 (0.00 %) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4952>
-rw-r--r--src/amd/compiler/aco_register_allocation.cpp9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 8d6971e1c4d..318e29b9cf3 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1837,13 +1837,10 @@ void register_allocation(Program *program, std::vector<TempSet>& live_out_per_bl
reg.reg_b += instr->definitions[j].bytes();
if (get_reg_specified(ctx, register_file, definition.regClass(), parallelcopy, instr, reg))
definition.setFixed(reg);
- } else if (instr->opcode == aco_opcode::p_wqm) {
- PhysReg reg;
- if (instr->operands[0].isKillBeforeDef() && instr->operands[0].getTemp().type() == definition.getTemp().type()) {
- reg = instr->operands[0].physReg();
+ } else if (instr->opcode == aco_opcode::p_wqm || instr->opcode == aco_opcode::p_parallelcopy) {
+ PhysReg reg = instr->operands[i].physReg();
+ if (get_reg_specified(ctx, register_file, definition.regClass(), parallelcopy, instr, reg))
definition.setFixed(reg);
- assert(register_file[reg.reg()] == 0);
- }
} else if (instr->opcode == aco_opcode::p_extract_vector) {
PhysReg reg;
if (instr->operands[0].isKillBeforeDef() &&