diff options
| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2018-05-16 17:30:04 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2018-05-29 15:44:50 -0700 |
| commit | a1a850cd3411400ce832e77c4be1f0e14924ce9e (patch) | |
| tree | 06b570fd6af0821648430471e4ec5b28ba0eaa17 | |
| parent | ed834aefa2dc078f1b73659934081d4214e2b338 (diff) | |
intel/fs: Assert that the gen4-6 plane restrictions are followed
The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.
Reviewed-by: Matt Turner <mattst88@gmail.com>
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 6d5306a0eee..0c050a73b4c 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -817,8 +817,14 @@ fs_generator::generate_linterp(fs_inst *inst, } return true; - } else if (devinfo->has_pln && - (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) { + } else if (devinfo->has_pln) { + /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane": + * + * "[DevSNB]:<src1> must be even register aligned. + * + * This restriction is lifted on Ivy Bridge. + */ + assert(devinfo->gen >= 7 || (delta_x.nr & 1) == 0); brw_PLN(p, dst, interp, delta_x); return false; |