r600g: always perform texture perspective divide + fix blending

quake3 engine seems to run fine at this point (ioquake)

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

4 files changed, 88 insertions, 65 deletions

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 43b3e40fad1..8da102cde07 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -963,68 +963,66 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
 
 	/* Add perspective divide */
-	if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_TXP) {
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
-		alu.src[0].sel = src_gpr;
-		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 3;
-		alu.last = 1;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+	alu.src[0].sel = src_gpr;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 3;
+	alu.last = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
 
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-		alu.src[0].sel = ctx->temp_reg;
-		alu.src[0].chan = 3;
-		alu.src[1].sel = src_gpr;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 0;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-		alu.src[0].sel = ctx->temp_reg;
-		alu.src[0].chan = 3;
-		alu.src[1].sel = src_gpr;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 1;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-		alu.src[0].sel = ctx->temp_reg;
-		alu.src[0].chan = 3;
-		alu.src[1].sel = src_gpr;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 2;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.src[0].sel = 249;
-		alu.src[0].chan = 0;
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 3;
-		alu.last = 1;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		src_gpr = ctx->temp_reg;
-	}
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 0;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 2;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+	alu.src[0].sel = 249;
+	alu.src[0].chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 3;
+	alu.last = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	src_gpr = ctx->temp_reg;
 
 	/* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
@@ -1041,6 +1039,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	tex.src_sel_y = 1;
 	tex.src_sel_z = 2;
 	tex.src_sel_w = 3;
+
 	if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
 		tex.coord_type_x = 1;
 		tex.coord_type_y = 1;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 72c0ac5dd1a..e8a591f73ed 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -628,7 +628,6 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
 
 	for (i = 0; i < 8; i++) {
-
 		unsigned eqRGB = state->rt[i].rgb_func;
 		unsigned srcRGB = state->rt[i].rgb_src_factor;
 		unsigned dstRGB = state->rt[i].rgb_dst_factor;
@@ -1202,7 +1201,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	int i;
 
 	target_mask = 0;
-	color_control = 0;
+	color_control = S_028808_PER_MRT_BLEND(1);
 
 	if (pbs->logicop_enable) {
 		color_control |= (pbs->logicop_func) << 16;
@@ -1212,7 +1211,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	target_mask |= (pbs->rt[0].colormask);
 	for (i = 0; i < 8; i++) {
 		if (pbs->rt[i].blend_enable) {
-			color_control |= (1 << (8 + i));
+			color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 26a5dd04321..321e75d7a14 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -48,7 +48,7 @@ static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
 {
 	switch (blend_fact) {
 	case PIPE_BLENDFACTOR_ONE:
-		return V_028804_BLEND_ZERO;
+		return V_028804_BLEND_ONE;
 	case PIPE_BLENDFACTOR_SRC_COLOR:
 		return V_028804_BLEND_SRC_COLOR;
 	case PIPE_BLENDFACTOR_SRC_ALPHA:
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 24cb8593f74..8205bdeadc7 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -315,6 +315,31 @@
 #define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
 #define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
 #define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
 #define R_028010_DB_DEPTH_INFO                       0x028010
 #define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
 #define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)