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authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>2020-08-18 08:23:13 -0400
committerEric Engestrom <eric@engestrom.ch>2020-09-02 21:50:41 +0200
commit873584e6044e5d71993bfc1b8afdda7016eb8686 (patch)
treef447ccb378d03005efe496a4a0c199f7f91c6e25
parent1c48578bcbdb5b09f61831b6ea0b8913bb135c81 (diff)
panfrost: Free hash_to_temp map
No need to put it on the context, we can keep it local in mir_squeeze and drop when we're done. 15.77KB leaked over 85 calls from: 0xffffaed3bfc3 in ?? _mesa_hash_table_rehash at ../src/util/hash_table.c:368 in /home/alyssa/rockchip_dri.so hash_table_insert at ../src/util/hash_table.c:403 in /home/alyssa/rockchip_dri.so find_or_allocate_temp at ../src/panfrost/midgard/mir_squeeze.c:48 in /home/alyssa/rockchip_dri.so find_or_allocate_temp at ../src/panfrost/midgard/mir_squeeze.c:35 in /home/alyssa/rockchip_dri.so mir_squeeze_index at ../src/panfrost/midgard/mir_squeeze.c:76 Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Cc: mesa-stable Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373> (cherry picked from commit 62637a913ab67dc3ade1af3c2d4ae724ab677836)
-rw-r--r--.pick_status.json2
-rw-r--r--src/panfrost/midgard/compiler.h2
-rw-r--r--src/panfrost/midgard/midgard_compile.c1
-rw-r--r--src/panfrost/midgard/mir_squeeze.c19
4 files changed, 12 insertions, 12 deletions
diff --git a/.pick_status.json b/.pick_status.json
index 915fb997930..6dcc74cbbb8 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -4378,7 +4378,7 @@
"description": "panfrost: Free hash_to_temp map",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": null
},
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 5158ea6a85c..66f4bcae042 100644
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -257,8 +257,6 @@ typedef struct compiler_context {
/* Constants which have been loaded, for later inlining */
struct hash_table_u64 *ssa_constants;
- /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
- struct hash_table_u64 *hash_to_temp;
int temp_count;
int max_hash;
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 83221a31c81..f0228c7ac1c 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -2562,7 +2562,6 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
/* Initialize at a global (not block) level hash tables */
ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
- ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
/* Lower gl_Position pre-optimisation, but after lowering vars to ssa
* (so we don't accidentally duplicate the epilogue since mesa/st has
diff --git a/src/panfrost/midgard/mir_squeeze.c b/src/panfrost/midgard/mir_squeeze.c
index e5bf078b344..4684bdd0029 100644
--- a/src/panfrost/midgard/mir_squeeze.c
+++ b/src/panfrost/midgard/mir_squeeze.c
@@ -30,13 +30,14 @@
* as such */
static unsigned
-find_or_allocate_temp(compiler_context *ctx, unsigned hash)
+find_or_allocate_temp(compiler_context *ctx, struct hash_table_u64 *map,
+ unsigned hash)
{
if (hash >= SSA_FIXED_MINIMUM)
return hash;
unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
- ctx->hash_to_temp, hash + 1);
+ map, hash + 1);
if (temp)
return temp - 1;
@@ -45,7 +46,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
temp = ctx->temp_count++;
ctx->max_hash = MAX2(ctx->max_hash, hash);
- _mesa_hash_table_u64_insert(ctx->hash_to_temp,
+ _mesa_hash_table_u64_insert(map,
hash + 1, (void *) ((uintptr_t) temp + 1));
return temp;
@@ -57,10 +58,10 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
void
mir_squeeze_index(compiler_context *ctx)
{
+ struct hash_table_u64 *map = _mesa_hash_table_u64_create(NULL);
+
/* Reset */
ctx->temp_count = 0;
- /* TODO don't leak old hash_to_temp */
- ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
/* We need to prioritize texture registers on older GPUs so we don't
* fail RA trying to assign to work registers r0/r1 when a work
@@ -68,14 +69,16 @@ mir_squeeze_index(compiler_context *ctx)
mir_foreach_instr_global(ctx, ins) {
if (ins->type == TAG_TEXTURE_4)
- ins->dest = find_or_allocate_temp(ctx, ins->dest);
+ ins->dest = find_or_allocate_temp(ctx, map, ins->dest);
}
mir_foreach_instr_global(ctx, ins) {
if (ins->type != TAG_TEXTURE_4)
- ins->dest = find_or_allocate_temp(ctx, ins->dest);
+ ins->dest = find_or_allocate_temp(ctx, map, ins->dest);
for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i)
- ins->src[i] = find_or_allocate_temp(ctx, ins->src[i]);
+ ins->src[i] = find_or_allocate_temp(ctx, map, ins->src[i]);
}
+
+ _mesa_hash_table_u64_destroy(map, NULL);
}