radv: check if DCC is enabled per mip not for the whole image

In other words, make use of radv_dcc_enabled() instead of
radv_image_has_dcc() all over the places.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

6 files changed, 23 insertions, 19 deletions

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2ca73c5a631..a26bf6c6a67 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1294,7 +1294,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 		}
 	}
 
-	if (radv_image_has_dcc(image)) {
+	if (radv_dcc_enabled(image, iview->base_mip)) {
 		/* Drawing with DCC enabled also compresses colorbuffers. */
 		VkImageSubresourceRange range = {
 			.aspectMask = iview->aspect_mask,
@@ -1624,7 +1624,7 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
 	uint32_t level_count = radv_get_levelCount(image, range);
 	uint32_t count = 2 * level_count;
 
-	assert(radv_image_has_dcc(image));
+	assert(radv_dcc_enabled(image, range->baseMipLevel));
 
 	radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 	radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
@@ -1652,7 +1652,7 @@ radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
 	uint32_t level_count = radv_get_levelCount(image, range);
 	uint32_t count = 2 * level_count;
 
-	assert(radv_image_has_dcc(image));
+	assert(radv_dcc_enabled(image, range->baseMipLevel));
 
 	radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 	radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
@@ -1714,7 +1714,8 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 	uint32_t level_count = radv_get_levelCount(image, range);
 	uint32_t count = 2 * level_count;
 
-	assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
+	assert(radv_image_has_cmask(image) ||
+	       radv_dcc_enabled(image, range->baseMipLevel));
 
 	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
 	radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
@@ -1747,7 +1748,8 @@ radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 		.layerCount = iview->layer_count,
 	};
 
-	assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
+	assert(radv_image_has_cmask(image) ||
+	       radv_dcc_enabled(image, iview->base_mip));
 
 	radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
 
@@ -1767,7 +1769,8 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 	struct radv_image *image = iview->image;
 	uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
 
-	if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
+	if (!radv_image_has_cmask(image) &&
+	    !radv_dcc_enabled(image, iview->base_mip))
 		return;
 
 	uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
@@ -4945,7 +4948,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
 		radv_initialize_fmask(cmd_buffer, image);
 	}
 
-	if (radv_image_has_dcc(image)) {
+	if (radv_dcc_enabled(image, range->baseMipLevel)) {
 		uint32_t value = 0xffffffffu; /* Fully expanded mode. */
 		bool need_decompress_pass = false;
 
@@ -4961,7 +4964,8 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
 					 need_decompress_pass);
 	}
 
-	if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
+	if (radv_image_has_cmask(image) ||
+	    radv_dcc_enabled(image, range->baseMipLevel)) {
 		uint32_t color_values[2] = {};
 		radv_set_color_clear_metadata(cmd_buffer, image, range,
 					      color_values);
@@ -4987,7 +4991,7 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe
 		return;
 	}
 
-	if (radv_image_has_dcc(image)) {
+	if (radv_dcc_enabled(image, range->baseMipLevel)) {
 		if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
 			radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
 		} else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 487b75491d1..1424eaef21d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4202,7 +4202,7 @@ radv_init_dcc_control_reg(struct radv_device *device,
 	unsigned max_compressed_block_size;
 	unsigned independent_64b_blocks;
 
-	if (!radv_image_has_dcc(iview->image))
+	if (!radv_dcc_enabled(iview->image, iview->base_mip))
 		return 0;
 
 	if (iview->image->info.samples > 1) {
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 8cacea034ec..c43ed6eeef1 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1469,7 +1469,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
 					  clear_color, &clear_value))
 		return false;
 
-	if (radv_image_has_dcc(iview->image)) {
+	if (radv_dcc_enabled(iview->image, iview->base_mip)) {
 		bool can_avoid_fast_clear_elim;
 		uint32_t reset_value;
 
@@ -1518,7 +1518,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
 	cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
 
 	/* clear cmask buffer */
-	if (radv_image_has_dcc(iview->image)) {
+	if (radv_dcc_enabled(iview->image, iview->base_mip)) {
 		uint32_t reset_value;
 		bool can_avoid_fast_clear_elim;
 		bool need_decompress_pass = false;
diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
index 9b92f64dc89..78a23851281 100644
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -87,7 +87,7 @@ blit_surf_for_image_level_layer(struct radv_image *image,
 {
 	VkFormat format = radv_get_aspect_format(image, aspect_mask);
 
-	if (!radv_image_has_dcc(image) &&
+	if (!radv_dcc_enabled(image, subres->mipLevel) &&
 	    !(radv_image_is_tc_compat_htile(image)))
 		format = vk_format_for_size(vk_format_get_blocksize(format));
 
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index feeb0a1b7ed..6e5fee552b0 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -704,7 +704,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 
 	assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
 
-	if (decompress_dcc && radv_image_has_dcc(image)) {
+	if (decompress_dcc && radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
 		pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
 	} else if (radv_image_has_fmask(image)) {
                pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
@@ -712,7 +712,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
                pipeline = &cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
 	}
 
-	if (radv_image_has_dcc(image)) {
+	if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
 		uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
 							image->fce_pred_offset;
 		pred_offset += 8 * subresourceRange->baseMipLevel;
@@ -725,7 +725,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 
 	radv_process_color_image(cmd_buffer, image, subresourceRange, pipeline);
 
-	if (radv_image_has_dcc(image)) {
+	if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
 		uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
 							image->fce_pred_offset;
 		pred_offset += 8 * subresourceRange->baseMipLevel;
@@ -742,7 +742,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 		}
 	}
 
-	if (radv_image_has_dcc(image)) {
+	if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) {
 		/* Clear the image's fast-clear eliminate predicate because
 		 * FMASK and DCC also imply a fast-clear eliminate.
 		 */
diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index 73a4bbe0789..d5c387d164f 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -506,7 +506,7 @@ void radv_CmdResolveImage(
 		const struct VkOffset3D dstOffset =
 			radv_sanitize_image_offset(dest_image->type, region->dstOffset);
 
-		if (radv_image_has_dcc(dest_image)) {
+		if (radv_dcc_enabled(dest_image, region->dstSubresource.mipLevel)) {
 			VkImageSubresourceRange range = {
 				.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
 				.baseMipLevel = region->dstSubresource.mipLevel,
@@ -676,7 +676,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
 		struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
 		struct radv_image *dst_img = dest_iview->image;
 
-		if (radv_image_has_dcc(dst_img)) {
+		if (radv_dcc_enabled(dst_img, dest_iview->base_mip)) {
 			VkImageSubresourceRange range = {
 				.aspectMask = dest_iview->aspect_mask,
 				.baseMipLevel = dest_iview->base_mip,