diff options
| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-06-22 17:18:02 -0700 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2015-07-01 15:22:41 +0100 |
| commit | 80e283b0539f284563482e9bf901924ac134c0a5 (patch) | |
| tree | f0f43d4c6589e1c3536e55d95f6723af60ba6b8e | |
| parent | 999b2b27168c85f2895c6574de28c31114fc5b7b (diff) | |
i965/skl: Use 1 register for uniform pull constant payload
When under dispatch_width=16 the previous code would allocate 2 registers for
the payload when only one is needed. This manifested itself through bugs on SKL
which needs to mess with this instruction.
Ken thought this might impact shader-db, but apparently it doesn't
Backported to 10.5.8 from (upstream uses alloc.allocate()):
commit 6e62a52865787362ae1deb9dee80140d3a66c519
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date: Thu Feb 19 15:49:34 2015 -0800
i965/skl: Use 1 register for uniform pull constant payload
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Timo Aaltonen <timo.aaltonen@canonical.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index f72d13d6ce3..b54e4d73e82 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -3039,7 +3039,7 @@ fs_visitor::lower_uniform_pull_constant_loads() assert(const_offset_reg.file == IMM && const_offset_reg.type == BRW_REGISTER_TYPE_UD); const_offset_reg.fixed_hw_reg.dw1.ud /= 4; - fs_reg payload = vgrf(glsl_type::uint_type); + fs_reg payload = fs_reg(GRF, virtual_grf_alloc(1)); /* We have to use a message header on Skylake to get SIMD4x2 mode. * Reserve space for the register. |