diff options
| author | Tapani Pälli <tapani.palli@intel.com> | 2022-01-31 11:49:53 +0200 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-02-09 10:05:10 +0000 |
| commit | 7a6ea047954461d8f61878494265ba4bb84b50fe (patch) | |
| tree | d4dd1a8ee69633a17f8abe1fd4df8460b6169b24 | |
| parent | 442628b70244f2c9fd0ed79e0656e999ee6fffca (diff) | |
anv: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: 6c345ddbe40 ("anv: Cache VB/IB in L3$ for Gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5941
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 7b50a448d05..0db3c7dfca5 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2400,6 +2400,13 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT; pipe.ConstantCacheInvalidationEnable = bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT; +#if GFX_VER >= 12 + /* Invalidates the L3 cache part in which index & vertex data is loaded + * when VERTEX_BUFFER_STATE::L3BypassDisable is set. + */ + pipe.L3ReadOnlyCacheInvalidationEnable = + bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT; +#endif pipe.VFCacheInvalidationEnable = bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT; pipe.TextureCacheInvalidationEnable = |