diff options
| author | Ian Romanick <ian.d.romanick@intel.com> | 2021-02-13 13:22:41 -0800 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2021-02-23 13:50:59 -0800 |
| commit | 6ee04359c346a1c156764b2ec8057dca23e08775 (patch) | |
| tree | d6079142234479a964358692646d7d7859db2b4a | |
| parent | 3c70ece7eb60997a1e0855dad600102b267e9d51 (diff) | |
intel/compiler: Make the CMPN builder work like the CMP builder
Since the CMPN builder was never used, there was no reason to make its
interface usable. :)
Fixes: 2f2c00c7279 ("i965: Lower min/max after optimization on Gen4/5.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9027>
(cherry picked from commit 684ec33c79a068bacff70c3414342ee895501926)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_builder.h | 26 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_builder.h | 26 |
3 files changed, 51 insertions, 3 deletions
diff --git a/.pick_status.json b/.pick_status.json index b71c8fec586..a4c23b33da0 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -2965,7 +2965,7 @@ "description": "intel/compiler: Make the CMPN builder work like the CMP builder", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "2f2c00c7279e7c43e520e21de1781f8cec263e92" }, diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 368285a3cbe..2fcbdb73f2a 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -565,7 +565,6 @@ namespace brw { ALU3(BFI2) ALU1(BFREV) ALU1(CBIT) - ALU2(CMPN) ALU1(DIM) ALU2(DP2) ALU2(DP3) @@ -634,6 +633,31 @@ namespace brw { } /** + * CMPN: Behaves like CMP, but produces true if src1 is NaN. + */ + instruction * + CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, + brw_conditional_mod condition) const + { + /* Take the instruction: + * + * CMP null<d> src0<f> src1<f> + * + * Original gen4 does type conversion to the destination type + * before comparison, producing garbage results for floating + * point comparisons. + * + * The destination type doesn't matter on newer generations, + * so we set the type to match src0 so we can compact the + * instruction. + */ + return set_condmod(condition, + emit(BRW_OPCODE_CMPN, retype(dst, src0.type), + fix_unsigned_negate(src0), + fix_unsigned_negate(src1))); + } + + /** * Gen4 predicated IF. */ instruction * diff --git a/src/intel/compiler/brw_vec4_builder.h b/src/intel/compiler/brw_vec4_builder.h index f056fe6a331..f821607bcfa 100644 --- a/src/intel/compiler/brw_vec4_builder.h +++ b/src/intel/compiler/brw_vec4_builder.h @@ -403,7 +403,6 @@ namespace brw { ALU3(BFI2) ALU1(BFREV) ALU1(CBIT) - ALU2(CMPN) ALU3(CSEL) ALU1(DIM) ALU2(DP2) @@ -471,6 +470,31 @@ namespace brw { } /** + * CMPN: Behaves like CMP, but produces true if src1 is NaN. + */ + instruction * + CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, + brw_conditional_mod condition) const + { + /* Take the instruction: + * + * CMPN null<d> src0<f> src1<f> + * + * Original gen4 does type conversion to the destination type + * before comparison, producing garbage results for floating + * point comparisons. + * + * The destination type doesn't matter on newer generations, + * so we set the type to match src0 so we can compact the + * instruction. + */ + return set_condmod(condition, + emit(BRW_OPCODE_CMPN, retype(dst, src0.type), + fix_unsigned_negate(src0), + fix_unsigned_negate(src1))); + } + + /** * Gen4 predicated IF. */ instruction * |