pan/va: Add 2-channel 8-bit swizzles for conversions

Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two
bytes. The definition is the same as Bifrost. Let's call this a half-swizzle
since we need a name, and it is indeed half a swizzle...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>

4 files changed, 48 insertions, 6 deletions

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index df210931281..6ceb53f72ca 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -201,6 +201,29 @@
     <reserved/>
   </enum>
 
+  <enum name="Half-swizzles (8-bit)">
+    <desc>
+      Used to select the 2 bytes to convert for conversions from 8-bit vectors
+      to 16-bit vectors
+    </desc>
+    <value>b00</value>
+    <value>b10</value>
+    <value>b20</value>
+    <value>b30</value>
+    <value>b01</value>
+    <value>b11</value>
+    <value>b21</value>
+    <value>b31</value>
+    <value>b02</value>
+    <value>b12</value>
+    <value>b22</value>
+    <value>b32</value>
+    <value>b03</value>
+    <value>b13</value>
+    <value>b23</value>
+    <value>b33</value>
+  </enum>
+
   <enum name="Swizzles (16-bit)">
     <value>h00</value> <!-- 0,2 -->
     <value>h10</value>
@@ -1207,22 +1230,32 @@
     <src lane="28" size="16" absneg="true">Value to convert</src>
   </ins>
 
-  <group name="CONVERT" title="8-bit data conversions" dests="1" opcode="0x90" unit="CVT">
+  <group name="CONVERT" title="8-bit to 32-bit data conversions" dests="1" opcode="0x90" unit="CVT">
     <desc>
       Performs the given data conversion.
     </desc>
 
     <ins name="S8_TO_S32" opcode2="0x0"/>
     <ins name="S8_TO_F32" opcode2="0x1"/>
-    <ins name="V2S8_TO_V2S16" opcode2="0x2"/>
-    <ins name="V2S8_TO_V2F16" opcode2="0x3"/>
 
     <ins name="U8_TO_U32" opcode2="0x10"/>
     <ins name="U8_TO_F32" opcode2="0x11"/>
+
+    <src lane="28" size="8">Value to convert</src>
+  </group>
+
+  <group name="CONVERT" title="8-bit to 16-bit data conversions" dests="1" opcode="0x90" unit="CVT">
+    <desc>
+      Performs the given data conversion.
+    </desc>
+
+    <ins name="V2S8_TO_V2S16" opcode2="0x2"/>
+    <ins name="V2S8_TO_V2F16" opcode2="0x3"/>
+
     <ins name="V2U8_TO_V2U16" opcode2="0x12"/>
     <ins name="V2U8_TO_V2F16" opcode2="0x13"/>
 
-    <src lane="28" size="8">Value to convert</src>
+    <src halfswizzle="true" size="8">Value to convert</src>
   </group>
 
   <group name="FROUND" title="Floating-point rounding" dests="1" opcode="0x90" unit="CVT">
diff --git a/src/panfrost/bifrost/valhall/asm.py b/src/panfrost/bifrost/valhall/asm.py
index c088eb66eb8..8c025a5b909 100644
--- a/src/panfrost/bifrost/valhall/asm.py
+++ b/src/panfrost/bifrost/valhall/asm.py
@@ -260,6 +260,11 @@ def parse_asm(line):
             # Encode the modifier
             if mod in src.offset and src.bits[mod] == 1:
                 encoded |= (1 << src.offset[mod])
+            elif src.halfswizzle and mod in enums[f'half_swizzles_{src.size}_bit'].bare_values:
+                die_if(swizzled, "Multiple swizzles specified")
+                swizzled = True
+                val = enums[f'half_swizzles_{src.size}_bit'].bare_values.index(mod)
+                encoded |= (val << src.offset['widen'])
             elif mod in enums[f'swizzles_{src.size}_bit'].bare_values and (src.widen or src.lanes):
                 die_if(swizzled, "Multiple swizzles specified")
                 swizzled = True
diff --git a/src/panfrost/bifrost/valhall/disasm.py b/src/panfrost/bifrost/valhall/disasm.py
index 50581c97824..bef71eeeb92 100644
--- a/src/panfrost/bifrost/valhall/disasm.py
+++ b/src/panfrost/bifrost/valhall/disasm.py
@@ -185,6 +185,8 @@ va_disasm_instr(FILE *fp, uint64_t instr)
 % endif
 % if src.lanes:
             fputs(valhall_lanes_8_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
+% elif src.halfswizzle:
+            fputs(valhall_half_swizzles_8_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
 % elif src.widen:
 		    fputs(valhall_swizzles_${src.size}_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
 % endif
diff --git a/src/panfrost/bifrost/valhall/valhall.py b/src/panfrost/bifrost/valhall/valhall.py
index 5056aec8f61..b90841cf910 100644
--- a/src/panfrost/bifrost/valhall/valhall.py
+++ b/src/panfrost/bifrost/valhall/valhall.py
@@ -98,12 +98,13 @@ def Flag(name, start):
 
 # Model a single instruction
 class Source:
-    def __init__(self, index, size, is_float = False, swizzle = False, widen = False, lanes = False, lane = None, absneg = False, notted = False, name = ""):
+    def __init__(self, index, size, is_float = False, swizzle = False, halfswizzle = False, widen = False, lanes = False, lane = None, absneg = False, notted = False, name = ""):
         self.is_float = is_float or absneg
         self.size = size
         self.absneg = absneg
         self.notted = notted
         self.swizzle = swizzle
+        self.halfswizzle = halfswizzle
         self.widen = widen
         self.lanes = lanes
         self.lane = lane
@@ -119,7 +120,7 @@ class Source:
         if notted:
             self.offset['not'] = 35
             self.bits['not'] = 1
-        if widen or lanes:
+        if widen or lanes or halfswizzle:
             self.offset['widen'] = 26 if index == 1 else 36
             self.bits['widen'] = 4 # XXX: too much?
         if lane:
@@ -210,6 +211,7 @@ def build_source(el, i, size):
             absneg = el.get('absneg', False),
             is_float = el.get('float', False),
             swizzle = el.get('swizzle', False),
+            halfswizzle = el.get('halfswizzle', False),
             widen = el.get('widen', False),
             lanes = el.get('lanes', False),
             lane = lane,