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authorDanylo Piliaiev <dpiliaiev@igalia.com>2020-12-07 15:56:03 +0200
committerDanylo Piliaiev <dpiliaiev@igalia.com>2020-12-21 16:06:20 +0200
commit4b208fa36b484d2dbe0e7f1fc707544d3a1f17c5 (patch)
tree7ab8f7eab3990527e916be484fa0641f1fe528c1
parent296d8662dc68612c41d0e488d9b8bdf51e674b06 (diff)
freedreno/a6xx: Fix assert which checks the count of shader outputs
The actual max count is 32 which corresponds to 128 output components. Fixes: 2251a434 "freedreno/a6xx: Write multiple regs for SP_VS_OUT_REG and SP_VS_VPC_DST_REG" Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7917>
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_program.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index f372123224a..c872c94839b 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -581,7 +581,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
setup_stream_out(state, last_shader, &l);
}
- debug_assert(l.cnt < 32);
+ debug_assert(l.cnt <= 32);
if (gs)
OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
else if (ds)