i965/gen6: Use the generic ISL-based path for renderbuffer surfaces

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

1 files changed, 1 insertions, 99 deletions

diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index d892c932af4..84b8ef47475 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -40,107 +40,9 @@
 #include "brw_defines.h"
 #include "brw_wm.h"
 
-/**
- * Sets up a surface state structure to point at the given region.
- * While it is only used for the front/back buffer currently, it should be
- * usable for further buffers when doing ARB_draw_buffer support.
- */
-static uint32_t
-gen6_update_renderbuffer_surface(struct brw_context *brw,
-                                 struct gl_renderbuffer *rb,
-                                 bool layered, unsigned unit /* unused */,
-                                 uint32_t surf_index)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   struct intel_mipmap_tree *mt = irb->mt;
-   uint32_t *surf;
-   uint32_t format = 0;
-   uint32_t offset;
-   /* _NEW_BUFFERS */
-   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
-   uint32_t surftype;
-   int depth = MAX2(irb->layer_count, 1);
-   const GLenum gl_target =
-      rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
-
-   intel_miptree_used_for_rendering(irb->mt);
-
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
-
-   format = brw->render_target_format[rb_format];
-   if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
-      _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-                    __func__, _mesa_get_format_name(rb_format));
-   }
-
-   switch (gl_target) {
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-      surftype = BRW_SURFACE_2D;
-      depth *= 6;
-      break;
-   case GL_TEXTURE_3D:
-      depth = MAX2(irb->mt->logical_depth0, 1);
-      /* fallthrough */
-   default:
-      surftype = translate_tex_target(gl_target);
-      break;
-   }
-
-   const int min_array_element = irb->mt_layer;
-   assert(!layered || irb->mt_layer == 0);
-
-   surf[0] = SET_FIELD(surftype, BRW_SURFACE_TYPE) |
-             SET_FIELD(format, BRW_SURFACE_FORMAT);
-
-   /* reloc */
-   assert(mt->offset % mt->cpp == 0);
-   surf[1] = mt->bo->offset64 + mt->offset;
-
-   /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
-    * (Surface Arrays For all surfaces other than separate stencil buffer):
-    *
-    * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
-    *  calculated in the equation above , for every other odd Surface Height
-    *  starting from 1 i.e. 1,5,9,13"
-    *
-    * Since this Qpitch errata only impacts the sampler, we have to adjust the
-    * input for the rendering surface to achieve the same qpitch. For the
-    * affected heights, we increment the height by 1 for the rendering
-    * surface.
-    */
-   int height0 = irb->mt->logical_height0;
-   if (brw->gen == 6 && irb->mt->num_samples > 1 && (height0 % 4) == 1)
-      height0++;
-
-   surf[2] = SET_FIELD(mt->logical_width0 - 1, BRW_SURFACE_WIDTH) |
-             SET_FIELD(height0 - 1, BRW_SURFACE_HEIGHT) |
-             SET_FIELD(irb->mt_level - irb->mt->first_level, BRW_SURFACE_LOD);
-
-   surf[3] = brw_get_surface_tiling_bits(mt->tiling) |
-             SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
-             SET_FIELD(mt->pitch - 1, BRW_SURFACE_PITCH);
-
-   surf[4] = brw_get_surface_num_multisamples(mt->num_samples) |
-             SET_FIELD(min_array_element, BRW_SURFACE_MIN_ARRAY_ELEMENT) |
-             SET_FIELD(depth - 1, BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT);
-
-   surf[5] = (mt->valign == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
-
-   drm_intel_bo_emit_reloc(brw->batch.bo,
-                           offset + 4,
-                           mt->bo,
-                           surf[1] - mt->bo->offset64,
-                           I915_GEM_DOMAIN_RENDER,
-                           I915_GEM_DOMAIN_RENDER);
-
-   return offset;
-}
-
 void
 gen6_init_vtable_surface_functions(struct brw_context *brw)
 {
    gen4_init_vtable_surface_functions(brw);
-   brw->vtbl.update_renderbuffer_surface = gen6_update_renderbuffer_surface;
+   brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
 }