diff options
| author | Chris Forbes <chrisf@ijw.co.nz> | 2014-08-04 19:41:03 +1200 |
|---|---|---|
| committer | Chris Forbes <chrisf@ijw.co.nz> | 2014-08-09 13:12:33 +1200 |
| commit | 298da9fa2adba3f0f4c89220c696684937016f7c (patch) | |
| tree | e52128f861cace6e33a02e7716c890b4b2257447 | |
| parent | 6be68767b9b5344d5753b8909f5ec8f57309b71a (diff) | |
i965/vec4/Gen8: Use src1 for sampler_index instead of ->sampler field
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.h | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 19 |
2 files changed, 15 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 7c2721dec1e..90012860498 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -727,7 +727,8 @@ private: struct brw_reg *src); void generate_tex(vec4_instruction *inst, - struct brw_reg dst); + struct brw_reg dst, + struct brw_reg sampler_index); void generate_urb_write(vec4_instruction *ir, bool copy_g0); void generate_gs_thread_end(vec4_instruction *ir); diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp index ee8e85ef992..6951f887d0a 100644 --- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp @@ -50,7 +50,8 @@ gen8_vec4_generator::~gen8_vec4_generator() } void -gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst) +gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst, + struct brw_reg sampler_index) { int msg_type = 0; @@ -100,6 +101,11 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst) unreachable("should not get here: invalid VS texture opcode"); } + assert(sampler_index.file == BRW_IMMEDIATE_VALUE); + assert(sampler_index.type == BRW_REGISTER_TYPE_UD); + + uint32_t sampler = sampler_index.dw1.ud; + if (ir->header_present) { MOV_RAW(retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); @@ -113,7 +119,7 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst) brw_imm_ud(ir->texture_offset)); } - if (ir->sampler >= 16) { + if (sampler >= 16) { /* The "Sampler Index" field can only store values between 0 and 15. * However, we can add an offset to the "Sampler State Pointer" * field, effectively selecting a different set of 16 samplers. @@ -126,7 +132,7 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst) gen8_instruction *add = ADD(get_element_ud(brw_message_reg(ir->base_mrf), 3), get_element_ud(brw_vec8_grf(0, 0), 3), - brw_imm_ud(16 * (ir->sampler / 16) * sampler_state_size)); + brw_imm_ud(16 * (sampler / 16) * sampler_state_size)); gen8_set_mask_control(add, BRW_MASK_DISABLE); } @@ -134,14 +140,14 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst) } uint32_t surf_index = - prog_data->base.binding_table.texture_start + ir->sampler; + prog_data->base.binding_table.texture_start + sampler; gen8_instruction *inst = next_inst(BRW_OPCODE_SEND); gen8_set_dst(brw, inst, dst); gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf)); gen8_set_sampler_message(brw, inst, surf_index, - ir->sampler % 16, + sampler % 16, msg_type, 1, ir->mlen, @@ -765,7 +771,8 @@ gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, case SHADER_OPCODE_TXS: case SHADER_OPCODE_TG4: case SHADER_OPCODE_TG4_OFFSET: - generate_tex(ir, dst); + /* note: src[0] is unused. */ + generate_tex(ir, dst, src[1]); break; case VS_OPCODE_URB_WRITE: |