diff options
author | Rob Clark <robdclark@chromium.org> | 2020-12-15 10:50:28 -0800 |
---|---|---|
committer | Marge Bot <eric+marge@anholt.net> | 2021-01-06 16:46:52 +0000 |
commit | 2933d54992960b84ef8696b9d6de7cce91eec6b1 (patch) | |
tree | b7c4a17d8ca1b6343dd7fbe3c34de2de8d9d1712 | |
parent | e3bd9aaf6ba3288cae74d19bc1265c9696390896 (diff) |
freedreno/ir3: Fix mova1 disasm
Yet another mnemonic for mov
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
-rw-r--r-- | src/freedreno/.gitlab-ci/reference/fd-clouds.log | 12 | ||||
-rw-r--r-- | src/freedreno/ir3/disasm-a3xx.c | 11 | ||||
-rw-r--r-- | src/freedreno/ir3/tests/disasm.c | 1 |
3 files changed, 16 insertions, 8 deletions
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log index 77bf190c8d2..874f1085c78 100644 --- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log +++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log @@ -2087,7 +2087,7 @@ t4 write SP_FS_OBJ_START_LO (a983) 00000000010130c0: 00c0: 10261023 6386800d 20080013 42700010 10261023 6387000e 40141066 4010001b 00000000010130e0: 00e0: 00141025 40700016 00000014 80100014 20040008 46f00008 00000004 80900000 :1:0000:0000[204cc000x_40400000x] mov.u32u32 r0.x, 0x40400000 - :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0x00000000 + :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0 :1:0002:0002[204cc004x_3e99999ax] mov.u32u32 r1.x, 0x3e99999a :2:0003:0003[42700008x_20080014x] sub.s r2.x, r5.x, 8 :3:0004:0004[6380000cx_10331003x] mad.f32 r3.x, c0.w, r0.x, c12.w @@ -3334,7 +3334,7 @@ t4 write SP_FS_OBJ_START_LO (a983) :2:1245:2200[40700009x_00180029x] mul.f r2.y, r10.y, r6.x :2:1246:2201[4070000ax_0012001dx] mul.f r2.z, r7.y, r4.z :0:1247:2202[01000000x_0000000ex] jump #14 - :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0x00000000 + :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0 :0:1249:2204[00000200x_00000000x] (rpt2)nop :1:1250:2207[200cc010x_00000007x] mov.u32u32 r4.x, r1.w :0:1251:2208[00000200x_00000000x] (rpt2)nop @@ -3510,7 +3510,7 @@ t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) { EXT_SRC_ADDR = 0x1013000 } { EXT_SRC_ADDR_HI = 0 } :1:0000:0000[204cc000x_40400000x] mov.u32u32 r0.x, 0x40400000 - :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0x00000000 + :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0 :1:0002:0002[204cc004x_3e99999ax] mov.u32u32 r1.x, 0x3e99999a :2:0003:0003[42700008x_20080014x] sub.s r2.x, r5.x, 8 :3:0004:0004[6380000cx_10331003x] mad.f32 r3.x, c0.w, r0.x, c12.w @@ -4757,7 +4757,7 @@ t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) :2:1245:2200[40700009x_00180029x] mul.f r2.y, r10.y, r6.x :2:1246:2201[4070000ax_0012001dx] mul.f r2.z, r7.y, r4.z :0:1247:2202[01000000x_0000000ex] jump #14 - :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0x00000000 + :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0 :0:1249:2204[00000200x_00000000x] (rpt2)nop :1:1250:2207[200cc010x_00000007x] mov.u32u32 r4.x, r1.w :0:1251:2208[00000200x_00000000x] (rpt2)nop @@ -5362,7 +5362,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) 00000000010130c0: 00c0: 10261023 6386800d 20080013 42700010 10261023 6387000e 40141066 4010001b 00000000010130e0: 00e0: 00141025 40700016 00000014 80100014 20040008 46f00008 00000004 80900000 :1:0000:0000[204cc000x_40400000x] mov.u32u32 r0.x, 0x40400000 - :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0x00000000 + :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0 :1:0002:0002[204cc004x_3e99999ax] mov.u32u32 r1.x, 0x3e99999a :2:0003:0003[42700008x_20080014x] sub.s r2.x, r5.x, 8 :3:0004:0004[6380000cx_10331003x] mad.f32 r3.x, c0.w, r0.x, c12.w @@ -6609,7 +6609,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) :2:1245:2200[40700009x_00180029x] mul.f r2.y, r10.y, r6.x :2:1246:2201[4070000ax_0012001dx] mul.f r2.z, r7.y, r4.z :0:1247:2202[01000000x_0000000ex] jump #14 - :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0x00000000 + :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0 :0:1249:2204[00000200x_00000000x] (rpt2)nop :1:1250:2207[200cc010x_00000007x] mov.u32u32 r4.x, r1.w :0:1251:2208[00000200x_00000000x] (rpt2)nop diff --git a/src/freedreno/ir3/disasm-a3xx.c b/src/freedreno/ir3/disasm-a3xx.c index ff504e69652..9e54fc441bf 100644 --- a/src/freedreno/ir3/disasm-a3xx.c +++ b/src/freedreno/ir3/disasm-a3xx.c @@ -450,9 +450,12 @@ static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr) switch (_OPC(1, cat1->opc)) { case OPC_MOV: if (cat1->src_type == cat1->dst_type) { - if ((cat1->src_type == TYPE_S16) && (((reg_t)cat1->dst).num == REG_A0)) { + reg_t dst = (reg_t)cat1->dst; + if ((cat1->src_type == TYPE_S16) && (dst.num == REG_A0) && (dst.comp == 0)) { /* special case (nmemonic?): */ fprintf(ctx->out, "mova"); + } else if ((cat1->src_type == TYPE_U16) && (dst.num == REG_A0) && (dst.comp == 1)) { + fprintf(ctx->out, "mova1"); } else { fprintf(ctx->out, "mov.%s%s", type[cat1->src_type], type[cat1->dst_type]); } @@ -481,7 +484,11 @@ static void print_instr_cat1(struct disasm_ctx *ctx, instr_t *instr) } else { fprintf(ctx->out, "(%f)", cat1->fim_val); } - } else if (type_uint(cat1->src_type)) { + } else if (type_uint(cat1->src_type) && (cat1->uim_val > 0x1000)) { + /* Print large uint as hex, which differs from blob, but ir3 + * will generate mov.u32u32 for floats sometimes, and this is + * easier to see in hex than dec + */ fprintf(ctx->out, "0x%08x", cat1->uim_val); } else { if ((type_size(cat1->src_type) < 32) && (cat1->uim_val & 0x8000)) { diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c index f2e73c96b94..06a6c59bf33 100644 --- a/src/freedreno/ir3/tests/disasm.c +++ b/src/freedreno/ir3/tests/disasm.c @@ -68,6 +68,7 @@ static const struct test { INSTR_6XX(20510005_0000ffff, "mov.s16s16 hr1.y, -1"), INSTR_6XX(20400005_00003900, "mov.f16f16 hr1.y, h(0.625000)"), INSTR_6XX(20400006_00003800, "mov.f16f16 hr1.z, h(0.500000)"), + INSTR_6XX(204880f5_00000000, "mova1 a1.x, 0"), /* cat2 */ INSTR_6XX(40104002_0c210001, "add.f hr0.z, r0.y, c<a0.x + 33>"), |