diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2024-02-26 21:08:51 -0500 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-03-11 23:36:55 +0000 |
| commit | 20445f296bfcf3be40436617aad5d8378ad09bce (patch) | |
| tree | 98baf89aef42eabf152969c0906f6f4d60760731 | |
| parent | 62d360c287193609e921cfd9886c3f5b37c4b9ed (diff) | |
radeonsi: disable binning correctly on gfx11.5
Fixes: b44a886b84c - amd/common: add registers for gfx11.5
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_binning.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index 39a97ebd0ce..984586eb864 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -393,6 +393,9 @@ static void si_emit_dpbb_disable(struct si_context *sctx) if (sctx->gfx_level >= GFX10) { struct uvec2 bin_size = {}; struct uvec2 bin_size_extend = {}; + unsigned binning_disabled = + sctx->gfx_level >= GFX11_5 ? V_028C44_BINNING_DISABLED + : V_028C44_DISABLE_BINNING_USE_NEW_SC; bin_size.x = 128; bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64; @@ -404,7 +407,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0, - S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | + S_028C44_BINNING_MODE(binning_disabled) | S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) | |