diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2019-07-12 15:45:33 -0400 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2019-07-19 20:16:19 -0400 |
| commit | 1d82240f554c6f610d2456db79958c261155960a (patch) | |
| tree | f87b716a9aef0eee6f758e0fa5f19516342253f9 | |
| parent | 8f72f137ad168775e6b50b69b1af2ba2754dbcfe (diff) | |
radeonsi/gfx10: add debug options to enable/disable Wave32
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 30 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 6 |
2 files changed, 35 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 7b2c2dc2ee9..e6b9d446565 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -63,6 +63,12 @@ static const struct debug_named_value debug_options[] = { { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" }, { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." }, { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." }, + { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." }, + { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." }, + { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." }, + { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." }, + { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." }, + { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." }, /* Shader compiler options (with no effect on the shader cache): */ { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" }, @@ -849,7 +855,13 @@ static void si_disk_cache_create(struct si_screen *sscreen) #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \ DBG(SI_SCHED) | \ DBG(GISEL) | \ - DBG(UNSAFE_MATH)) + DBG(UNSAFE_MATH) | \ + DBG(W32_GE) | \ + DBG(W32_PS) | \ + DBG(W32_CS) | \ + DBG(W64_GE) | \ + DBG(W64_PS) | \ + DBG(W64_CS)) uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS; if (sscreen->options.enable_nir) { @@ -1218,6 +1230,22 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->ps_wave_size = 64; sscreen->compute_wave_size = 64; + if (sscreen->info.chip_class >= GFX10) { + if (sscreen->debug_flags & DBG(W32_GE)) + sscreen->ge_wave_size = 32; + if (sscreen->debug_flags & DBG(W32_PS)) + sscreen->ps_wave_size = 32; + if (sscreen->debug_flags & DBG(W32_CS)) + sscreen->compute_wave_size = 32; + + if (sscreen->debug_flags & DBG(W64_GE)) + sscreen->ge_wave_size = 64; + if (sscreen->debug_flags & DBG(W64_PS)) + sscreen->ps_wave_size = 64; + if (sscreen->debug_flags & DBG(W64_CS)) + sscreen->compute_wave_size = 64; + } + /* Create the auxiliary context. This must be done last. */ sscreen->aux_context = si_create_context( &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 63e1bdaa813..6798606c0d8 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -148,6 +148,12 @@ enum { DBG_UNSAFE_MATH, DBG_SI_SCHED, DBG_GISEL, + DBG_W32_GE, + DBG_W32_PS, + DBG_W32_CS, + DBG_W64_GE, + DBG_W64_PS, + DBG_W64_CS, /* Shader compiler options (with no effect on the shader cache): */ DBG_CHECK_IR, |