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| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2021-02-24 19:42:03 -0500 |
|---|---|---|
| committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2021-04-11 11:47:42 -0400 |
| commit | 1a6a772527974b390a5a691512319f7692ae430f (patch) | |
| tree | 1917a40664ba234f118ef99658e76442bb78a53a | |
| parent | cd296c9f8cc363088e63eda6092e146f061e9cdb (diff) | |
nv50: implement memory barrier handling
With shader images / buffers, we can get more complex barrier requests.
This mirrors the logic in nvc0.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>
| -rw-r--r-- | src/gallium/drivers/nouveau/nv50/nv50_context.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c b/src/gallium/drivers/nouveau/nv50/nv50_context.c index 447f10e3acb..3616895ed4c 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_context.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c @@ -58,6 +58,7 @@ static void nv50_memory_barrier(struct pipe_context *pipe, unsigned flags) { struct nv50_context *nv50 = nv50_context(pipe); + struct nouveau_pushbuf *push = nv50->base.pushbuf; int i, s; if (flags & PIPE_BARRIER_MAPPED_BUFFER) { @@ -87,7 +88,23 @@ nv50_memory_barrier(struct pipe_context *pipe, unsigned flags) nv50->cb_dirty = true; } } + } else { + BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1); + PUSH_DATA (push, 0); + } + + /* If we're going to texture from a buffer/image written by a shader, we + * must flush the texture cache. + */ + if (flags & PIPE_BARRIER_TEXTURE) { + BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1); + PUSH_DATA (push, 0x20); } + + if (flags & PIPE_BARRIER_CONSTANT_BUFFER) + nv50->cb_dirty = true; + if (flags & (PIPE_BARRIER_VERTEX_BUFFER | PIPE_BARRIER_INDEX_BUFFER)) + nv50->base.vbo_dirty = true; } static void |