diff options
| author | Dave Airlie <airlied@redhat.com> | 2017-03-31 11:47:18 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2017-03-31 11:47:18 +1000 |
| commit | 8cd3ac52963f2e99f4c21d1c9ce89531ce66c2d6 (patch) | |
| tree | 94f7d4526fe19a32643308d6e00d0fc5442af277 | |
| parent | 8bcad07a45637fb88e799466e4eee83859e8ffd3 (diff) | |
| parent | 60508d3df2d2052881190ac82802a12cabcef53c (diff) | |
Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next
New stuff for 4.12:
- Preliminary vega10 support
- Support for multi-level page tables
- GPU sensor stuff for mesa
- job tracing improvements
- PRT support for sparse buffers
- Additional SR-IOV improvements
- ttm improvements
- misc bug fixes and code cleanups
* 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (315 commits)
drm/amdgpu: Fix 32bit x86 compilation warning
drm/amdgpu: just disallow reading untouched registers
drm/amdgpu: remove duplicate allowed reg CP_CPF_BUSY_STAT
drm/amdgpu/soc15: enable psp block for SRIOV
drm/amdgpu/soc15: bypass pp block for vf
drm/amdgpu/psp: add check sOS sign
drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)
drm/amdgpu: Fix multi-level page table bugs for large BOs v3
drm/amdgpu: Fix Vega10 VM initialization
drm/amdgpu: Make max_pfn 64-bit
drm/amdgpu: drop GB_GPU_ID from the golden settings
drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)
drm/amd/amdgpu: fix Tonga S3 resume hang on rhel6.8
drm/ttm: decrease ttm bo priority number
drm/amd/amdgpu: fix performance drop when VRAM pressure
drm/amdgpu: Couple small warning fixes
drm/amdgpu: Clean up GFX 9 VM fault messages
drm/amdgpu: Register UTCL2 as a source of VM faults
drm/amdgpu/soc15: drop support for reading some registers
drm/amdgpu/soc15: return cached values for some registers (v2)
...
253 files changed, 398656 insertions, 1916 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 2814aad81752..660786aba7d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -24,7 +24,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ - amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o + amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o # add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ @@ -34,12 +34,13 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o amdgpu-y += \ - vi.o mxgpu_vi.o + vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o # add GMC block amdgpu-y += \ gmc_v7_0.o \ - gmc_v8_0.o + gmc_v8_0.o \ + gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o # add IH block amdgpu-y += \ @@ -47,7 +48,13 @@ amdgpu-y += \ amdgpu_ih.o \ iceland_ih.o \ tonga_ih.o \ - cz_ih.o + cz_ih.o \ + vega10_ih.o + +# add PSP block +amdgpu-y += \ + amdgpu_psp.o \ + psp_v3_1.o # add SMC block amdgpu-y += \ @@ -63,23 +70,27 @@ amdgpu-y += \ # add GFX block amdgpu-y += \ amdgpu_gfx.o \ - gfx_v8_0.o + gfx_v8_0.o \ + gfx_v9_0.o # add async DMA block amdgpu-y += \ sdma_v2_4.o \ - sdma_v3_0.o + sdma_v3_0.o \ + sdma_v4_0.o # add UVD block amdgpu-y += \ amdgpu_uvd.o \ uvd_v5_0.o \ - uvd_v6_0.o + uvd_v6_0.o \ + uvd_v7_0.o # add VCE block amdgpu-y += \ amdgpu_vce.o \ - vce_v3_0.o + vce_v3_0.o \ + vce_v4_0.o # add amdkfd interfaces amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c1b913541739..262056778f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -52,6 +52,7 @@ #include "amdgpu_irq.h" #include "amdgpu_ucode.h" #include "amdgpu_ttm.h" +#include "amdgpu_psp.h" #include "amdgpu_gds.h" #include "amdgpu_sync.h" #include "amdgpu_ring.h" @@ -59,6 +60,8 @@ #include "amd_powerplay.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" +#include "amdgpu_uvd.h" +#include "amdgpu_vce.h" #include "gpu_scheduler.h" #include "amdgpu_virt.h" @@ -79,7 +82,7 @@ extern int amdgpu_pcie_gen2; extern int amdgpu_msi; extern int amdgpu_lockup_timeout; extern int amdgpu_dpm; -extern int amdgpu_smc_load_fw; +extern int amdgpu_fw_load_type; extern int amdgpu_aspm; extern int amdgpu_runtime_pm; extern unsigned amdgpu_ip_block_mask; @@ -101,6 +104,11 @@ extern char *amdgpu_disable_cu; extern char *amdgpu_virtual_display; extern unsigned amdgpu_pp_feature_mask; extern int amdgpu_vram_page_split; +extern int amdgpu_ngg; +extern int amdgpu_prim_buf_per_se; +extern int amdgpu_pos_buf_per_se; +extern int amdgpu_cntl_sb_buf_per_se; +extern int amdgpu_param_buf_per_se; #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ @@ -109,11 +117,16 @@ extern int amdgpu_vram_page_split; #define AMDGPU_IB_POOL_SIZE 16 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 #define AMDGPUFB_CONN_LIMIT 4 -#define AMDGPU_BIOS_NUM_SCRATCH 8 +#define AMDGPU_BIOS_NUM_SCRATCH 16 /* max number of IP instances */ #define AMDGPU_MAX_SDMA_INSTANCES 2 +/* max number of VMHUB */ +#define AMDGPU_MAX_VMHUBS 2 +#define AMDGPU_MMHUB 0 +#define AMDGPU_GFXHUB 1 + /* hardcode that limit for now */ #define AMDGPU_VA_RESERVED_SIZE (8 << 20) @@ -280,7 +293,7 @@ struct amdgpu_vm_pte_funcs { void (*set_pte_pde)(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, - uint32_t incr, uint32_t flags); + uint32_t incr, uint64_t flags); }; /* provided by the gmc block */ @@ -293,7 +306,18 @@ struct amdgpu_gart_funcs { void *cpu_pt_addr, /* cpu addr of page table */ uint32_t gpu_page_idx, /* pte/pde to update */ uint64_t addr, /* addr to write into pte/pde */ - uint32_t flags); /* access flags */ + uint64_t flags); /* access flags */ + /* enable/disable PRT support */ + void (*set_prt)(struct amdgpu_device *adev, bool enable); + /* set pte flags based per asic */ + uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, + uint32_t flags); +}; + +/* provided by the mc block */ +struct amdgpu_mc_funcs { + /* adjust mc addr in fb for APU case */ + u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr); }; /* provided by the ih block */ @@ -522,6 +546,10 @@ struct amdgpu_gart { struct page **pages; #endif bool ready; + + /* Asic default pte flags */ + uint64_t gart_pte_flags; + const struct amdgpu_gart_funcs *gart_funcs; }; @@ -537,10 +565,25 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int pages); int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, struct page **pagelist, - dma_addr_t *dma_addr, uint32_t flags); + dma_addr_t *dma_addr, uint64_t flags); int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); /* + * VMHUB structures, functions & helpers + */ +struct amdgpu_vmhub { + uint32_t ctx0_ptb_addr_lo32; + uint32_t ctx0_ptb_addr_hi32; + uint32_t vm_inv_eng0_req; + uint32_t vm_inv_eng0_ack; + uint32_t vm_context0_cntl; + uint32_t vm_l2_pro_fault_status; + uint32_t vm_l2_pro_fault_cntl; + uint32_t (*get_invalidate_req)(unsigned int vm_id); + uint32_t (*get_vm_protection_bits)(void); +}; + +/* * GPU MC structures, functions & helpers */ struct amdgpu_mc { @@ -567,6 +610,15 @@ struct amdgpu_mc { uint32_t vram_type; uint32_t srbm_soft_reset; struct amdgpu_mode_mc_save save; + bool prt_warning; + /* apertures */ + u64 shared_aperture_start; + u64 shared_aperture_end; + u64 private_aperture_start; + u64 private_aperture_end; + /* protects concurrent invalidation */ + spinlock_t invalidate_lock; + const struct amdgpu_mc_funcs *mc_funcs; }; /* @@ -601,6 +653,83 @@ struct amdgpu_doorbell { u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ }; +/* + * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space + */ +typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT +{ + /* + * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in + * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. + * Compute related doorbells are allocated from 0x00 to 0x8a + */ + + + /* kernel scheduling */ + AMDGPU_DOORBELL64_KIQ = 0x00, + + /* HSA interface queue and debug queue */ + AMDGPU_DOORBELL64_HIQ = 0x01, + AMDGPU_DOORBELL64_DIQ = 0x02, + + /* Compute engines */ + AMDGPU_DOORBELL64_MEC_RING0 = 0x03, + AMDGPU_DOORBELL64_MEC_RING1 = 0x04, + AMDGPU_DOORBELL64_MEC_RING2 = 0x05, + AMDGPU_DOORBELL64_MEC_RING3 = 0x06, + AMDGPU_DOORBELL64_MEC_RING4 = 0x07, + AMDGPU_DOORBELL64_MEC_RING5 = 0x08, + AMDGPU_DOORBELL64_MEC_RING6 = 0x09, + AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, + + /* User queue doorbell range (128 doorbells) */ + AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, + AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, + + /* Graphics engine */ + AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, + + /* + * Other graphics doorbells can be allocated here: from 0x8c to 0xef + * Graphics voltage island aperture 1 + * default non-graphics QWORD index is 0xF0 - 0xFF inclusive + */ + + /* sDMA engines */ + AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, + AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, + AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, + AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, + + /* Interrupt handler */ + AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ + AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ + AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ + + /* VCN engine use 32 bits doorbell */ + AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ + AMDGPU_DOORBELL64_VCN2_3 = 0xF9, + AMDGPU_DOORBELL64_VCN4_5 = 0xFA, + AMDGPU_DOORBELL64_VCN6_7 = 0xFB, + + /* overlap the doorbell assignment with VCN as they are mutually exclusive + * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD + */ + AMDGPU_DOORBELL64_RING0_1 = 0xF8, + AMDGPU_DOORBELL64_RING2_3 = 0xF9, + AMDGPU_DOORBELL64_RING4_5 = 0xFA, + AMDGPU_DOORBELL64_RING6_7 = 0xFB, + + AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC, + AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD, + AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE, + AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF, + + AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, + AMDGPU_DOORBELL64_INVALID = 0xFFFF +} AMDGPU_DOORBELL64_ASSIGNMENT; + + void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, phys_addr_t *aperture_base, size_t *aperture_size, @@ -699,6 +828,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); struct amdgpu_fpriv { struct amdgpu_vm vm; + struct amdgpu_bo_va *prt_va; struct mutex bo_list_lock; struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; @@ -776,9 +906,12 @@ struct amdgpu_rlc { struct amdgpu_mec { struct amdgpu_bo *hpd_eop_obj; u64 hpd_eop_gpu_addr; + struct amdgpu_bo *mec_fw_obj; + u64 mec_fw_gpu_addr; u32 num_pipe; u32 num_mec; u32 num_queue; + void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; }; struct amdgpu_kiq { @@ -810,7 +943,16 @@ struct amdgpu_rb_config { uint32_t raster_config_1; }; -struct amdgpu_gca_config { +struct gb_addr_config { + uint16_t pipe_interleave_size; + uint8_t num_pipes; + uint8_t max_compress_frags; + uint8_t num_banks; + uint8_t num_se; + uint8_t num_rb_per_se; +}; + +struct amdgpu_gfx_config { unsigned max_shader_engines; unsigned max_tile_pipes; unsigned max_cu_per_sh; @@ -839,7 +981,11 @@ struct amdgpu_gca_config { uint32_t tile_mode_array[32]; uint32_t macrotile_mode_array[16]; + struct gb_addr_config gb_addr_config_fields; struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; + + /* gfx configure feature */ + uint32_t double_offchip_lds_buf; }; struct amdgpu_cu_info { @@ -857,9 +1003,31 @@ struct amdgpu_gfx_funcs { void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); }; +struct amdgpu_ngg_buf { + struct amdgpu_bo *bo; + uint64_t gpu_addr; + uint32_t size; + uint32_t bo_size; +}; + +enum { + PRIM = 0, + POS, + CNTL, + PARAM, + NGG_BUF_MAX +}; + +struct amdgpu_ngg { + struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; + uint32_t gds_reserve_addr; + uint32_t gds_reserve_size; + bool init; +}; + struct amdgpu_gfx { struct mutex gpu_clock_mutex; - struct amdgpu_gca_config config; + struct amdgpu_gfx_config config; struct amdgpu_rlc rlc; struct amdgpu_mec mec; struct amdgpu_kiq kiq; @@ -899,6 +1067,9 @@ struct amdgpu_gfx { /* reset mask */ uint32_t grbm_soft_reset; uint32_t srbm_soft_reset; + bool in_reset; + /* NGG */ + struct amdgpu_ngg ngg; }; int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, @@ -1007,67 +1178,12 @@ struct amdgpu_wb { int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); +int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb); +void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb); void amdgpu_get_pcie_info(struct amdgpu_device *adev); /* - * UVD - */ -#define AMDGPU_DEFAULT_UVD_HANDLES 10 -#define AMDGPU_MAX_UVD_HANDLES 40 -#define AMDGPU_UVD_STACK_SIZE (200*1024) -#define AMDGPU_UVD_HEAP_SIZE (256*1024) -#define AMDGPU_UVD_SESSION_SIZE (50*1024) -#define AMDGPU_UVD_FIRMWARE_OFFSET 256 - -struct amdgpu_uvd { - struct amdgpu_bo *vcpu_bo; - void *cpu_addr; - uint64_t gpu_addr; - unsigned fw_version; - void *saved_bo; - unsigned max_handles; - atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; - struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; - struct delayed_work idle_work; - const struct firmware *fw; /* UVD firmware */ - struct amdgpu_ring ring; - struct amdgpu_irq_src irq; - bool address_64_bit; - bool use_ctx_buf; - struct amd_sched_entity entity; - uint32_t srbm_soft_reset; -}; - -/* - * VCE - */ -#define AMDGPU_MAX_VCE_HANDLES 16 -#define AMDGPU_VCE_FIRMWARE_OFFSET 256 - -#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) -#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) - -struct amdgpu_vce { - struct amdgpu_bo *vcpu_bo; - uint64_t gpu_addr; - unsigned fw_version; - unsigned fb_version; - atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; - struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; - uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; - struct delayed_work idle_work; - struct mutex idle_mutex; - const struct firmware *fw; /* VCE firmware */ - struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; - struct amdgpu_irq_src irq; - unsigned harvest_config; - struct amd_sched_entity entity; - uint32_t srbm_soft_reset; - unsigned num_rings; -}; - -/* * SDMA */ struct amdgpu_sdma_instance { @@ -1095,11 +1211,22 @@ struct amdgpu_sdma { /* * Firmware */ +enum amdgpu_firmware_load_type { + AMDGPU_FW_LOAD_DIRECT = 0, + AMDGPU_FW_LOAD_SMU, + AMDGPU_FW_LOAD_PSP, +}; + struct amdgpu_firmware { struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; - bool smu_load; + enum amdgpu_firmware_load_type load_type; struct amdgpu_bo *fw_buf; unsigned int fw_size; + unsigned int max_ucodes; + /* firmwares are loaded by psp instead of smu from vega10 */ + const struct amdgpu_psp_funcs *funcs; + struct amdgpu_bo *rbuf; + struct mutex mutex; }; /* @@ -1112,10 +1239,6 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); * Testing */ void amdgpu_test_moves(struct amdgpu_device *adev); -void amdgpu_test_ring_sync(struct amdgpu_device *adev, - struct amdgpu_ring *cpA, - struct amdgpu_ring *cpB); -void amdgpu_test_syncing(struct amdgpu_device *adev); /* * MMU Notifier @@ -1202,6 +1325,8 @@ struct amdgpu_asic_funcs { /* static power management */ int (*get_pcie_lanes)(struct amdgpu_device *adev); void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); + /* get config memsize register */ + u32 (*get_config_memsize)(struct amdgpu_device *adev); }; /* @@ -1342,9 +1467,11 @@ struct amdgpu_device { bool have_disp_power_ref; /* BIOS */ + bool is_atom_fw; uint8_t *bios; uint32_t bios_size; struct amdgpu_bo *stollen_vga_memory; + uint32_t bios_scratch_reg_offset; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; /* Register/doorbell mmio */ @@ -1391,6 +1518,7 @@ struct amdgpu_device { struct amdgpu_gart gart; struct amdgpu_dummy_page dummy_page; struct amdgpu_vm_manager vm_manager; + struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; /* memory management */ struct amdgpu_mman mman; @@ -1457,6 +1585,9 @@ struct amdgpu_device { /* firmwares */ struct amdgpu_firmware firmware; + /* PSP */ + struct psp_context psp; + /* GDS */ struct amdgpu_gds gds; @@ -1501,23 +1632,32 @@ void amdgpu_device_fini(struct amdgpu_device *adev); int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, - bool always_indirect); + uint32_t acc_flags); void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, - bool always_indirect); + uint32_t acc_flags); u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); +u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); +void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); /* * Registers read & write functions. */ -#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) -#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) -#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) -#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) -#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) + +#define AMDGPU_REGS_IDX (1<<0) +#define AMDGPU_REGS_NO_KIQ (1<<1) + +#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) +#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) + +#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) +#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) +#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) +#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) +#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) @@ -1556,6 +1696,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) +#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) +#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK @@ -1584,7 +1726,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) { if (ring->count_dw <= 0) DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); - ring->ring[ring->wptr++] = v; + ring->ring[ring->wptr++ & ring->buf_mask] = v; ring->wptr &= ring->ptr_mask; ring->count_dw--; } @@ -1597,9 +1739,9 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *sr if (ring->count_dw < count_dw) { DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); } else { - occupied = ring->wptr & ring->ptr_mask; + occupied = ring->wptr & ring->buf_mask; dst = (void *)&ring->ring[occupied]; - chunk1 = ring->ptr_mask + 1 - occupied; + chunk1 = ring->buf_mask + 1 - occupied; chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; chunk2 = count_dw - chunk1; chunk1 <<= 2; @@ -1650,11 +1792,13 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) +#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) +#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) @@ -1698,6 +1842,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) +#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) /* Common functions */ int amdgpu_gpu_reset(struct amdgpu_device *adev); @@ -1723,7 +1868,7 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, int *last_invalidated); bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); -uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, +uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, struct ttm_mem_reg *mem); void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); @@ -1762,8 +1907,6 @@ void amdgpu_driver_lastclose_kms(struct drm_device *dev); int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); void amdgpu_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv); -void amdgpu_driver_preclose_kms(struct drm_device *dev, - struct drm_file *file_priv); int amdgpu_suspend(struct amdgpu_device *adev); int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c index 857ba0897159..3889486f71fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c @@ -74,9 +74,9 @@ static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) /* Check that we are in spec (not always possible) */ if (n < (128*freq/1500)) - printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); + pr_warn("Calculated ACR N value is too small. You may experience audio problems.\n"); if (n > (128*freq/300)) - printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); + pr_warn("Calculated ACR N value is too large. You may experience audio problems.\n"); *N = n; *CTS = cts; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 56a86dd5789e..f52b1bf3d3d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1748,3 +1748,31 @@ void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) memcpy(dst, src, num_bytes); #endif } + +int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) +{ + struct atom_context *ctx = adev->mode_info.atom_context; + int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); + uint16_t data_offset; + int usage_bytes = 0; + struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; + + if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { + firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); + + DRM_DEBUG("atom firmware requested %08x %dkb\n", + le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), + le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); + + usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; + } + ctx->scratch_size_bytes = 0; + if (usage_bytes == 0) + usage_bytes = 20 * 1024; + /* allocate some scratch memory */ + ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); + if (!ctx->scratch) + return -ENOMEM; + ctx->scratch_size_bytes = usage_bytes; + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 70e9acef5d9c..4e0f488487f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -215,4 +215,7 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, u8 voltage_type, u8 *svd_gpio_id, u8 *svc_gpio_id); + +int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c new file mode 100644 index 000000000000..4b9abd68e04f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -0,0 +1,112 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include <drm/drmP.h> +#include <drm/amdgpu_drm.h> +#include "amdgpu.h" +#include "atomfirmware.h" +#include "amdgpu_atomfirmware.h" +#include "atom.h" + +#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t)) + +bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev) +{ + int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + firmwareinfo); + uint16_t data_offset; + + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, + NULL, NULL, &data_offset)) { + struct atom_firmware_info_v3_1 *firmware_info = + (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + + data_offset); + + if (le32_to_cpu(firmware_info->firmware_capability) & + ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) + return true; + } + return false; +} + +void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) +{ + int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + firmwareinfo); + uint16_t data_offset; + + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, + NULL, NULL, &data_offset)) { + struct atom_firmware_info_v3_1 *firmware_info = + (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + + data_offset); + + adev->bios_scratch_reg_offset = + le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); + } +} + +void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) + adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + i); +} + +void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) + WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]); +} + +int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) +{ + struct atom_context *ctx = adev->mode_info.atom_context; + int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + vram_usagebyfirmware); + uint16_t data_offset; + int usage_bytes = 0; + + if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { + struct vram_usagebyfirmware_v2_1 *firmware_usage = + (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); + + DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n", + le32_to_cpu(firmware_usage->start_address_in_kb), + le16_to_cpu(firmware_usage->used_by_firmware_in_kb), + le16_to_cpu(firmware_usage->used_by_driver_in_kb)); + + usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) * 1024; + } + ctx->scratch_size_bytes = 0; + if (usage_bytes == 0) + usage_bytes = 20 * 1024; + /* allocate some scratch memory */ + ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); + if (!ctx->scratch) + return -ENOMEM; + ctx->scratch_size_bytes = usage_bytes; + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h new file mode 100644 index 000000000000..d0c4dcd7fa96 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_ATOMFIRMWARE_H__ +#define __AMDGPU_ATOMFIRMWARE_H__ + +bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev); +void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev); +void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev); +void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev); +int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index 6c343a933182..c13c51af0b68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -583,8 +583,8 @@ static bool amdgpu_atpx_detect(void) if (has_atpx && vga_count == 2) { acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer); - printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n", - acpi_method_name); + pr_info("vga_switcheroo: detected switching method %s handle\n", + acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; amdgpu_atpx_priv.bridge_pm_usable = d3_supported; amdgpu_atpx_init(); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 821f7cc2051f..365e735f6647 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -86,6 +86,18 @@ static bool check_atom_bios(uint8_t *bios, size_t size) return false; } +static bool is_atom_fw(uint8_t *bios) +{ + uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8); + uint8_t frev = bios[bios_header_start + 2]; + uint8_t crev = bios[bios_header_start + 3]; + + if ((frev < 3) || + ((frev == 3) && (crev < 3))) + return false; + + return true; +} /* If you boot an IGP board with a discrete card as the primary, * the IGP rom is not accessible via the rom bar as the IGP rom is @@ -419,26 +431,30 @@ static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) bool amdgpu_get_bios(struct amdgpu_device *adev) { if (amdgpu_atrm_get_bios(adev)) - return true; + goto success; if (amdgpu_acpi_vfct_bios(adev)) - return true; + goto success; if (igp_read_bios_from_vram(adev)) - return true; + goto success; if (amdgpu_read_bios(adev)) - return true; + goto success; if (amdgpu_read_bios_from_rom(adev)) - return true; + goto success; if (amdgpu_read_disabled_bios(adev)) - return true; + goto success; if (amdgpu_read_platform_bios(adev)) - return true; + goto success; DRM_ERROR("Unable to locate a BIOS ROM\n"); return false; + +success: + adev->is_atom_fw = is_atom_fw(adev->bios); + return true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index d9e5aa4a79ef..1c7e6c28f93a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -571,7 +571,9 @@ static const struct amdgpu_irq_src_funcs cgs_irq_funcs = { .process = cgs_process_irq, }; -static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id, +static int amdgpu_cgs_add_irq_source(void *cgs_device, + unsigned client_id, + unsigned src_id, unsigned num_types, cgs_irq_source_set_func_t set, cgs_irq_handler_func_t handler, @@ -597,7 +599,7 @@ static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src irq_params->handler = handler; irq_params->private_data = private_data; source->data = (void *)irq_params; - ret = amdgpu_irq_add_id(adev, src_id, source); + ret = amdgpu_irq_add_id(adev, client_id, src_id, source); if (ret) { kfree(irq_params); kfree(source); @@ -606,16 +608,26 @@ static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src return ret; } -static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type) +static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id, + unsigned src_id, unsigned type) { CGS_FUNC_ADEV; - return amdgpu_irq_get(adev, adev->irq.sources[src_id], type); + + if (!adev->irq.client[client_id].sources) + return -EINVAL; + + return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type); } -static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type) +static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id, + unsigned src_id, unsigned type) { CGS_FUNC_ADEV; - return amdgpu_irq_put(adev, adev->irq.sources[src_id], type); + + if (!adev->irq.client[client_id].sources) + return -EINVAL; + + return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type); } static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, @@ -825,9 +837,8 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, uint32_t ucode_start_address; const uint8_t *src; const struct smc_firmware_header_v1_0 *hdr; - - if (CGS_UCODE_ID_SMU_SK == type) - amdgpu_cgs_rel_firmware(cgs_device, CGS_UCODE_ID_SMU); + const struct common_firmware_header *header; + struct amdgpu_firmware_info *ucode = NULL; if (!adev->pm.fw) { switch (adev->asic_type) { @@ -889,6 +900,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, case CHIP_POLARIS12: strcpy(fw_name, "amdgpu/polaris12_smc.bin"); break; + case CHIP_VEGA10: + strcpy(fw_name, "amdgpu/vega10_smc.bin"); + break; default: DRM_ERROR("SMC firmware not supported\n"); return -EINVAL; @@ -907,6 +921,15 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, adev->pm.fw = NULL; return err; } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; + ucode->ucode_id = AMDGPU_UCODE_ID_SMC; + ucode->fw = adev->pm.fw; + header = (const struct common_firmware_header *)ucode->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } } hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 99424cb8020b..97f661372a1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -82,6 +82,15 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, return -EINVAL; } break; + case AMDGPU_HW_IP_UVD_ENC: + if (ring < adev->uvd.num_enc_rings){ + *out_ring = &adev->uvd.ring_enc[ring]; + } else { + DRM_ERROR("only %d UVD ENC rings are supported\n", + adev->uvd.num_enc_rings); + return -EINVAL; + } + break; } if (!(*out_ring && (*out_ring)->adev)) { @@ -759,23 +768,33 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo amdgpu_bo_unref(&parser->uf_entry.robj); } -static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, - struct amdgpu_vm *vm) +static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) { struct amdgpu_device *adev = p->adev; + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; int i, r; - r = amdgpu_vm_update_page_directory(adev, vm); + r = amdgpu_vm_update_directories(adev, vm); + if (r) + return r; + + r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update); if (r) return r; - r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence); + r = amdgpu_vm_clear_freed(adev, vm, NULL); if (r) return r; - r = amdgpu_vm_clear_freed(adev, vm); + r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); + if (r) + return r; + + r = amdgpu_sync_fence(adev, &p->job->sync, + fpriv->prt_va->last_pt_update); if (r) return r; @@ -853,9 +872,9 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, } if (p->job->vm) { - p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); + p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo); - r = amdgpu_bo_vm_update_pte(p, vm); + r = amdgpu_bo_vm_update_pte(p); if (r) return r; } @@ -869,7 +888,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; int i, j; - int r; + int r, ce_preempt = 0, de_preempt = 0; for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { struct amdgpu_cs_chunk *chunk; @@ -884,13 +903,26 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) continue; + if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) { + if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) { + if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) + ce_preempt++; + else + de_preempt++; + } + + /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */ + if (ce_preempt > 1 || de_preempt > 1) + return -EINVAL; + } + r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, chunk_ib->ip_instance, chunk_ib->ring, &ring); if (r) return r; - if (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) { + if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) { parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT; if (!parser->ctx->preamble_presented) { parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index de0cf3315484..93061a439dbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -40,6 +40,7 @@ #include "amdgpu_i2c.h" #include "atom.h" #include "amdgpu_atombios.h" +#include "amdgpu_atomfirmware.h" #include "amd_pcie.h" #ifdef CONFIG_DRM_AMDGPU_SI #include "si.h" @@ -48,9 +49,11 @@ #include "cik.h" #endif #include "vi.h" +#include "soc15.h" #include "bif/bif_4_1_d.h" #include <linux/pci.h> #include <linux/firmware.h> +#include "amdgpu_pm.h" static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); @@ -74,6 +77,7 @@ static const char *amdgpu_asic_name[] = { "POLARIS10", "POLARIS11", "POLARIS12", + "VEGA10", "LAST", }; @@ -90,16 +94,16 @@ bool amdgpu_device_is_px(struct drm_device *dev) * MMIO register access helper functions. */ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, - bool always_indirect) + uint32_t acc_flags) { uint32_t ret; - if (amdgpu_sriov_runtime(adev)) { + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { BUG_ON(in_interrupt()); return amdgpu_virt_kiq_rreg(adev, reg); } - if ((reg * 4) < adev->rmmio_size && !always_indirect) + if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); else { unsigned long flags; @@ -114,16 +118,16 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, } void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, - bool always_indirect) + uint32_t acc_flags) { trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); - if (amdgpu_sriov_runtime(adev)) { + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) { BUG_ON(in_interrupt()); return amdgpu_virt_kiq_wreg(adev, reg, v); } - if ((reg * 4) < adev->rmmio_size && !always_indirect) + if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); else { unsigned long flags; @@ -195,6 +199,44 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) } /** + * amdgpu_mm_rdoorbell64 - read a doorbell Qword + * + * @adev: amdgpu_device pointer + * @index: doorbell index + * + * Returns the value in the doorbell aperture at the + * requested doorbell index (VEGA10+). + */ +u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) +{ + if (index < adev->doorbell.num_doorbells) { + return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); + } else { + DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); + return 0; + } +} + +/** + * amdgpu_mm_wdoorbell64 - write a doorbell Qword + * + * @adev: amdgpu_device pointer + * @index: doorbell index + * @v: value to write + * + * Writes @v to the doorbell aperture at the + * requested doorbell index (VEGA10+). + */ +void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) +{ + if (index < adev->doorbell.num_doorbells) { + atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); + } else { + DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); + } +} + +/** * amdgpu_invalid_rreg - dummy reg read function * * @adev: amdgpu device pointer @@ -516,6 +558,29 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) } /** + * amdgpu_wb_get_64bit - Allocate a wb entry + * + * @adev: amdgpu_device pointer + * @wb: wb index + * + * Allocate a wb slot for use by the driver (all asics). + * Returns 0 on success or -EINVAL on failure. + */ +int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) +{ + unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, + adev->wb.num_wb, 0, 2, 7, 0); + if ((offset + 1) < adev->wb.num_wb) { + __set_bit(offset, adev->wb.used); + __set_bit(offset + 1, adev->wb.used); + *wb = offset; + return 0; + } else { + return -EINVAL; + } +} + +/** * amdgpu_wb_free - Free a wb entry * * @adev: amdgpu_device pointer @@ -530,6 +595,22 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) } /** + * amdgpu_wb_free_64bit - Free a wb entry + * + * @adev: amdgpu_device pointer + * @wb: wb index + * + * Free a wb slot allocated for use by the driver (all asics) + */ +void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) +{ + if ((wb + 1) < adev->wb.num_wb) { + __clear_bit(wb, adev->wb.used); + __clear_bit(wb + 1, adev->wb.used); + } +} + +/** * amdgpu_vram_location - try to find VRAM location * @adev: amdgpu device structure holding all necessary informations * @mc: memory controller structure holding memory informations @@ -602,7 +683,7 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) dev_warn(adev->dev, "limiting GTT\n"); mc->gtt_size = size_bf; } - mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; + mc->gtt_start = 0; } else { if (mc->gtt_size > size_af) { dev_warn(adev->dev, "limiting GTT\n"); @@ -636,9 +717,9 @@ bool amdgpu_need_post(struct amdgpu_device *adev) return true; } /* then check MEM_SIZE, in case the crtcs are off */ - reg = RREG32(mmCONFIG_MEMSIZE); + reg = amdgpu_asic_get_config_memsize(adev); - if (reg) + if ((reg != 0) && (reg != 0xffffffff)) return false; return true; @@ -915,8 +996,13 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) } mutex_init(&adev->mode_info.atom_context->mutex); - amdgpu_atombios_scratch_regs_init(adev); - amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); + if (adev->is_atom_fw) { + amdgpu_atomfirmware_scratch_regs_init(adev); + amdgpu_atomfirmware_allocate_fb_scratch(adev); + } else { + amdgpu_atombios_scratch_regs_init(adev); + amdgpu_atombios_allocate_fb_scratch(adev); + } return 0; } @@ -954,6 +1040,45 @@ static bool amdgpu_check_pot_argument(int arg) return (arg & (arg - 1)) == 0; } +static void amdgpu_get_block_size(struct amdgpu_device *adev) +{ + /* from AI, asic starts to support multiple level VMPT */ + if (adev->asic_type >= CHIP_VEGA10) { + if (amdgpu_vm_block_size != 9) + dev_warn(adev->dev, + "Multi-VMPT limits block size to one page!\n"); + amdgpu_vm_block_size = 9; + return; + } + /* defines number of bits in page table versus page directory, + * a page is 4KB so we have 12 bits offset, minimum 9 bits in the + * page table and the remaining bits are in the page directory */ + if (amdgpu_vm_block_size == -1) { + + /* Total bits covered by PD + PTs */ + unsigned bits = ilog2(amdgpu_vm_size) + 18; + + /* Make sure the PD is 4K in size up to 8GB address space. + Above that split equal between PD and PTs */ + if (amdgpu_vm_size <= 8) + amdgpu_vm_block_size = bits - 9; + else + amdgpu_vm_block_size = (bits + 3) / 2; + + } else if (amdgpu_vm_block_size < 9) { + dev_warn(adev->dev, "VM page table size (%d) too small\n", + amdgpu_vm_block_size); + amdgpu_vm_block_size = 9; + } + + if (amdgpu_vm_block_size > 24 || + (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { + dev_warn(adev->dev, "VM page table size (%d) too large\n", + amdgpu_vm_block_size); + amdgpu_vm_block_size = 9; + } +} + /** * amdgpu_check_arguments - validate module params * @@ -1004,33 +1129,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_vm_size = 8; } - /* defines number of bits in page table versus page directory, - * a page is 4KB so we have 12 bits offset, minimum 9 bits in the - * page table and the remaining bits are in the page directory */ - if (amdgpu_vm_block_size == -1) { - - /* Total bits covered by PD + PTs */ - unsigned bits = ilog2(amdgpu_vm_size) + 18; - - /* Make sure the PD is 4K in size up to 8GB address space. - Above that split equal between PD and PTs */ - if (amdgpu_vm_size <= 8) - amdgpu_vm_block_size = bits - 9; - else - amdgpu_vm_block_size = (bits + 3) / 2; - - } else if (amdgpu_vm_block_size < 9) { - dev_warn(adev->dev, "VM page table size (%d) too small\n", - amdgpu_vm_block_size); - amdgpu_vm_block_size = 9; - } - - if (amdgpu_vm_block_size > 24 || - (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { - dev_warn(adev->dev, "VM page table size (%d) too large\n", - amdgpu_vm_block_size); - amdgpu_vm_block_size = 9; - } + amdgpu_get_block_size(adev); if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { @@ -1059,7 +1158,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero if (state == VGA_SWITCHEROO_ON) { unsigned d3_delay = dev->pdev->d3_delay; - printk(KERN_INFO "amdgpu: switched on\n"); + pr_info("amdgpu: switched on\n"); /* don't suspend or resume card normally */ dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; @@ -1070,7 +1169,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero dev->switch_power_state = DRM_SWITCH_POWER_ON; drm_kms_helper_poll_enable(dev); } else { - printk(KERN_INFO "amdgpu: switched off\n"); + pr_info("amdgpu: switched off\n"); drm_kms_helper_poll_disable(dev); dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; amdgpu_device_suspend(dev, true, true); @@ -1114,13 +1213,15 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].version->type == block_type) { - r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, - state); - if (r) - return r; - break; - } + if (adev->ip_blocks[i].version->type != block_type) + continue; + if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) + continue; + r = adev->ip_blocks[i].version->funcs->set_clockgating_state( + (void *)adev, state); + if (r) + DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); } return r; } @@ -1134,13 +1235,15 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].version->type == block_type) { - r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, - state); - if (r) - return r; - break; - } + if (adev->ip_blocks[i].version->type != block_type) + continue; + if (!adev->ip_blocks[i].version->funcs->set_powergating_state) + continue; + r = adev->ip_blocks[i].version->funcs->set_powergating_state( + (void *)adev, state); + if (r) + DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); } return r; } @@ -1345,6 +1448,13 @@ static int amdgpu_early_init(struct amdgpu_device *adev) return r; break; #endif + case CHIP_VEGA10: + adev->family = AMDGPU_FAMILY_AI; + + r = soc15_set_ip_blocks(adev); + if (r) + return r; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -1476,6 +1586,9 @@ static int amdgpu_late_init(struct amdgpu_device *adev) } } + amdgpu_dpm_enable_uvd(adev, false); + amdgpu_dpm_enable_vce(adev, false); + return 0; } @@ -1607,6 +1720,53 @@ int amdgpu_suspend(struct amdgpu_device *adev) return 0; } +static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) + r = adev->ip_blocks[i].version->funcs->hw_init(adev); + + if (r) { + DRM_ERROR("resume of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } + } + + return 0; +} + +static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ) + continue; + + r = adev->ip_blocks[i].version->funcs->hw_init(adev); + if (r) { + DRM_ERROR("resume of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } + } + + return 0; +} + static int amdgpu_resume(struct amdgpu_device *adev) { int i, r; @@ -1627,8 +1787,13 @@ static int amdgpu_resume(struct amdgpu_device *adev) static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) { - if (amdgpu_atombios_has_gpu_virtualization_table(adev)) - adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; + if (adev->is_atom_fw) { + if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) + adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; + } else { + if (amdgpu_atombios_has_gpu_virtualization_table(adev)) + adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; + } } /** @@ -1693,6 +1858,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, * can recall function without having locking issues */ mutex_init(&adev->vm_manager.lock); atomic_set(&adev->irq.ih.lock, 0); + mutex_init(&adev->firmware.mutex); mutex_init(&adev->pm.mutex); mutex_init(&adev->gfx.gpu_clock_mutex); mutex_init(&adev->srbm_mutex); @@ -1799,14 +1965,16 @@ int amdgpu_device_init(struct amdgpu_device *adev, DRM_INFO("GPU post is not needed\n"); } - /* Initialize clocks */ - r = amdgpu_atombios_get_clock_info(adev); - if (r) { - dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); - goto failed; + if (!adev->is_atom_fw) { + /* Initialize clocks */ + r = amdgpu_atombios_get_clock_info(adev); + if (r) { + dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); + return r; + } + /* init i2c buses */ + amdgpu_atombios_i2c_init(adev); } - /* init i2c buses */ - amdgpu_atombios_i2c_init(adev); /* Fence driver */ r = amdgpu_fence_driver_init(adev); @@ -1835,8 +2003,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); - amdgpu_fbdev_init(adev); - r = amdgpu_ib_pool_init(adev); if (r) { dev_err(adev->dev, "IB initialization failed (%d).\n", r); @@ -1847,21 +2013,19 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (r) DRM_ERROR("ib ring test failed (%d).\n", r); + amdgpu_fbdev_init(adev); + r = amdgpu_gem_debugfs_init(adev); - if (r) { + if (r) DRM_ERROR("registering gem debugfs failed (%d).\n", r); - } r = amdgpu_debugfs_regs_init(adev); - if (r) { + if (r) DRM_ERROR("registering register debugfs failed (%d).\n", r); - } r = amdgpu_debugfs_firmware_init(adev); - if (r) { + if (r) DRM_ERROR("registering firmware debugfs failed (%d).\n", r); - return r; - } if ((amdgpu_testing & 1)) { if (adev->accel_working) @@ -1869,12 +2033,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, else DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); } - if ((amdgpu_testing & 2)) { - if (adev->accel_working) - amdgpu_test_syncing(adev); - else - DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); - } if (amdgpu_benchmarking) { if (adev->accel_working) amdgpu_benchmark(adev, amdgpu_benchmarking); @@ -2020,7 +2178,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) */ amdgpu_bo_evict_vram(adev); - amdgpu_atombios_scratch_regs_save(adev); + if (adev->is_atom_fw) + amdgpu_atomfirmware_scratch_regs_save(adev); + else + amdgpu_atombios_scratch_regs_save(adev); pci_save_state(dev->pdev); if (suspend) { /* Shut down the device */ @@ -2072,7 +2233,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) return r; } } - amdgpu_atombios_scratch_regs_restore(adev); + if (adev->is_atom_fw) + amdgpu_atomfirmware_scratch_regs_restore(adev); + else + amdgpu_atombios_scratch_regs_restore(adev); /* post card */ if (amdgpu_need_post(adev)) { @@ -2286,6 +2450,117 @@ err: } /** + * amdgpu_sriov_gpu_reset - reset the asic + * + * @adev: amdgpu device pointer + * @voluntary: if this reset is requested by guest. + * (true means by guest and false means by HYPERVISOR ) + * + * Attempt the reset the GPU if it has hung (all asics). + * for SRIOV case. + * Returns 0 for success or an error on failure. + */ +int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary) +{ + int i, r = 0; + int resched; + struct amdgpu_bo *bo, *tmp; + struct amdgpu_ring *ring; + struct dma_fence *fence = NULL, *next = NULL; + + mutex_lock(&adev->virt.lock_reset); + atomic_inc(&adev->gpu_reset_counter); + adev->gfx.in_reset = true; + + /* block TTM */ + resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); + + /* block scheduler */ + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + + kthread_park(ring->sched.thread); + amd_sched_hw_job_reset(&ring->sched); + } + + /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ + amdgpu_fence_driver_force_completion(adev); + + /* request to take full control of GPU before re-initialization */ + if (voluntary) + amdgpu_virt_reset_gpu(adev); + else + amdgpu_virt_request_full_gpu(adev, true); + + + /* Resume IP prior to SMC */ + amdgpu_sriov_reinit_early(adev); + + /* we need recover gart prior to run SMC/CP/SDMA resume */ + amdgpu_ttm_recover_gart(adev); + + /* now we are okay to resume SMC/CP/SDMA */ + amdgpu_sriov_reinit_late(adev); + + amdgpu_irq_gpu_reset_resume_helper(adev); + + if (amdgpu_ib_ring_tests(adev)) + dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); + + /* release full control of GPU after ib test */ + amdgpu_virt_release_full_gpu(adev, true); + + DRM_INFO("recover vram bo from shadow\n"); + + ring = adev->mman.buffer_funcs_ring; + mutex_lock(&adev->shadow_list_lock); + list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { + amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); + if (fence) { + r = dma_fence_wait(fence, false); + if (r) { + WARN(r, "recovery from shadow isn't completed\n"); + break; + } + } + + dma_fence_put(fence); + fence = next; + } + mutex_unlock(&adev->shadow_list_lock); + + if (fence) { + r = dma_fence_wait(fence, false); + if (r) + WARN(r, "recovery from shadow isn't completed\n"); + } + dma_fence_put(fence); + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring || !ring->sched.thread) + continue; + + amd_sched_job_recovery(&ring->sched); + kthread_unpark(ring->sched.thread); + } + + drm_helper_resume_force_mode(adev->ddev); + ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); + if (r) { + /* bad news, how to tell it to userspace ? */ + dev_info(adev->dev, "GPU reset failed\n"); + } + + adev->gfx.in_reset = false; + mutex_unlock(&adev->virt.lock_reset); + return r; +} + +/** * amdgpu_gpu_reset - reset the asic * * @adev: amdgpu device pointer @@ -2300,7 +2575,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) bool need_full_reset; if (amdgpu_sriov_vf(adev)) - return 0; + return amdgpu_sriov_gpu_reset(adev, true); if (!amdgpu_check_soft_reset(adev)) { DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); @@ -2346,9 +2621,15 @@ retry: amdgpu_display_stop_mc_access(adev, &save); amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); } - amdgpu_atombios_scratch_regs_save(adev); + if (adev->is_atom_fw) + amdgpu_atomfirmware_scratch_regs_save(adev); + else + amdgpu_atombios_scratch_regs_save(adev); r = amdgpu_asic_reset(adev); - amdgpu_atombios_scratch_regs_restore(adev); + if (adev->is_atom_fw) + amdgpu_atomfirmware_scratch_regs_restore(adev); + else + amdgpu_atombios_scratch_regs_restore(adev); /* post card */ amdgpu_atom_asic_init(adev->mode_info.atom_context); @@ -2387,7 +2668,7 @@ retry: if (fence) { r = dma_fence_wait(fence, false); if (r) { - WARN(r, "recovery from shadow isn't comleted\n"); + WARN(r, "recovery from shadow isn't completed\n"); break; } } @@ -2399,7 +2680,7 @@ retry: if (fence) { r = dma_fence_wait(fence, false); if (r) - WARN(r, "recovery from shadow isn't comleted\n"); + WARN(r, "recovery from shadow isn't completed\n"); } dma_fence_put(fence); } @@ -2954,24 +3235,42 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { struct amdgpu_device *adev = file_inode(f)->i_private; - int idx, r; - int32_t value; + int idx, x, outsize, r, valuesize; + uint32_t values[16]; - if (size != 4 || *pos & 0x3) + if (size & 3 || *pos & 0x3) + return -EINVAL; + + if (amdgpu_dpm == 0) return -EINVAL; /* convert offset to sensor number */ idx = *pos >> 2; + valuesize = sizeof(values); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) - r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value); + r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize); + else if (adev->pm.funcs && adev->pm.funcs->read_sensor) + r = adev->pm.funcs->read_sensor(adev, idx, &values[0], + &valuesize); else return -EINVAL; - if (!r) - r = put_user(value, (int32_t *)buf); + if (size > valuesize) + return -EINVAL; + + outsize = 0; + x = 0; + if (!r) { + while (size) { + r = put_user(values[x++], (int32_t *)buf); + buf += 4; + size -= 4; + outsize += 4; + } + } - return !r ? 4 : r; + return !r ? outsize : r; } static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 6ca0333ca4c0..38e9b0d3659a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -31,86 +31,88 @@ void amdgpu_dpm_print_class_info(u32 class, u32 class2) { - printk("\tui class: "); + const char *s; + switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { case ATOM_PPLIB_CLASSIFICATION_UI_NONE: default: - printk("none\n"); + s = "none"; break; case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: - printk("battery\n"); + s = "battery"; break; case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: - printk("balanced\n"); + s = "balanced"; break; case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: - printk("performance\n"); + s = "performance"; break; } - printk("\tinternal class: "); + printk("\tui class: %s\n", s); + printk("\tinternal class:"); if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && (class2 == 0)) - printk("none"); + pr_cont(" none"); else { if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) - printk("boot "); + pr_cont(" boot"); if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) - printk("thermal "); + pr_cont(" thermal"); if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) - printk("limited_pwr "); + pr_cont(" limited_pwr"); if (class & ATOM_PPLIB_CLASSIFICATION_REST) - printk("rest "); + pr_cont(" rest"); if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) - printk("forced "); + pr_cont(" forced"); if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) - printk("3d_perf "); + pr_cont(" 3d_perf"); if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) - printk("ovrdrv "); + pr_cont(" ovrdrv"); if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) - printk("uvd "); + pr_cont(" uvd"); if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) - printk("3d_low "); + pr_cont(" 3d_low"); if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) - printk("acpi "); + pr_cont(" acpi"); if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) - printk("uvd_hd2 "); + pr_cont(" uvd_hd2"); if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) - printk("uvd_hd "); + pr_cont(" uvd_hd"); if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) - printk("uvd_sd "); + pr_cont(" uvd_sd"); if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) - printk("limited_pwr2 "); + pr_cont(" limited_pwr2"); if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) - printk("ulv "); + pr_cont(" ulv"); if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) - printk("uvd_mvc "); + pr_cont(" uvd_mvc"); } - printk("\n"); + pr_cont("\n"); } void amdgpu_dpm_print_cap_info(u32 caps) { - printk("\tcaps: "); + printk("\tcaps:"); if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) - printk("single_disp "); + pr_cont(" single_disp"); if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) - printk("video "); + pr_cont(" video"); if (caps & ATOM_PPLIB_DISALLOW_ON_DC) - printk("no_dc "); - printk("\n"); + pr_cont(" no_dc"); + pr_cont("\n"); } void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, struct amdgpu_ps *rps) { - printk("\tstatus: "); + printk("\tstatus:"); if (rps == adev->pm.dpm.current_ps) - printk("c "); + pr_cont(" c"); if (rps == adev->pm.dpm.requested_ps) - printk("r "); + pr_cont(" r"); if (rps == adev->pm.dpm.boot_ps) - printk("b "); - printk("\n"); + pr_cont(" b"); + pr_cont("\n"); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index fa2b55681422..8c96a4caa715 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -270,8 +270,18 @@ struct amdgpu_dpm_funcs { struct amdgpu_ps *cps, struct amdgpu_ps *rps, bool *equal); + int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value, + int *size); struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx); + int (*reset_power_profile_state)(struct amdgpu_device *adev, + struct amd_pp_profile *request); + int (*get_power_profile_state)(struct amdgpu_device *adev, + struct amd_pp_profile *query); + int (*set_power_profile_state)(struct amdgpu_device *adev, + struct amd_pp_profile *request); + int (*switch_power_profile)(struct amdgpu_device *adev, + enum amd_pp_profile_type type); }; #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) @@ -282,10 +292,10 @@ struct amdgpu_dpm_funcs { #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) -#define amdgpu_dpm_read_sensor(adev, idx, value) \ +#define amdgpu_dpm_read_sensor(adev, idx, value, size) \ ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \ - -EINVAL) + (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value), (size)) : \ + (adev)->pm.funcs->read_sensor((adev), (idx), (value), (size))) #define amdgpu_dpm_get_temperature(adev) \ ((adev)->pp_enabled ? \ @@ -388,6 +398,22 @@ struct amdgpu_dpm_funcs { (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \ (adev)->pm.dpm.forced_level) +#define amdgpu_dpm_reset_power_profile_state(adev, request) \ + ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ + (adev)->powerplay.pp_handle, request)) + +#define amdgpu_dpm_get_power_profile_state(adev, query) \ + ((adev)->powerplay.pp_funcs->get_power_profile_state(\ + (adev)->powerplay.pp_handle, query)) + +#define amdgpu_dpm_set_power_profile_state(adev, request) \ + ((adev)->powerplay.pp_funcs->set_power_profile_state(\ + (adev)->powerplay.pp_handle, request)) + +#define amdgpu_dpm_switch_power_profile(adev, type) \ + ((adev)->powerplay.pp_funcs->switch_power_profile(\ + (adev)->powerplay.pp_handle, type)) + struct amdgpu_dpm { struct amdgpu_ps *ps; /* number of valid power states */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b76cd699eb0d..400917fd7486 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -60,9 +60,12 @@ * - 3.8.0 - Add support raster config init in the kernel * - 3.9.0 - Add support for memory query info about VRAM and GTT. * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags + * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). + * - 3.12.0 - Add query for double offchip LDS buffers + * - 3.13.0 - Add PRT support */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 10 +#define KMS_DRIVER_MINOR 13 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; @@ -77,7 +80,7 @@ int amdgpu_pcie_gen2 = -1; int amdgpu_msi = -1; int amdgpu_lockup_timeout = 0; int amdgpu_dpm = -1; -int amdgpu_smc_load_fw = 1; +int amdgpu_fw_load_type = -1; int amdgpu_aspm = -1; int amdgpu_runtime_pm = -1; unsigned amdgpu_ip_block_mask = 0xffffffff; @@ -100,6 +103,11 @@ unsigned amdgpu_pg_mask = 0xffffffff; char *amdgpu_disable_cu = NULL; char *amdgpu_virtual_display = NULL; unsigned amdgpu_pp_feature_mask = 0xffffffff; +int amdgpu_ngg = 0; +int amdgpu_prim_buf_per_se = 0; +int amdgpu_pos_buf_per_se = 0; +int amdgpu_cntl_sb_buf_per_se = 0; +int amdgpu_param_buf_per_se = 0; MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -137,8 +145,8 @@ module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(dpm, amdgpu_dpm, int, 0444); -MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); -module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); +MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); +module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(aspm, amdgpu_aspm, int, 0444); @@ -207,6 +215,22 @@ MODULE_PARM_DESC(virtual_display, "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); +MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); +module_param_named(ngg, amdgpu_ngg, int, 0444); + +MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); +module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); + +MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); +module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); + +MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); +module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); + +MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); +module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); + + static const struct pci_device_id pciidlist[] = { #ifdef CONFIG_DRM_AMDGPU_SI {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, @@ -409,6 +433,7 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, + {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, @@ -423,7 +448,14 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, - + /* Vega 10 */ + {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, {0, 0, 0} }; @@ -686,7 +718,6 @@ static struct drm_driver kms_driver = { DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, .load = amdgpu_driver_load_kms, .open = amdgpu_driver_open_kms, - .preclose = amdgpu_driver_preclose_kms, .postclose = amdgpu_driver_postclose_kms, .lastclose = amdgpu_driver_lastclose_kms, .set_busid = drm_pci_set_busid, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 72505b15dd13..a48142d930c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -147,11 +147,11 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, ret = amdgpu_gem_object_create(adev, aligned_size, 0, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED, true, &gobj); if (ret) { - printk(KERN_ERR "failed to allocate framebuffer (%d)\n", - aligned_size); + pr_err("failed to allocate framebuffer (%d)\n", aligned_size); return -ENOMEM; } abo = gem_to_amdgpu_bo(gobj); @@ -241,8 +241,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper, /* setup helper */ rfbdev->helper.fb = fb; - memset_io(abo->kptr, 0x0, amdgpu_bo_size(abo)); - strcpy(info->fix.id, "amdgpudrmfb"); drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 964d2a946ed5..6d691abe889c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -229,7 +229,8 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, unsigned p; int i, j; u64 page_base; - uint32_t flags = AMDGPU_PTE_SYSTEM; + /* Starting from VEGA10, system bit must be 0 to mean invalid. */ + uint64_t flags = 0; if (!adev->gart.ready) { WARN(1, "trying to unbind memory from uninitialized GART !\n"); @@ -271,7 +272,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, */ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, struct page **pagelist, dma_addr_t *dma_addr, - uint32_t flags) + uint64_t flags) { unsigned t; unsigned p; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 106cf83c2e6b..f85520d4e711 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -152,6 +152,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct amdgpu_bo_va *bo_va; + struct dma_fence *fence = NULL; int r; INIT_LIST_HEAD(&list); @@ -173,6 +174,17 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, if (bo_va) { if (--bo_va->ref_count == 0) { amdgpu_vm_bo_rmv(adev, bo_va); + + r = amdgpu_vm_clear_freed(adev, vm, &fence); + if (unlikely(r)) { + dev_err(adev->dev, "failed to clear page " + "tables on GEM object close (%d)\n", r); + } + + if (fence) { + amdgpu_bo_fence(bo, fence, true); + dma_fence_put(fence); + } } } ttm_eu_backoff_reservation(&ticket, &list); @@ -507,14 +519,16 @@ static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo) * amdgpu_gem_va_update_vm -update the bo_va in its VM * * @adev: amdgpu_device pointer + * @vm: vm to update * @bo_va: bo_va to update * @list: validation list - * @operation: map or unmap + * @operation: map, unmap or clear * * Update the bo_va directly after setting its address. Errors are not * vital here, so they are not reported back to userspace. */ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, + struct amdgpu_vm *vm, struct amdgpu_bo_va *bo_va, struct list_head *list, uint32_t operation) @@ -529,20 +543,21 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, goto error; } - r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check, + r = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_va_check, NULL); if (r) goto error; - r = amdgpu_vm_update_page_directory(adev, bo_va->vm); + r = amdgpu_vm_update_directories(adev, vm); if (r) goto error; - r = amdgpu_vm_clear_freed(adev, bo_va->vm); + r = amdgpu_vm_clear_freed(adev, vm, NULL); if (r) goto error; - if (operation == AMDGPU_VA_OP_MAP) + if (operation == AMDGPU_VA_OP_MAP || + operation == AMDGPU_VA_OP_REPLACE) r = amdgpu_vm_bo_update(adev, bo_va, false); error: @@ -553,6 +568,12 @@ error: int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | + AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | + AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; + const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | + AMDGPU_VM_PAGE_PRT; + struct drm_amdgpu_gem_va *args = data; struct drm_gem_object *gobj; struct amdgpu_device *adev = dev->dev_private; @@ -563,7 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head list; - uint32_t invalid_flags, va_flags = 0; + uint64_t va_flags; int r = 0; if (!adev->vm_manager.enabled) @@ -577,17 +598,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } - invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE | - AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); - if ((args->flags & invalid_flags)) { - dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", - args->flags, invalid_flags); + if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { + dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", + args->flags); return -EINVAL; } switch (args->operation) { case AMDGPU_VA_OP_MAP: case AMDGPU_VA_OP_UNMAP: + case AMDGPU_VA_OP_CLEAR: + case AMDGPU_VA_OP_REPLACE: break; default: dev_err(&dev->pdev->dev, "unsupported operation %d\n", @@ -595,38 +616,47 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } - gobj = drm_gem_object_lookup(filp, args->handle); - if (gobj == NULL) - return -ENOENT; - abo = gem_to_amdgpu_bo(gobj); INIT_LIST_HEAD(&list); - tv.bo = &abo->tbo; - tv.shared = false; - list_add(&tv.head, &list); + if ((args->operation != AMDGPU_VA_OP_CLEAR) && + !(args->flags & AMDGPU_VM_PAGE_PRT)) { + gobj = drm_gem_object_lookup(filp, args->handle); + if (gobj == NULL) + return -ENOENT; + abo = gem_to_amdgpu_bo(gobj); + tv.bo = &abo->tbo; + tv.shared = false; + list_add(&tv.head, &list); + } else { + gobj = NULL; + abo = NULL; + } amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); - if (r) { - drm_gem_object_unreference_unlocked(gobj); - return r; - } + if (r) + goto error_unref; - bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); - if (!bo_va) { - ttm_eu_backoff_reservation(&ticket, &list); - drm_gem_object_unreference_unlocked(gobj); - return -ENOENT; + if (abo) { + bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); + if (!bo_va) { + r = -ENOENT; + goto error_backoff; + } + } else if (args->operation != AMDGPU_VA_OP_CLEAR) { + bo_va = fpriv->prt_va; + } else { + bo_va = NULL; } switch (args->operation) { case AMDGPU_VA_OP_MAP: - if (args->flags & AMDGPU_VM_PAGE_READABLE) - va_flags |= AMDGPU_PTE_READABLE; - if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) - va_flags |= AMDGPU_PTE_WRITEABLE; - if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) - va_flags |= AMDGPU_PTE_EXECUTABLE; + r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, + args->map_size); + if (r) + goto error_backoff; + + va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, args->offset_in_bo, args->map_size, va_flags); @@ -634,14 +664,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, case AMDGPU_VA_OP_UNMAP: r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); break; + + case AMDGPU_VA_OP_CLEAR: + r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, + args->va_address, + args->map_size); + break; + case AMDGPU_VA_OP_REPLACE: + r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, + args->map_size); + if (r) + goto error_backoff; + + va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); + r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, + args->offset_in_bo, args->map_size, + va_flags); + break; default: break; } - if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && - !amdgpu_vm_debug) - amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation); + if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) + amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, + args->operation); + +error_backoff: ttm_eu_backoff_reservation(&ticket, &list); +error_unref: drm_gem_object_unreference_unlocked(gobj); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index e02a70dd37b5..aab857d89d03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -161,9 +161,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return r; } - if (ring->funcs->init_cond_exec) - patch_offset = amdgpu_ring_init_cond_exec(ring); - if (vm) { r = amdgpu_vm_flush(ring, job); if (r) { @@ -172,7 +169,14 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, } } - if (ring->funcs->emit_hdp_flush) + if (ring->funcs->init_cond_exec) + patch_offset = amdgpu_ring_init_cond_exec(ring); + + if (ring->funcs->emit_hdp_flush +#ifdef CONFIG_X86_64 + && !(adev->flags & AMD_IS_APU) +#endif + ) amdgpu_ring_emit_hdp_flush(ring); skip_preamble = ring->current_ctx == fence_ctx; @@ -202,7 +206,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, need_ctx_switch = false; } - if (ring->funcs->emit_hdp_invalidate) + if (ring->funcs->emit_hdp_invalidate +#ifdef CONFIG_X86_64 + && !(adev->flags & AMD_IS_APU) +#endif + ) amdgpu_ring_emit_hdp_invalidate(ring); r = amdgpu_fence_emit(ring, f); @@ -214,6 +222,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return r; } + if (ring->funcs->insert_end) + ring->funcs->insert_end(ring); + /* wrap the last IB with fence */ if (job && job->uf_addr) { amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index ba38ae6a1463..a3da1a122fc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -25,6 +25,48 @@ #define __AMDGPU_IH_H__ struct amdgpu_device; + /* + * vega10+ IH clients + */ +enum amdgpu_ih_clientid +{ + AMDGPU_IH_CLIENTID_IH = 0x00, + AMDGPU_IH_CLIENTID_ACP = 0x01, + AMDGPU_IH_CLIENTID_ATHUB = 0x02, + AMDGPU_IH_CLIENTID_BIF = 0x03, + AMDGPU_IH_CLIENTID_DCE = 0x04, + AMDGPU_IH_CLIENTID_ISP = 0x05, + AMDGPU_IH_CLIENTID_PCIE0 = 0x06, + AMDGPU_IH_CLIENTID_RLC = 0x07, + AMDGPU_IH_CLIENTID_SDMA0 = 0x08, + AMDGPU_IH_CLIENTID_SDMA1 = 0x09, + AMDGPU_IH_CLIENTID_SE0SH = 0x0a, + AMDGPU_IH_CLIENTID_SE1SH = 0x0b, + AMDGPU_IH_CLIENTID_SE2SH = 0x0c, + AMDGPU_IH_CLIENTID_SE3SH = 0x0d, + AMDGPU_IH_CLIENTID_SYSHUB = 0x0e, + AMDGPU_IH_CLIENTID_THM = 0x0f, + AMDGPU_IH_CLIENTID_UVD = 0x10, + AMDGPU_IH_CLIENTID_VCE0 = 0x11, + AMDGPU_IH_CLIENTID_VMC = 0x12, + AMDGPU_IH_CLIENTID_XDMA = 0x13, + AMDGPU_IH_CLIENTID_GRBM_CP = 0x14, + AMDGPU_IH_CLIENTID_ATS = 0x15, + AMDGPU_IH_CLIENTID_ROM_SMUIO = 0x16, + AMDGPU_IH_CLIENTID_DF = 0x17, + AMDGPU_IH_CLIENTID_VCE1 = 0x18, + AMDGPU_IH_CLIENTID_PWR = 0x19, + AMDGPU_IH_CLIENTID_UTCL2 = 0x1b, + AMDGPU_IH_CLIENTID_EA = 0x1c, + AMDGPU_IH_CLIENTID_UTCL2LOG = 0x1d, + AMDGPU_IH_CLIENTID_MP0 = 0x1e, + AMDGPU_IH_CLIENTID_MP1 = 0x1f, + + AMDGPU_IH_CLIENTID_MAX + +}; + +#define AMDGPU_IH_CLIENTID_LEGACY 0 /* * R6xx+ IH ring @@ -46,12 +88,19 @@ struct amdgpu_ih_ring { dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ }; +#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4 + struct amdgpu_iv_entry { + unsigned client_id; unsigned src_id; - unsigned src_data; unsigned ring_id; unsigned vm_id; + unsigned vm_id_src; + uint64_t timestamp; + unsigned timestamp_src; unsigned pas_id; + unsigned pasid_src; + unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW]; const uint32_t *iv_entry; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index e63ece049b05..13b487235a8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -33,6 +33,7 @@ #include "amdgpu_ih.h" #include "atom.h" #include "amdgpu_connectors.h" +#include "amdgpu_trace.h" #include <linux/pm_runtime.h> @@ -89,23 +90,28 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work) static void amdgpu_irq_disable_all(struct amdgpu_device *adev) { unsigned long irqflags; - unsigned i, j; + unsigned i, j, k; int r; spin_lock_irqsave(&adev->irq.lock, irqflags); - for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) { - struct amdgpu_irq_src *src = adev->irq.sources[i]; - - if (!src || !src->funcs->set || !src->num_types) + for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) { + if (!adev->irq.client[i].sources) continue; - for (j = 0; j < src->num_types; ++j) { - atomic_set(&src->enabled_types[j], 0); - r = src->funcs->set(adev, src, j, - AMDGPU_IRQ_STATE_DISABLE); - if (r) - DRM_ERROR("error disabling interrupt (%d)\n", - r); + for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { + struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; + + if (!src || !src->funcs->set || !src->num_types) + continue; + + for (k = 0; k < src->num_types; ++k) { + atomic_set(&src->enabled_types[k], 0); + r = src->funcs->set(adev, src, k, + AMDGPU_IRQ_STATE_DISABLE); + if (r) + DRM_ERROR("error disabling interrupt (%d)\n", + r); + } } } spin_unlock_irqrestore(&adev->irq.lock, irqflags); @@ -254,7 +260,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) */ void amdgpu_irq_fini(struct amdgpu_device *adev) { - unsigned i; + unsigned i, j; drm_vblank_cleanup(adev->ddev); if (adev->irq.installed) { @@ -266,19 +272,25 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) cancel_work_sync(&adev->reset_work); } - for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) { - struct amdgpu_irq_src *src = adev->irq.sources[i]; - - if (!src) + for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) { + if (!adev->irq.client[i].sources) continue; - kfree(src->enabled_types); - src->enabled_types = NULL; - if (src->data) { - kfree(src->data); - kfree(src); - adev->irq.sources[i] = NULL; + for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { + struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; + + if (!src) + continue; + + kfree(src->enabled_types); + src->enabled_types = NULL; + if (src->data) { + kfree(src->data); + kfree(src); + adev->irq.client[i].sources[j] = NULL; + } } + kfree(adev->irq.client[i].sources); } } @@ -290,18 +302,30 @@ void amdgpu_irq_fini(struct amdgpu_device *adev) * @source: irq source * */ -int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, +int amdgpu_irq_add_id(struct amdgpu_device *adev, + unsigned client_id, unsigned src_id, struct amdgpu_irq_src *source) { - if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) + if (client_id >= AMDGPU_IH_CLIENTID_MAX) return -EINVAL; - if (adev->irq.sources[src_id] != NULL) + if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) return -EINVAL; if (!source->funcs) return -EINVAL; + if (!adev->irq.client[client_id].sources) { + adev->irq.client[client_id].sources = kcalloc(AMDGPU_MAX_IRQ_SRC_ID, + sizeof(struct amdgpu_irq_src), + GFP_KERNEL); + if (!adev->irq.client[client_id].sources) + return -ENOMEM; + } + + if (adev->irq.client[client_id].sources[src_id] != NULL) + return -EINVAL; + if (source->num_types && !source->enabled_types) { atomic_t *types; @@ -313,8 +337,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, source->enabled_types = types; } - adev->irq.sources[src_id] = source; - + adev->irq.client[client_id].sources[src_id] = source; return 0; } @@ -329,10 +352,18 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, void amdgpu_irq_dispatch(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { + unsigned client_id = entry->client_id; unsigned src_id = entry->src_id; struct amdgpu_irq_src *src; int r; + trace_amdgpu_iv(entry); + + if (client_id >= AMDGPU_IH_CLIENTID_MAX) { + DRM_DEBUG("Invalid client_id in IV: %d\n", client_id); + return; + } + if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); return; @@ -341,7 +372,13 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, if (adev->irq.virq[src_id]) { generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); } else { - src = adev->irq.sources[src_id]; + if (!adev->irq.client[client_id].sources) { + DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", + client_id, src_id); + return; + } + + src = adev->irq.client[client_id].sources[src_id]; if (!src) { DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); return; @@ -385,13 +422,20 @@ int amdgpu_irq_update(struct amdgpu_device *adev, void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) { - int i, j; - for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; i++) { - struct amdgpu_irq_src *src = adev->irq.sources[i]; - if (!src) + int i, j, k; + + for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) { + if (!adev->irq.client[i].sources) continue; - for (j = 0; j < src->num_types; j++) - amdgpu_irq_update(adev, src, j); + + for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { + struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; + + if (!src) + continue; + for (k = 0; k < src->num_types; k++) + amdgpu_irq_update(adev, src, k); + } } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 1642f4108297..0610cc4a9788 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -28,6 +28,7 @@ #include "amdgpu_ih.h" #define AMDGPU_MAX_IRQ_SRC_ID 0x100 +#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 struct amdgpu_device; struct amdgpu_iv_entry; @@ -44,6 +45,10 @@ struct amdgpu_irq_src { void *data; }; +struct amdgpu_irq_client { + struct amdgpu_irq_src **sources; +}; + /* provided by interrupt generating IP blocks */ struct amdgpu_irq_src_funcs { int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, @@ -58,7 +63,7 @@ struct amdgpu_irq { bool installed; spinlock_t lock; /* interrupt sources */ - struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID]; + struct amdgpu_irq_client client[AMDGPU_IH_CLIENTID_MAX]; /* status, etc. */ bool msi_enabled; /* msi enabled */ @@ -80,7 +85,8 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg); int amdgpu_irq_init(struct amdgpu_device *adev); void amdgpu_irq_fini(struct amdgpu_device *adev); -int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, +int amdgpu_irq_add_id(struct amdgpu_device *adev, + unsigned client_id, unsigned src_id, struct amdgpu_irq_src *source); void amdgpu_irq_dispatch(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 61d94c745672..5ded370a4b35 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -208,6 +208,14 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; break; + case AMDGPU_INFO_FW_SOS: + fw_info->ver = adev->psp.sos_fw_version; + fw_info->feature = adev->psp.sos_feature_version; + break; + case AMDGPU_INFO_FW_ASD: + fw_info->ver = adev->psp.asd_fw_version; + fw_info->feature = adev->psp.asd_feature_version; + break; default: return -EINVAL; } @@ -240,6 +248,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file uint32_t ui32 = 0; uint64_t ui64 = 0; int i, found; + int ui32_size = sizeof(ui32); if (!info->return_size || !info->return_pointer) return -EINVAL; @@ -308,6 +317,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ib_size_alignment = 1; break; + case AMDGPU_HW_IP_UVD_ENC: + type = AMD_IP_BLOCK_TYPE_UVD; + for (i = 0; i < adev->uvd.num_enc_rings; i++) + ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 1; + break; default: return -EINVAL; } @@ -347,6 +363,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file case AMDGPU_HW_IP_VCE: type = AMD_IP_BLOCK_TYPE_VCE; break; + case AMDGPU_HW_IP_UVD_ENC: + type = AMD_IP_BLOCK_TYPE_UVD; + break; default: return -EINVAL; } @@ -527,6 +546,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.vram_type = adev->mc.vram_type; dev_info.vram_bit_width = adev->mc.vram_width; dev_info.vce_harvest_config = adev->vce.harvest_config; + dev_info.gc_double_offchip_lds_buf = + adev->gfx.config.double_offchip_lds_buf; + + if (amdgpu_ngg) { + dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr; + dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr; + dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr; + dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr; + } return copy_to_user(out, &dev_info, min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; @@ -596,6 +624,80 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file return -EINVAL; } } + case AMDGPU_INFO_SENSOR: { + struct pp_gpu_power query = {0}; + int query_size = sizeof(query); + + if (amdgpu_dpm == 0) + return -ENOENT; + + switch (info->sensor_info.type) { + case AMDGPU_INFO_SENSOR_GFX_SCLK: + /* get sclk in Mhz */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_GFX_SCLK, + (void *)&ui32, &ui32_size)) { + return -EINVAL; + } + ui32 /= 100; + break; + case AMDGPU_INFO_SENSOR_GFX_MCLK: + /* get mclk in Mhz */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_GFX_MCLK, + (void *)&ui32, &ui32_size)) { + return -EINVAL; + } + ui32 /= 100; + break; + case AMDGPU_INFO_SENSOR_GPU_TEMP: + /* get temperature in millidegrees C */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_GPU_TEMP, + (void *)&ui32, &ui32_size)) { + return -EINVAL; + } + break; + case AMDGPU_INFO_SENSOR_GPU_LOAD: + /* get GPU load */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_GPU_LOAD, + (void *)&ui32, &ui32_size)) { + return -EINVAL; + } + break; + case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: + /* get average GPU power */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_GPU_POWER, + (void *)&query, &query_size)) { + return -EINVAL; + } + ui32 = query.average_gpu_power >> 8; + break; + case AMDGPU_INFO_SENSOR_VDDNB: + /* get VDDNB in millivolts */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_VDDNB, + (void *)&ui32, &ui32_size)) { + return -EINVAL; + } + break; + case AMDGPU_INFO_SENSOR_VDDGFX: + /* get VDDGFX in millivolts */ + if (amdgpu_dpm_read_sensor(adev, + AMDGPU_PP_SENSOR_VDDGFX, + (void *)&ui32, &ui32_size)) { + return -EINVAL; + } + break; + default: + DRM_DEBUG_KMS("Invalid request %d\n", + info->sensor_info.type); + return -EINVAL; + } + return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; + } default: DRM_DEBUG_KMS("Invalid request %d\n", info->query); return -EINVAL; @@ -655,6 +757,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) goto out_suspend; } + fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); + if (!fpriv->prt_va) { + r = -ENOMEM; + amdgpu_vm_fini(adev, &fpriv->vm); + kfree(fpriv); + goto out_suspend; + } + if (amdgpu_sriov_vf(adev)) { r = amdgpu_map_static_csa(adev, &fpriv->vm); if (r) @@ -694,11 +804,15 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, if (!fpriv) return; + pm_runtime_get_sync(dev->dev); + amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); amdgpu_uvd_free_handles(adev, file_priv); amdgpu_vce_free_handles(adev, file_priv); + amdgpu_vm_bo_rmv(adev, fpriv->prt_va); + if (amdgpu_sriov_vf(adev)) { /* TODO: how to handle reserve failure */ BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false)); @@ -722,21 +836,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } -/** - * amdgpu_driver_preclose_kms - drm callback for pre close - * - * @dev: drm dev pointer - * @file_priv: drm file - * - * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx - * (all asics). - */ -void amdgpu_driver_preclose_kms(struct drm_device *dev, - struct drm_file *file_priv) -{ - pm_runtime_get_sync(dev->dev); -} - /* * VBlank related functions. */ @@ -989,6 +1088,23 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) fw_info.feature, fw_info.ver); } + /* PSP SOS */ + query_fw.fw_type = AMDGPU_INFO_FW_SOS; + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); + if (ret) + return ret; + seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", + fw_info.feature, fw_info.ver); + + + /* PSP ASD */ + query_fw.fw_type = AMDGPU_INFO_FW_ASD; + ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); + if (ret) + return ret; + seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", + fw_info.feature, fw_info.ver); + /* SMC */ query_fw.fw_type = AMDGPU_INFO_FW_SMC; ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index be80a4a68d7b..5aac350b007f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -395,32 +395,18 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, amdgpu_fill_placement_to_bo(bo, placement); /* Kernel allocation are uninterruptible */ - if (!resv) { - bool locked; - - reservation_object_init(&bo->tbo.ttm_resv); - locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock); - WARN_ON(!locked); - } - initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, - &bo->placement, page_align, !kernel, NULL, - acc_size, sg, resv ? resv : &bo->tbo.ttm_resv, - &amdgpu_ttm_bo_destroy); + r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, + &bo->placement, page_align, !kernel, NULL, + acc_size, sg, resv, &amdgpu_ttm_bo_destroy); amdgpu_cs_report_moved_bytes(adev, atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved); - if (unlikely(r != 0)) { - if (!resv) - ww_mutex_unlock(&bo->tbo.resv->lock); + if (unlikely(r != 0)) return r; - } - bo->tbo.priority = ilog2(bo->tbo.num_pages); if (kernel) - bo->tbo.priority *= 2; - bo->tbo.priority = min(bo->tbo.priority, (unsigned)(TTM_MAX_BO_PRIORITY - 1)); + bo->tbo.priority = 1; if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { @@ -436,7 +422,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, dma_fence_put(fence); } if (!resv) - ww_mutex_unlock(&bo->tbo.resv->lock); + amdgpu_bo_unreserve(bo); *bo_ptr = bo; trace_amdgpu_bo_create(bo); @@ -827,7 +813,10 @@ int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) { - if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + + if (adev->family <= AMDGPU_FAMILY_CZ && + AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) return -EINVAL; bo->tiling_flags = tiling_flags; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 346e80a7119b..990fde2cf4fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -43,16 +43,22 @@ static const struct cg_flag_name clocks[] = { {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, + {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, + {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, + {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, + {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, + {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, + {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, {0, NULL}, }; @@ -610,6 +616,174 @@ fail: return count; } +static ssize_t amdgpu_get_pp_power_profile(struct device *dev, + char *buf, struct amd_pp_profile *query) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + int ret = 0; + + if (adev->pp_enabled) + ret = amdgpu_dpm_get_power_profile_state( + adev, query); + else if (adev->pm.funcs->get_power_profile_state) + ret = adev->pm.funcs->get_power_profile_state( + adev, query); + + if (ret) + return ret; + + return snprintf(buf, PAGE_SIZE, + "%d %d %d %d %d\n", + query->min_sclk / 100, + query->min_mclk / 100, + query->activity_threshold, + query->up_hyst, + query->down_hyst); +} + +static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amd_pp_profile query = {0}; + + query.type = AMD_PP_GFX_PROFILE; + + return amdgpu_get_pp_power_profile(dev, buf, &query); +} + +static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amd_pp_profile query = {0}; + + query.type = AMD_PP_COMPUTE_PROFILE; + + return amdgpu_get_pp_power_profile(dev, buf, &query); +} + +static ssize_t amdgpu_set_pp_power_profile(struct device *dev, + const char *buf, + size_t count, + struct amd_pp_profile *request) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + uint32_t loop = 0; + char *sub_str, buf_cpy[128], *tmp_str; + const char delimiter[3] = {' ', '\n', '\0'}; + long int value; + int ret = 0; + + if (strncmp("reset", buf, strlen("reset")) == 0) { + if (adev->pp_enabled) + ret = amdgpu_dpm_reset_power_profile_state( + adev, request); + else if (adev->pm.funcs->reset_power_profile_state) + ret = adev->pm.funcs->reset_power_profile_state( + adev, request); + if (ret) { + count = -EINVAL; + goto fail; + } + return count; + } + + if (strncmp("set", buf, strlen("set")) == 0) { + if (adev->pp_enabled) + ret = amdgpu_dpm_set_power_profile_state( + adev, request); + else if (adev->pm.funcs->set_power_profile_state) + ret = adev->pm.funcs->set_power_profile_state( + adev, request); + if (ret) { + count = -EINVAL; + goto fail; + } + return count; + } + + if (count + 1 >= 128) { + count = -EINVAL; + goto fail; + } + + memcpy(buf_cpy, buf, count + 1); + tmp_str = buf_cpy; + + while (tmp_str[0]) { + sub_str = strsep(&tmp_str, delimiter); + ret = kstrtol(sub_str, 0, &value); + if (ret) { + count = -EINVAL; + goto fail; + } + + switch (loop) { + case 0: + /* input unit MHz convert to dpm table unit 10KHz*/ + request->min_sclk = (uint32_t)value * 100; + break; + case 1: + /* input unit MHz convert to dpm table unit 10KHz*/ + request->min_mclk = (uint32_t)value * 100; + break; + case 2: + request->activity_threshold = (uint16_t)value; + break; + case 3: + request->up_hyst = (uint8_t)value; + break; + case 4: + request->down_hyst = (uint8_t)value; + break; + default: + break; + } + + loop++; + } + + if (adev->pp_enabled) + ret = amdgpu_dpm_set_power_profile_state( + adev, request); + else if (adev->pm.funcs->set_power_profile_state) + ret = adev->pm.funcs->set_power_profile_state( + adev, request); + + if (ret) + count = -EINVAL; + +fail: + return count; +} + +static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct amd_pp_profile request = {0}; + + request.type = AMD_PP_GFX_PROFILE; + + return amdgpu_set_pp_power_profile(dev, buf, count, &request); +} + +static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct amd_pp_profile request = {0}; + + request.type = AMD_PP_COMPUTE_PROFILE; + + return amdgpu_set_pp_power_profile(dev, buf, count, &request); +} + static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state); static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, amdgpu_get_dpm_forced_performance_level, @@ -637,6 +811,12 @@ static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR, static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR, amdgpu_get_pp_mclk_od, amdgpu_set_pp_mclk_od); +static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR, + amdgpu_get_pp_gfx_power_profile, + amdgpu_set_pp_gfx_power_profile); +static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR, + amdgpu_get_pp_compute_power_profile, + amdgpu_set_pp_compute_power_profile); static ssize_t amdgpu_hwmon_show_temp(struct device *dev, struct device_attribute *attr, @@ -1142,11 +1322,11 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) /* XXX select vce level based on ring/task */ adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; mutex_unlock(&adev->pm.mutex); - amdgpu_pm_compute_clocks(adev); - amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, - AMD_PG_STATE_UNGATE); amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); + amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_UNGATE); + amdgpu_pm_compute_clocks(adev); } else { amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); @@ -1255,6 +1435,20 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) DRM_ERROR("failed to create device file pp_mclk_od\n"); return ret; } + ret = device_create_file(adev->dev, + &dev_attr_pp_gfx_power_profile); + if (ret) { + DRM_ERROR("failed to create device file " + "pp_gfx_power_profile\n"); + return ret; + } + ret = device_create_file(adev->dev, + &dev_attr_pp_compute_power_profile); + if (ret) { + DRM_ERROR("failed to create device file " + "pp_compute_power_profile\n"); + return ret; + } ret = amdgpu_debugfs_pm_init(adev); if (ret) { @@ -1284,6 +1478,10 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); device_remove_file(adev->dev, &dev_attr_pp_sclk_od); device_remove_file(adev->dev, &dev_attr_pp_mclk_od); + device_remove_file(adev->dev, + &dev_attr_pp_gfx_power_profile); + device_remove_file(adev->dev, + &dev_attr_pp_compute_power_profile); } void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) @@ -1340,7 +1538,9 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) { - int32_t value; + uint32_t value; + struct pp_gpu_power query = {0}; + int size; /* sanity check PP is enabled */ if (!(adev->powerplay.pp_funcs && @@ -1348,47 +1548,60 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a return -EINVAL; /* GPU Clocks */ + size = sizeof(value); seq_printf(m, "GFX Clocks and Power:\n"); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) seq_printf(m, "\t%u MHz (MCLK)\n", value/100); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) seq_printf(m, "\t%u MHz (SCLK)\n", value/100); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) seq_printf(m, "\t%u mV (VDDGFX)\n", value); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) seq_printf(m, "\t%u mV (VDDNB)\n", value); + size = sizeof(query); + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) { + seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8, + query.vddc_power & 0xff); + seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8, + query.vddci_power & 0xff); + seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8, + query.max_gpu_power & 0xff); + seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8, + query.average_gpu_power & 0xff); + } + size = sizeof(value); seq_printf(m, "\n"); /* GPU Temp */ - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) seq_printf(m, "GPU Temperature: %u C\n", value/1000); /* GPU Load */ - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) seq_printf(m, "GPU Load: %u %%\n", value); seq_printf(m, "\n"); /* UVD clocks */ - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, &value)) { + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { if (!value) { seq_printf(m, "UVD: Disabled\n"); } else { seq_printf(m, "UVD: Enabled\n"); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) seq_printf(m, "\t%u MHz (DCLK)\n", value/100); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) seq_printf(m, "\t%u MHz (VCLK)\n", value/100); } } seq_printf(m, "\n"); /* VCE clocks */ - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, &value)) { + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { if (!value) { seq_printf(m, "VCE: Disabled\n"); } else { seq_printf(m, "VCE: Enabled\n"); - if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, &value)) + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index 8856eccc37fa..f5ae871aa11c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -43,7 +43,7 @@ static int amdgpu_create_pp_handle(struct amdgpu_device *adev) amd_pp = &(adev->powerplay); pp_init.chip_family = adev->family; pp_init.chip_id = adev->asic_type; - pp_init.pm_en = amdgpu_dpm != 0 ? true : false; + pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false; pp_init.feature_mask = amdgpu_pp_feature_mask; pp_init.device = amdgpu_cgs_create_device(adev); ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle)); @@ -71,6 +71,7 @@ static int amdgpu_pp_early_init(void *handle) case CHIP_TOPAZ: case CHIP_CARRIZO: case CHIP_STONEY: + case CHIP_VEGA10: adev->pp_enabled = true; if (amdgpu_create_pp_handle(adev)) return -EINVAL; @@ -163,7 +164,7 @@ static int amdgpu_pp_hw_init(void *handle) int ret = 0; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->pp_enabled && adev->firmware.smu_load) + if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) amdgpu_ucode_init_bo(adev); if (adev->powerplay.ip_funcs->hw_init) @@ -190,7 +191,7 @@ static int amdgpu_pp_hw_fini(void *handle) ret = adev->powerplay.ip_funcs->hw_fini( adev->powerplay.pp_handle); - if (adev->pp_enabled && adev->firmware.smu_load) + if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) amdgpu_ucode_fini_bo(adev); return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c new file mode 100644 index 000000000000..4731015f6101 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -0,0 +1,481 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ + +#include <linux/firmware.h> +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_psp.h" +#include "amdgpu_ucode.h" +#include "soc15_common.h" +#include "psp_v3_1.h" + +static void psp_set_funcs(struct amdgpu_device *adev); + +static int psp_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + psp_set_funcs(adev); + + return 0; +} + +static int psp_sw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct psp_context *psp = &adev->psp; + int ret; + + switch (adev->asic_type) { + case CHIP_VEGA10: + psp->init_microcode = psp_v3_1_init_microcode; + psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv; + psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos; + psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf; + psp->ring_init = psp_v3_1_ring_init; + psp->cmd_submit = psp_v3_1_cmd_submit; + psp->compare_sram_data = psp_v3_1_compare_sram_data; + psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk; + break; + default: + return -EINVAL; + } + + psp->adev = adev; + + ret = psp_init_microcode(psp); + if (ret) { + DRM_ERROR("Failed to load psp firmware!\n"); + return ret; + } + + return 0; +} + +static int psp_sw_fini(void *handle) +{ + return 0; +} + +int psp_wait_for(struct psp_context *psp, uint32_t reg_index, + uint32_t reg_val, uint32_t mask, bool check_changed) +{ + uint32_t val; + int i; + struct amdgpu_device *adev = psp->adev; + + val = RREG32(reg_index); + + for (i = 0; i < adev->usec_timeout; i++) { + if (check_changed) { + if (val != reg_val) + return 0; + } else { + if ((val & mask) == reg_val) + return 0; + } + udelay(1); + } + + return -ETIME; +} + +static int +psp_cmd_submit_buf(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr, + int index) +{ + int ret; + struct amdgpu_bo *cmd_buf_bo; + uint64_t cmd_buf_mc_addr; + struct psp_gfx_cmd_resp *cmd_buf_mem; + struct amdgpu_device *adev = psp->adev; + + ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &cmd_buf_bo, &cmd_buf_mc_addr, + (void **)&cmd_buf_mem); + if (ret) + return ret; + + memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); + + memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); + + ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr, + fence_mc_addr, index); + + while (*((unsigned int *)psp->fence_buf) != index) { + msleep(1); + }; + + amdgpu_bo_free_kernel(&cmd_buf_bo, + &cmd_buf_mc_addr, + (void **)&cmd_buf_mem); + + return ret; +} + +static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd, + uint64_t tmr_mc, uint32_t size) +{ + cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; + cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc; + cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32); + cmd->cmd.cmd_setup_tmr.buf_size = size; +} + +/* Set up Trusted Memory Region */ +static int psp_tmr_init(struct psp_context *psp) +{ + int ret; + struct psp_gfx_cmd_resp *cmd; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + /* + * Allocate 3M memory aligned to 1M from Frame Buffer (local + * physical). + * + * Note: this memory need be reserved till the driver + * uninitializes. + */ + ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000, + AMDGPU_GEM_DOMAIN_VRAM, + &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); + if (ret) + goto failed; + + psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000); + + ret = psp_cmd_submit_buf(psp, NULL, cmd, + psp->fence_buf_mc_addr, 1); + if (ret) + goto failed_mem; + + kfree(cmd); + + return 0; + +failed_mem: + amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); +failed: + kfree(cmd); + return ret; +} + +static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd, + uint64_t asd_mc, uint64_t asd_mc_shared, + uint32_t size, uint32_t shared_size) +{ + cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; + cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); + cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); + cmd->cmd.cmd_load_ta.app_len = size; + + cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); + cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared); + cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size; +} + +static int psp_asd_load(struct psp_context *psp) +{ + int ret; + struct amdgpu_bo *asd_bo, *asd_shared_bo; + uint64_t asd_mc_addr, asd_shared_mc_addr; + void *asd_buf, *asd_shared_buf; + struct psp_gfx_cmd_resp *cmd; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + /* + * Allocate 16k memory aligned to 4k from Frame Buffer (local + * physical) for shared ASD <-> Driver + */ + ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &asd_shared_bo, &asd_shared_mc_addr, &asd_buf); + if (ret) + goto failed; + + /* + * Allocate 256k memory aligned to 4k from Frame Buffer (local + * physical) for ASD firmware + */ + ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_BIN_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &asd_bo, &asd_mc_addr, &asd_buf); + if (ret) + goto failed_mem; + + memcpy(asd_buf, psp->asd_start_addr, psp->asd_ucode_size); + + psp_prep_asd_cmd_buf(cmd, asd_mc_addr, asd_shared_mc_addr, + psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); + + ret = psp_cmd_submit_buf(psp, NULL, cmd, + psp->fence_buf_mc_addr, 2); + if (ret) + goto failed_mem1; + + amdgpu_bo_free_kernel(&asd_bo, &asd_mc_addr, &asd_buf); + amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf); + kfree(cmd); + + return 0; + +failed_mem1: + amdgpu_bo_free_kernel(&asd_bo, &asd_mc_addr, &asd_buf); +failed_mem: + amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf); +failed: + kfree(cmd); + return ret; +} + +static int psp_load_fw(struct amdgpu_device *adev) +{ + int ret; + struct psp_gfx_cmd_resp *cmd; + int i; + struct amdgpu_firmware_info *ucode; + struct psp_context *psp = &adev->psp; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + ret = psp_bootloader_load_sysdrv(psp); + if (ret) + goto failed; + + ret = psp_bootloader_load_sos(psp); + if (ret) + goto failed; + + ret = psp_ring_init(psp, PSP_RING_TYPE__KM); + if (ret) + goto failed; + + ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &psp->fence_buf_bo, + &psp->fence_buf_mc_addr, + &psp->fence_buf); + if (ret) + goto failed; + + memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); + + ret = psp_tmr_init(psp); + if (ret) + goto failed_mem; + + ret = psp_asd_load(psp); + if (ret) + goto failed_mem; + + for (i = 0; i < adev->firmware.max_ucodes; i++) { + ucode = &adev->firmware.ucode[i]; + if (!ucode->fw) + continue; + + if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && + psp_smu_reload_quirk(psp)) + continue; + + ret = psp_prep_cmd_buf(ucode, cmd); + if (ret) + goto failed_mem; + + ret = psp_cmd_submit_buf(psp, ucode, cmd, + psp->fence_buf_mc_addr, i + 3); + if (ret) + goto failed_mem; + +#if 0 + /* check if firmware loaded sucessfully */ + if (!amdgpu_psp_check_fw_loading_status(adev, i)) + return -EINVAL; +#endif + } + + amdgpu_bo_free_kernel(&psp->fence_buf_bo, + &psp->fence_buf_mc_addr, &psp->fence_buf); + kfree(cmd); + + return 0; + +failed_mem: + amdgpu_bo_free_kernel(&psp->fence_buf_bo, + &psp->fence_buf_mc_addr, &psp->fence_buf); +failed: + kfree(cmd); + return ret; +} + +static int psp_hw_init(void *handle) +{ + int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) + return 0; + + mutex_lock(&adev->firmware.mutex); + /* + * This sequence is just used on hw_init only once, no need on + * resume. + */ + ret = amdgpu_ucode_init_bo(adev); + if (ret) + goto failed; + + ret = psp_load_fw(adev); + if (ret) { + DRM_ERROR("PSP firmware loading failed\n"); + goto failed; + } + + mutex_unlock(&adev->firmware.mutex); + return 0; + +failed: + adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; + mutex_unlock(&adev->firmware.mutex); + return -EINVAL; +} + +static int psp_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct psp_context *psp = &adev->psp; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) + amdgpu_ucode_fini_bo(adev); + + if (psp->tmr_buf) + amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); + + return 0; +} + +static int psp_suspend(void *handle) +{ + return 0; +} + +static int psp_resume(void *handle) +{ + int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) + return 0; + + mutex_lock(&adev->firmware.mutex); + + ret = psp_load_fw(adev); + if (ret) + DRM_ERROR("PSP resume failed\n"); + + mutex_unlock(&adev->firmware.mutex); + + return ret; +} + +static bool psp_check_fw_loading_status(struct amdgpu_device *adev, + enum AMDGPU_UCODE_ID ucode_type) +{ + struct amdgpu_firmware_info *ucode = NULL; + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + DRM_INFO("firmware is not loaded by PSP\n"); + return true; + } + + if (!adev->firmware.fw_size) + return false; + + ucode = &adev->firmware.ucode[ucode_type]; + if (!ucode->fw || !ucode->ucode_size) + return false; + + return psp_compare_sram_data(&adev->psp, ucode, ucode_type); +} + +static int psp_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + return 0; +} + +static int psp_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +const struct amd_ip_funcs psp_ip_funcs = { + .name = "psp", + .early_init = psp_early_init, + .late_init = NULL, + .sw_init = psp_sw_init, + .sw_fini = psp_sw_fini, + .hw_init = psp_hw_init, + .hw_fini = psp_hw_fini, + .suspend = psp_suspend, + .resume = psp_resume, + .is_idle = NULL, + .wait_for_idle = NULL, + .soft_reset = NULL, + .set_clockgating_state = psp_set_clockgating_state, + .set_powergating_state = psp_set_powergating_state, +}; + +static const struct amdgpu_psp_funcs psp_funcs = { + .check_fw_loading_status = psp_check_fw_loading_status, +}; + +static void psp_set_funcs(struct amdgpu_device *adev) +{ + if (NULL == adev->firmware.funcs) + adev->firmware.funcs = &psp_funcs; +} + +const struct amdgpu_ip_block_version psp_v3_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_PSP, + .major = 3, + .minor = 1, + .rev = 0, + .funcs = &psp_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h new file mode 100644 index 000000000000..e9f35e025b59 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -0,0 +1,127 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ +#ifndef __AMDGPU_PSP_H__ +#define __AMDGPU_PSP_H__ + +#include "amdgpu.h" +#include "psp_gfx_if.h" + +#define PSP_FENCE_BUFFER_SIZE 0x1000 +#define PSP_CMD_BUFFER_SIZE 0x1000 +#define PSP_ASD_BIN_SIZE 0x40000 +#define PSP_ASD_SHARED_MEM_SIZE 0x4000 + +enum psp_ring_type +{ + PSP_RING_TYPE__INVALID = 0, + /* + * These values map to the way the PSP kernel identifies the + * rings. + */ + PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ + PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ +}; + +struct psp_ring +{ + enum psp_ring_type ring_type; + struct psp_gfx_rb_frame *ring_mem; + uint64_t ring_mem_mc_addr; + void *ring_mem_handle; + uint32_t ring_size; +}; + +struct psp_context +{ + struct amdgpu_device *adev; + struct psp_ring km_ring; + + int (*init_microcode)(struct psp_context *psp); + int (*bootloader_load_sysdrv)(struct psp_context *psp); + int (*bootloader_load_sos)(struct psp_context *psp); + int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, + struct psp_gfx_cmd_resp *cmd); + int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); + int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode, + uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index); + bool (*compare_sram_data)(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + enum AMDGPU_UCODE_ID ucode_type); + bool (*smu_reload_quirk)(struct psp_context *psp); + + /* sos firmware */ + const struct firmware *sos_fw; + uint32_t sos_fw_version; + uint32_t sos_feature_version; + uint32_t sys_bin_size; + uint32_t sos_bin_size; + uint8_t *sys_start_addr; + uint8_t *sos_start_addr; + + /* tmr buffer */ + struct amdgpu_bo *tmr_bo; + uint64_t tmr_mc_addr; + void *tmr_buf; + + /* asd firmware */ + const struct firmware *asd_fw; + uint32_t asd_fw_version; + uint32_t asd_feature_version; + uint32_t asd_ucode_size; + uint8_t *asd_start_addr; + + /* fence buffer */ + struct amdgpu_bo *fence_buf_bo; + uint64_t fence_buf_mc_addr; + void *fence_buf; +}; + +struct amdgpu_psp_funcs { + bool (*check_fw_loading_status)(struct amdgpu_device *adev, + enum AMDGPU_UCODE_ID); +}; + +#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type)) +#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type)) +#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ + (psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) +#define psp_compare_sram_data(psp, ucode, type) \ + (psp)->compare_sram_data((psp), (ucode), (type)) +#define psp_init_microcode(psp) \ + ((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0) +#define psp_bootloader_load_sysdrv(psp) \ + ((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0) +#define psp_bootloader_load_sos(psp) \ + ((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0) +#define psp_smu_reload_quirk(psp) \ + ((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false) + +extern const struct amd_ip_funcs psp_ip_funcs; + +extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; +extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, + uint32_t field_val, uint32_t mask, bool check_changed); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 7c842b7f1004..6a85db0c0bc3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -182,16 +182,32 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, return r; } - r = amdgpu_wb_get(adev, &ring->rptr_offs); - if (r) { - dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); - return r; - } + if (ring->funcs->support_64bit_ptrs) { + r = amdgpu_wb_get_64bit(adev, &ring->rptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); + return r; + } + + r = amdgpu_wb_get_64bit(adev, &ring->wptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); + return r; + } + + } else { + r = amdgpu_wb_get(adev, &ring->rptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); + return r; + } + + r = amdgpu_wb_get(adev, &ring->wptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); + return r; + } - r = amdgpu_wb_get(adev, &ring->wptr_offs); - if (r) { - dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); - return r; } r = amdgpu_wb_get(adev, &ring->fence_offs); @@ -219,6 +235,9 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, ring->ring_size = roundup_pow_of_two(max_dw * 4 * amdgpu_sched_hw_submission); + ring->buf_mask = (ring->ring_size / 4) - 1; + ring->ptr_mask = ring->funcs->support_64bit_ptrs ? + 0xffffffffffffffff : ring->buf_mask; /* Allocate ring buffer */ if (ring->ring_obj == NULL) { r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, @@ -230,9 +249,9 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, dev_err(adev->dev, "(%d) ring create failed\n", r); return r; } - memset((void *)ring->ring, 0, ring->ring_size); + amdgpu_ring_clear_ring(ring); } - ring->ptr_mask = (ring->ring_size / 4) - 1; + ring->max_dw = max_dw; if (amdgpu_debugfs_ring_init(adev, ring)) { @@ -253,10 +272,18 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) { ring->ready = false; - amdgpu_wb_free(ring->adev, ring->cond_exe_offs); - amdgpu_wb_free(ring->adev, ring->fence_offs); - amdgpu_wb_free(ring->adev, ring->rptr_offs); - amdgpu_wb_free(ring->adev, ring->wptr_offs); + if (ring->funcs->support_64bit_ptrs) { + amdgpu_wb_free_64bit(ring->adev, ring->cond_exe_offs); + amdgpu_wb_free_64bit(ring->adev, ring->fence_offs); + amdgpu_wb_free_64bit(ring->adev, ring->rptr_offs); + amdgpu_wb_free_64bit(ring->adev, ring->wptr_offs); + } else { + amdgpu_wb_free(ring->adev, ring->cond_exe_offs); + amdgpu_wb_free(ring->adev, ring->fence_offs); + amdgpu_wb_free(ring->adev, ring->rptr_offs); + amdgpu_wb_free(ring->adev, ring->wptr_offs); + } + amdgpu_bo_free_kernel(&ring->ring_obj, &ring->gpu_addr, @@ -293,8 +320,8 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, if (*pos < 12) { early[0] = amdgpu_ring_get_rptr(ring); - early[1] = amdgpu_ring_get_wptr(ring); - early[2] = ring->wptr; + early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; + early[2] = ring->wptr & ring->buf_mask; for (i = *pos / 4; i < 3 && size; i++) { r = put_user(early[i], (uint32_t *)buf); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 2345b39878c6..63e56398ca9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -27,10 +27,11 @@ #include "gpu_scheduler.h" /* max number of rings */ -#define AMDGPU_MAX_RINGS 16 +#define AMDGPU_MAX_RINGS 18 #define AMDGPU_MAX_GFX_RINGS 1 #define AMDGPU_MAX_COMPUTE_RINGS 8 #define AMDGPU_MAX_VCE_RINGS 3 +#define AMDGPU_MAX_UVD_ENC_RINGS 2 /* some special values for the owner field */ #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) @@ -45,7 +46,8 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_SDMA, AMDGPU_RING_TYPE_UVD, AMDGPU_RING_TYPE_VCE, - AMDGPU_RING_TYPE_KIQ + AMDGPU_RING_TYPE_KIQ, + AMDGPU_RING_TYPE_UVD_ENC }; struct amdgpu_device; @@ -96,10 +98,11 @@ struct amdgpu_ring_funcs { enum amdgpu_ring_type type; uint32_t align_mask; u32 nop; + bool support_64bit_ptrs; /* ring read/write ptr handling */ - u32 (*get_rptr)(struct amdgpu_ring *ring); - u32 (*get_wptr)(struct amdgpu_ring *ring); + u64 (*get_rptr)(struct amdgpu_ring *ring); + u64 (*get_wptr)(struct amdgpu_ring *ring); void (*set_wptr)(struct amdgpu_ring *ring); /* validating and patching of IBs */ int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); @@ -126,6 +129,7 @@ struct amdgpu_ring_funcs { int (*test_ib)(struct amdgpu_ring *ring, long timeout); /* insert NOP packets */ void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); + void (*insert_end)(struct amdgpu_ring *ring); /* pad the indirect buffer to the necessary number of dw */ void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); unsigned (*init_cond_exec)(struct amdgpu_ring *ring); @@ -148,19 +152,23 @@ struct amdgpu_ring { struct amdgpu_bo *ring_obj; volatile uint32_t *ring; unsigned rptr_offs; - unsigned wptr; - unsigned wptr_old; + u64 wptr; + u64 wptr_old; unsigned ring_size; unsigned max_dw; int count_dw; uint64_t gpu_addr; - uint32_t ptr_mask; + uint64_t ptr_mask; + uint32_t buf_mask; bool ready; u32 idx; u32 me; u32 pipe; u32 queue; struct amdgpu_bo *mqd_obj; + uint64_t mqd_gpu_addr; + void *mqd_ptr; + uint64_t eop_gpu_addr; u32 doorbell_index; bool use_doorbell; unsigned wptr_offs; @@ -184,5 +192,12 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned ring_size, struct amdgpu_irq_src *irq_src, unsigned irq_type); void amdgpu_ring_fini(struct amdgpu_ring *ring); +static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) +{ + int i = 0; + while (i <= ring->buf_mask) + ring->ring[i++] = ring->funcs->nop; + +} #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index e05a24325eeb..15510dadde01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -228,7 +228,7 @@ out_unref: out_cleanup: kfree(gtt_obj); if (r) { - printk(KERN_WARNING "Error while testing BO move.\n"); + pr_warn("Error while testing BO move\n"); } } @@ -237,82 +237,3 @@ void amdgpu_test_moves(struct amdgpu_device *adev) if (adev->mman.buffer_funcs) amdgpu_do_test_moves(adev); } - -void amdgpu_test_ring_sync(struct amdgpu_device *adev, - struct amdgpu_ring *ringA, - struct amdgpu_ring *ringB) -{ -} - -static void amdgpu_test_ring_sync2(struct amdgpu_device *adev, - struct amdgpu_ring *ringA, - struct amdgpu_ring *ringB, - struct amdgpu_ring *ringC) -{ -} - -static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA, - struct amdgpu_ring *ringB) -{ - if (ringA == &ringA->adev->vce.ring[0] && - ringB == &ringB->adev->vce.ring[1]) - return false; - - return true; -} - -void amdgpu_test_syncing(struct amdgpu_device *adev) -{ - int i, j, k; - - for (i = 1; i < AMDGPU_MAX_RINGS; ++i) { - struct amdgpu_ring *ringA = adev->rings[i]; - if (!ringA || !ringA->ready) - continue; - - for (j = 0; j < i; ++j) { - struct amdgpu_ring *ringB = adev->rings[j]; - if (!ringB || !ringB->ready) - continue; - - if (!amdgpu_test_sync_possible(ringA, ringB)) - continue; - - DRM_INFO("Testing syncing between rings %d and %d...\n", i, j); - amdgpu_test_ring_sync(adev, ringA, ringB); - - DRM_INFO("Testing syncing between rings %d and %d...\n", j, i); - amdgpu_test_ring_sync(adev, ringB, ringA); - - for (k = 0; k < j; ++k) { - struct amdgpu_ring *ringC = adev->rings[k]; - if (!ringC || !ringC->ready) - continue; - - if (!amdgpu_test_sync_possible(ringA, ringC)) - continue; - - if (!amdgpu_test_sync_possible(ringB, ringC)) - continue; - - DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k); - amdgpu_test_ring_sync2(adev, ringA, ringB, ringC); - - DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j); - amdgpu_test_ring_sync2(adev, ringA, ringC, ringB); - - DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k); - amdgpu_test_ring_sync2(adev, ringB, ringA, ringC); - - DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i); - amdgpu_test_ring_sync2(adev, ringB, ringC, ringA); - - DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j); - amdgpu_test_ring_sync2(adev, ringC, ringA, ringB); - - DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i); - amdgpu_test_ring_sync2(adev, ringC, ringB, ringA); - } - } - } -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index a18ae1e97860..a87de18160a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -11,6 +11,9 @@ #define TRACE_SYSTEM amdgpu #define TRACE_INCLUDE_FILE amdgpu_trace +#define AMDGPU_JOB_GET_TIMELINE_NAME(job) \ + job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished) + TRACE_EVENT(amdgpu_mm_rreg, TP_PROTO(unsigned did, uint32_t reg, uint32_t value), TP_ARGS(did, reg, value), @@ -49,6 +52,43 @@ TRACE_EVENT(amdgpu_mm_wreg, (unsigned long)__entry->value) ); +TRACE_EVENT(amdgpu_iv, + TP_PROTO(struct amdgpu_iv_entry *iv), + TP_ARGS(iv), + TP_STRUCT__entry( + __field(unsigned, client_id) + __field(unsigned, src_id) + __field(unsigned, ring_id) + __field(unsigned, vm_id) + __field(unsigned, vm_id_src) + __field(uint64_t, timestamp) + __field(unsigned, timestamp_src) + __field(unsigned, pas_id) + __array(unsigned, src_data, 4) + ), + TP_fast_assign( + __entry->client_id = iv->client_id; + __entry->src_id = iv->src_id; + __entry->ring_id = iv->ring_id; + __entry->vm_id = iv->vm_id; + __entry->vm_id_src = iv->vm_id_src; + __entry->timestamp = iv->timestamp; + __entry->timestamp_src = iv->timestamp_src; + __entry->pas_id = iv->pas_id; + __entry->src_data[0] = iv->src_data[0]; + __entry->src_data[1] = iv->src_data[1]; + __entry->src_data[2] = iv->src_data[2]; + __entry->src_data[3] = iv->src_data[3]; + ), + TP_printk("client_id:%u src_id:%u ring:%u vm_id:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n", + __entry->client_id, __entry->src_id, + __entry->ring_id, __entry->vm_id, + __entry->timestamp, __entry->pas_id, + __entry->src_data[0], __entry->src_data[1], + __entry->src_data[2], __entry->src_data[3]) +); + + TRACE_EVENT(amdgpu_bo_create, TP_PROTO(struct amdgpu_bo *bo), TP_ARGS(bo), @@ -70,7 +110,7 @@ TRACE_EVENT(amdgpu_bo_create, __entry->visible = bo->flags; ), - TP_printk("bo=%p,pages=%u,type=%d,prefered=%d,allowed=%d,visible=%d", + TP_printk("bo=%p, pages=%u, type=%d, prefered=%d, allowed=%d, visible=%d", __entry->bo, __entry->pages, __entry->type, __entry->prefer, __entry->allow, __entry->visible) ); @@ -101,50 +141,51 @@ TRACE_EVENT(amdgpu_cs_ioctl, TP_PROTO(struct amdgpu_job *job), TP_ARGS(job), TP_STRUCT__entry( - __field(struct amdgpu_device *, adev) - __field(struct amd_sched_job *, sched_job) - __field(struct amdgpu_ib *, ib) + __field(uint64_t, sched_job_id) + __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)) + __field(unsigned int, context) + __field(unsigned int, seqno) __field(struct dma_fence *, fence) __field(char *, ring_name) __field(u32, num_ibs) ), TP_fast_assign( - __entry->adev = job->adev; - __entry->sched_job = &job->base; - __entry->ib = job->ibs; - __entry->fence = &job->base.s_fence->finished; + __entry->sched_job_id = job->base.id; + __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)) + __entry->context = job->base.s_fence->finished.context; + __entry->seqno = job->base.s_fence->finished.seqno; __entry->ring_name = job->ring->name; __entry->num_ibs = job->num_ibs; ), - TP_printk("adev=%p, sched_job=%p, first ib=%p, sched fence=%p, ring name:%s, num_ibs:%u", - __entry->adev, __entry->sched_job, __entry->ib, - __entry->fence, __entry->ring_name, __entry->num_ibs) + TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", + __entry->sched_job_id, __get_str(timeline), __entry->context, + __entry->seqno, __entry->ring_name, __entry->num_ibs) ); TRACE_EVENT(amdgpu_sched_run_job, TP_PROTO(struct amdgpu_job *job), TP_ARGS(job), TP_STRUCT__entry( - __field(struct amdgpu_device *, adev) - __field(struct amd_sched_job *, sched_job) - __field(struct amdgpu_ib *, ib) - __field(struct dma_fence *, fence) + __field(uint64_t, sched_job_id) + __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)) + __field(unsigned int, context) + __field(unsigned int, seqno) __field(char *, ring_name) __field(u32, num_ibs) ), TP_fast_assign( - __entry->adev = job->adev; - __entry->sched_job = &job->base; - __entry->ib = job->ibs; - __entry->fence = &job->base.s_fence->finished; + __entry->sched_job_id = job->base.id; + __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)) + __entry->context = job->base.s_fence->finished.context; + __entry->seqno = job->base.s_fence->finished.seqno; __entry->ring_name = job->ring->name; __entry->num_ibs = job->num_ibs; ), - TP_printk("adev=%p, sched_job=%p, first ib=%p, sched fence=%p, ring name:%s, num_ibs:%u", - __entry->adev, __entry->sched_job, __entry->ib, - __entry->fence, __entry->ring_name, __entry->num_ibs) + TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", + __entry->sched_job_id, __get_str(timeline), __entry->context, + __entry->seqno, __entry->ring_name, __entry->num_ibs) ); @@ -184,7 +225,7 @@ TRACE_EVENT(amdgpu_vm_bo_map, ), TP_fast_assign( - __entry->bo = bo_va->bo; + __entry->bo = bo_va ? bo_va->bo : NULL; __entry->start = mapping->it.start; __entry->last = mapping->it.last; __entry->offset = mapping->offset; @@ -321,7 +362,7 @@ TRACE_EVENT(amdgpu_bo_list_set, __entry->bo = bo; __entry->bo_size = amdgpu_bo_size(bo); ), - TP_printk("list=%p, bo=%p, bo_size = %Ld", + TP_printk("list=%p, bo=%p, bo_size=%Ld", __entry->list, __entry->bo, __entry->bo_size) @@ -339,7 +380,7 @@ TRACE_EVENT(amdgpu_cs_bo_status, __entry->total_bo = total_bo; __entry->total_size = total_size; ), - TP_printk("total bo size = %Ld, total bo count = %Ld", + TP_printk("total_bo_size=%Ld, total_bo_count=%Ld", __entry->total_bo, __entry->total_size) ); @@ -359,11 +400,12 @@ TRACE_EVENT(amdgpu_ttm_bo_move, __entry->new_placement = new_placement; __entry->old_placement = old_placement; ), - TP_printk("bo=%p from:%d to %d with size = %Ld", + TP_printk("bo=%p, from=%d, to=%d, size=%Ld", __entry->bo, __entry->old_placement, __entry->new_placement, __entry->bo_size) ); +#undef AMDGPU_JOB_GET_TIMELINE_NAME #endif /* This part must be outside protection */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 4c6094eefc51..244bb9aacf86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -746,7 +746,7 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) { struct ttm_tt *ttm = bo->ttm; struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; - uint32_t flags; + uint64_t flags; int r; if (!ttm || amdgpu_ttm_is_bound(ttm)) @@ -1027,10 +1027,10 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); } -uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, +uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, struct ttm_mem_reg *mem) { - uint32_t flags = 0; + uint64_t flags = 0; if (mem && mem->mem_type != TTM_PL_SYSTEM) flags |= AMDGPU_PTE_VALID; @@ -1042,9 +1042,7 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, flags |= AMDGPU_PTE_SNOOPED; } - if (adev->asic_type >= CHIP_TONGA) - flags |= AMDGPU_PTE_EXECUTABLE; - + flags |= adev->gart.gart_pte_flags; flags |= AMDGPU_PTE_READABLE; if (!amdgpu_ttm_tt_is_readonly(ttm)) @@ -1160,27 +1158,33 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; /* GDS Memory */ - r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, - adev->gds.mem.total_size >> PAGE_SHIFT); - if (r) { - DRM_ERROR("Failed initializing GDS heap.\n"); - return r; + if (adev->gds.mem.total_size) { + r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, + adev->gds.mem.total_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing GDS heap.\n"); + return r; + } } /* GWS */ - r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, - adev->gds.gws.total_size >> PAGE_SHIFT); - if (r) { - DRM_ERROR("Failed initializing gws heap.\n"); - return r; + if (adev->gds.gws.total_size) { + r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, + adev->gds.gws.total_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing gws heap.\n"); + return r; + } } /* OA */ - r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, - adev->gds.oa.total_size >> PAGE_SHIFT); - if (r) { - DRM_ERROR("Failed initializing oa heap.\n"); - return r; + if (adev->gds.oa.total_size) { + r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, + adev->gds.oa.total_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing oa heap.\n"); + return r; + } } r = amdgpu_ttm_debugfs_init(adev); @@ -1208,9 +1212,12 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) } ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); - ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); - ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); - ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); + if (adev->gds.mem.total_size) + ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); + if (adev->gds.gws.total_size) + ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); + if (adev->gds.oa.total_size) + ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); ttm_bo_device_release(&adev->mman.bdev); amdgpu_gart_fini(adev); amdgpu_ttm_global_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 0f0b38191fac..a1891c93cdbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -217,10 +217,55 @@ bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, return true; } -static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, - uint64_t mc_addr, void *kptr) +enum amdgpu_firmware_load_type +amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) +{ + switch (adev->asic_type) { +#ifdef CONFIG_DRM_AMDGPU_SI + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_OLAND: + return AMDGPU_FW_LOAD_DIRECT; +#endif +#ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_HAWAII: + case CHIP_MULLINS: + return AMDGPU_FW_LOAD_DIRECT; +#endif + case CHIP_TOPAZ: + case CHIP_TONGA: + case CHIP_FIJI: + case CHIP_CARRIZO: + case CHIP_STONEY: + case CHIP_POLARIS10: + case CHIP_POLARIS11: + case CHIP_POLARIS12: + if (!load_type) + return AMDGPU_FW_LOAD_DIRECT; + else + return AMDGPU_FW_LOAD_SMU; + case CHIP_VEGA10: + if (!load_type) + return AMDGPU_FW_LOAD_DIRECT; + else + return AMDGPU_FW_LOAD_PSP; + default: + DRM_ERROR("Unknow firmware load type\n"); + } + + return AMDGPU_FW_LOAD_DIRECT; +} + +static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, + struct amdgpu_firmware_info *ucode, + uint64_t mc_addr, void *kptr) { const struct common_firmware_header *header = NULL; + const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; if (NULL == ucode->fw) return 0; @@ -232,9 +277,36 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, return 0; header = (const struct common_firmware_header *)ucode->fw->data; - memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + - le32_to_cpu(header->ucode_array_offset_bytes)), - le32_to_cpu(header->ucode_size_bytes)); + + cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || + (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && + ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && + ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && + ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) { + ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); + + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes)), + ucode->ucode_size); + } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || + ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { + ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - + le32_to_cpu(cp_hdr->jt_size) * 4; + + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes)), + ucode->ucode_size); + } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || + ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { + ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; + + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes) + + le32_to_cpu(cp_hdr->jt_offset) * 4), + ucode->ucode_size); + } return 0; } @@ -260,10 +332,11 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, (le32_to_cpu(header->jt_offset) * 4); memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); + ucode->ucode_size += le32_to_cpu(header->jt_size) * 4; + return 0; } - int amdgpu_ucode_init_bo(struct amdgpu_device *adev) { struct amdgpu_bo **bo = &adev->firmware.fw_buf; @@ -303,20 +376,32 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) amdgpu_bo_unreserve(*bo); - for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { + memset(fw_buf_ptr, 0, adev->firmware.fw_size); + + /* + * if SMU loaded firmware, it needn't add SMC, UVD, and VCE + * ucode info here + */ + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) + adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; + else + adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; + + for (i = 0; i < adev->firmware.max_ucodes; i++) { ucode = &adev->firmware.ucode[i]; if (ucode->fw) { header = (const struct common_firmware_header *)ucode->fw->data; - amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset, - fw_buf_ptr + fw_offset); - if (i == AMDGPU_UCODE_ID_CP_MEC1) { + amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset, + (void *)((uint8_t *)fw_buf_ptr + fw_offset)); + if (i == AMDGPU_UCODE_ID_CP_MEC1 && + adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { const struct gfx_firmware_header_v1_0 *cp_hdr; cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset, fw_buf_ptr + fw_offset); fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); } - fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); } } return 0; @@ -328,7 +413,8 @@ failed_pin: failed_reserve: amdgpu_bo_unref(bo); failed: - adev->firmware.smu_load = false; + if (err) + adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; return err; } @@ -338,7 +424,7 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev) int i; struct amdgpu_firmware_info *ucode = NULL; - for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { + for (i = 0; i < adev->firmware.max_ucodes; i++) { ucode = &adev->firmware.ucode[i]; if (ucode->fw) { ucode->mc_addr = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index a8a4230729f9..758f03a1770d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -50,6 +50,14 @@ struct smc_firmware_header_v1_0 { }; /* version_major=1, version_minor=0 */ +struct psp_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t sos_offset_bytes; + uint32_t sos_size_bytes; +}; + +/* version_major=1, version_minor=0 */ struct gfx_firmware_header_v1_0 { struct common_firmware_header header; uint32_t ucode_feature_version; @@ -110,6 +118,7 @@ union amdgpu_firmware_header { struct common_firmware_header common; struct mc_firmware_header_v1_0 mc; struct smc_firmware_header_v1_0 smc; + struct psp_firmware_header_v1_0 psp; struct gfx_firmware_header_v1_0 gfx; struct rlc_firmware_header_v1_0 rlc; struct rlc_firmware_header_v2_0 rlc_v2_0; @@ -128,9 +137,14 @@ enum AMDGPU_UCODE_ID { AMDGPU_UCODE_ID_CP_PFP, AMDGPU_UCODE_ID_CP_ME, AMDGPU_UCODE_ID_CP_MEC1, + AMDGPU_UCODE_ID_CP_MEC1_JT, AMDGPU_UCODE_ID_CP_MEC2, + AMDGPU_UCODE_ID_CP_MEC2_JT, AMDGPU_UCODE_ID_RLC_G, AMDGPU_UCODE_ID_STORAGE, + AMDGPU_UCODE_ID_SMC, + AMDGPU_UCODE_ID_UVD, + AMDGPU_UCODE_ID_VCE, AMDGPU_UCODE_ID_MAXIMUM, }; @@ -161,6 +175,8 @@ struct amdgpu_firmware_info { uint64_t mc_addr; /* kernel linear address */ void *kaddr; + /* ucode_size_bytes */ + uint32_t ucode_size; }; void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); @@ -174,4 +190,7 @@ bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, int amdgpu_ucode_init_bo(struct amdgpu_device *adev); int amdgpu_ucode_fini_bo(struct amdgpu_device *adev); +enum amdgpu_firmware_load_type +amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 6d6ab7f11b4c..0b92dd0c1d70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -67,6 +67,14 @@ #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" +#define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" + +#define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) +#define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) +#define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) +#define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) +#define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) + /** * amdgpu_uvd_cs_ctx - Command submission parser context * @@ -101,6 +109,8 @@ MODULE_FIRMWARE(FIRMWARE_POLARIS10); MODULE_FIRMWARE(FIRMWARE_POLARIS11); MODULE_FIRMWARE(FIRMWARE_POLARIS12); +MODULE_FIRMWARE(FIRMWARE_VEGA10); + static void amdgpu_uvd_idle_work_handler(struct work_struct *work); int amdgpu_uvd_sw_init(struct amdgpu_device *adev) @@ -151,6 +161,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_POLARIS11: fw_name = FIRMWARE_POLARIS11; break; + case CHIP_VEGA10: + fw_name = FIRMWARE_VEGA10; + break; case CHIP_POLARIS12: fw_name = FIRMWARE_POLARIS12; break; @@ -203,9 +216,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", version_major, version_minor); - bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) - + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE + bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) + bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); @@ -319,11 +334,13 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) unsigned offset; hdr = (const struct common_firmware_header *)adev->uvd.fw->data; - offset = le32_to_cpu(hdr->ucode_array_offset_bytes); - memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, - le32_to_cpu(hdr->ucode_size_bytes)); - size -= le32_to_cpu(hdr->ucode_size_bytes); - ptr += le32_to_cpu(hdr->ucode_size_bytes); + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + offset = le32_to_cpu(hdr->ucode_array_offset_bytes); + memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, + le32_to_cpu(hdr->ucode_size_bytes)); + size -= le32_to_cpu(hdr->ucode_size_bytes); + ptr += le32_to_cpu(hdr->ucode_size_bytes); + } memset_io(ptr, 0, size); } @@ -936,6 +953,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, struct dma_fence *f = NULL; struct amdgpu_device *adev = ring->adev; uint64_t addr; + uint32_t data[4]; int i, r; memset(&tv, 0, sizeof(tv)); @@ -961,16 +979,28 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (r) goto err; + if (adev->asic_type >= CHIP_VEGA10) { + data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); + data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); + data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); + data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); + } else { + data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); + data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); + data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); + data[3] = PACKET0(mmUVD_NO_OP, 0); + } + ib = &job->ibs[0]; addr = amdgpu_bo_gpu_offset(bo); - ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); + ib->ptr[0] = data[0]; ib->ptr[1] = addr; - ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); + ib->ptr[2] = data[1]; ib->ptr[3] = addr >> 32; - ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); + ib->ptr[4] = data[2]; ib->ptr[5] = 0; for (i = 6; i < 16; i += 2) { - ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0); + ib->ptr[i] = data[3]; ib->ptr[i+1] = 0; } ib->length_dw = 16; @@ -1108,6 +1138,9 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) container_of(work, struct amdgpu_device, uvd.idle_work.work); unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); + if (amdgpu_sriov_vf(adev)) + return; + if (fences == 0) { if (adev->pm.dpm_enabled) { amdgpu_dpm_enable_uvd(adev, false); @@ -1129,6 +1162,9 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); + if (amdgpu_sriov_vf(adev)) + return; + if (set_clocks) { if (adev->pm.dpm_enabled) { amdgpu_dpm_enable_uvd(adev, true); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h index c10682baccae..3553b92bf69a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h @@ -24,6 +24,35 @@ #ifndef __AMDGPU_UVD_H__ #define __AMDGPU_UVD_H__ +#define AMDGPU_DEFAULT_UVD_HANDLES 10 +#define AMDGPU_MAX_UVD_HANDLES 40 +#define AMDGPU_UVD_STACK_SIZE (200*1024) +#define AMDGPU_UVD_HEAP_SIZE (256*1024) +#define AMDGPU_UVD_SESSION_SIZE (50*1024) +#define AMDGPU_UVD_FIRMWARE_OFFSET 256 + +struct amdgpu_uvd { + struct amdgpu_bo *vcpu_bo; + void *cpu_addr; + uint64_t gpu_addr; + unsigned fw_version; + void *saved_bo; + unsigned max_handles; + atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; + struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; + struct delayed_work idle_work; + const struct firmware *fw; /* UVD firmware */ + struct amdgpu_ring ring; + struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS]; + struct amdgpu_irq_src irq; + bool address_64_bit; + bool use_ctx_buf; + struct amd_sched_entity entity; + struct amd_sched_entity entity_enc; + uint32_t srbm_soft_reset; + unsigned num_enc_rings; +}; + int amdgpu_uvd_sw_init(struct amdgpu_device *adev); int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); int amdgpu_uvd_suspend(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index e2c06780ce49..0184197eb000 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -54,6 +54,8 @@ #define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin" #define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin" +#define FIRMWARE_VEGA10 "amdgpu/vega10_vce.bin" + #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); MODULE_FIRMWARE(FIRMWARE_KABINI); @@ -69,6 +71,8 @@ MODULE_FIRMWARE(FIRMWARE_POLARIS10); MODULE_FIRMWARE(FIRMWARE_POLARIS11); MODULE_FIRMWARE(FIRMWARE_POLARIS12); +MODULE_FIRMWARE(FIRMWARE_VEGA10); + static void amdgpu_vce_idle_work_handler(struct work_struct *work); /** @@ -123,6 +127,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_POLARIS11: fw_name = FIRMWARE_POLARIS11; break; + case CHIP_VEGA10: + fw_name = FIRMWARE_VEGA10; + break; case CHIP_POLARIS12: fw_name = FIRMWARE_POLARIS12; break; @@ -313,6 +320,9 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work) container_of(work, struct amdgpu_device, vce.idle_work.work); unsigned i, count = 0; + if (amdgpu_sriov_vf(adev)) + return; + for (i = 0; i < adev->vce.num_rings; i++) count += amdgpu_fence_count_emitted(&adev->vce.ring[i]); @@ -343,6 +353,9 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; bool set_clocks; + if (amdgpu_sriov_vf(adev)) + return; + mutex_lock(&adev->vce.idle_mutex); set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work); if (set_clocks) { @@ -944,6 +957,10 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) unsigned i; int r; + /* TODO: remove it if VCE can work for sriov */ + if (amdgpu_sriov_vf(adev)) + return 0; + r = amdgpu_ring_alloc(ring, 16); if (r) { DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n", @@ -982,6 +999,10 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) struct dma_fence *fence = NULL; long r; + /* TODO: remove it if VCE can work for sriov */ + if (amdgpu_sriov_vf(ring->adev)) + return 0; + /* skip vce ring1/2 ib test for now, since it's not reliable */ if (ring != &ring->adev->vce.ring[0]) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index d98041f7508d..0a7f18c461e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -24,6 +24,31 @@ #ifndef __AMDGPU_VCE_H__ #define __AMDGPU_VCE_H__ +#define AMDGPU_MAX_VCE_HANDLES 16 +#define AMDGPU_VCE_FIRMWARE_OFFSET 256 + +#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) +#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) + +struct amdgpu_vce { + struct amdgpu_bo *vcpu_bo; + uint64_t gpu_addr; + unsigned fw_version; + unsigned fb_version; + atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; + struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; + uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; + struct delayed_work idle_work; + struct mutex idle_mutex; + const struct firmware *fw; /* VCE firmware */ + struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; + struct amdgpu_irq_src irq; + unsigned harvest_config; + struct amd_sched_entity entity; + uint32_t srbm_soft_reset; + unsigned num_rings; +}; + int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); int amdgpu_vce_sw_fini(struct amdgpu_device *adev); int amdgpu_vce_suspend(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index dcfb7df3caf4..ecef35a1fe33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -75,6 +75,15 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm) return -ENOMEM; } + r = amdgpu_vm_alloc_pts(adev, bo_va->vm, AMDGPU_CSA_VADDR, + AMDGPU_CSA_SIZE); + if (r) { + DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r); + amdgpu_vm_bo_rmv(adev, bo_va); + ttm_eu_backoff_reservation(&ticket, &list); + return r; + } + r = amdgpu_vm_bo_map(adev, bo_va, AMDGPU_CSA_VADDR, 0,AMDGPU_CSA_SIZE, AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_EXECUTABLE); @@ -97,7 +106,8 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; - mutex_init(&adev->virt.lock); + mutex_init(&adev->virt.lock_kiq); + mutex_init(&adev->virt.lock_reset); } uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) @@ -110,14 +120,14 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) BUG_ON(!ring->funcs->emit_rreg); - mutex_lock(&adev->virt.lock); + mutex_lock(&adev->virt.lock_kiq); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_hdp_flush(ring); amdgpu_ring_emit_rreg(ring, reg); amdgpu_ring_emit_hdp_invalidate(ring); amdgpu_fence_emit(ring, &f); amdgpu_ring_commit(ring); - mutex_unlock(&adev->virt.lock); + mutex_unlock(&adev->virt.lock_kiq); r = dma_fence_wait(f, false); if (r) @@ -138,14 +148,14 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) BUG_ON(!ring->funcs->emit_wreg); - mutex_lock(&adev->virt.lock); + mutex_lock(&adev->virt.lock_kiq); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_hdp_flush(ring); amdgpu_ring_emit_wreg(ring, reg, v); amdgpu_ring_emit_hdp_invalidate(ring); amdgpu_fence_emit(ring, &f); amdgpu_ring_commit(ring); - mutex_unlock(&adev->virt.lock); + mutex_unlock(&adev->virt.lock_kiq); r = dma_fence_wait(f, false); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 675e12c42532..1ee0a190b33b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -30,6 +30,12 @@ #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ +struct amdgpu_mm_table { + struct amdgpu_bo *bo; + uint32_t *cpu_addr; + uint64_t gpu_addr; +}; + /** * struct amdgpu_virt_ops - amdgpu device virt operations */ @@ -46,10 +52,12 @@ struct amdgpu_virt { uint64_t csa_vmid0_addr; bool chained_ib_support; uint32_t reg_val_offs; - struct mutex lock; + struct mutex lock_kiq; + struct mutex lock_reset; struct amdgpu_irq_src ack_irq; struct amdgpu_irq_src rcv_irq; - struct delayed_work flr_work; + struct work_struct flr_work; + struct amdgpu_mm_table mm_table; const struct amdgpu_virt_ops *ops; }; @@ -89,5 +97,6 @@ void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); +int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index bd0d33125c18..0235d7933efd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -57,6 +57,8 @@ struct amdgpu_pte_update_params { /* amdgpu device we do this update for */ struct amdgpu_device *adev; + /* optional amdgpu_vm we do this update for */ + struct amdgpu_vm *vm; /* address where to copy page table entries from */ uint64_t src; /* indirect buffer to fill with commands */ @@ -64,33 +66,49 @@ struct amdgpu_pte_update_params { /* Function which actually does the update */ void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, - uint32_t flags); + uint64_t flags); /* indicate update pt or its shadow */ bool shadow; }; +/* Helper to disable partial resident texture feature from a fence callback */ +struct amdgpu_prt_cb { + struct amdgpu_device *adev; + struct dma_fence_cb cb; +}; + /** - * amdgpu_vm_num_pde - return the number of page directory entries + * amdgpu_vm_num_entries - return the number of entries in a PD/PT * * @adev: amdgpu_device pointer * - * Calculate the number of page directory entries. + * Calculate the number of entries in a page directory or page table. */ -static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) +static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, + unsigned level) { - return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; + if (level == 0) + /* For the root directory */ + return adev->vm_manager.max_pfn >> + (amdgpu_vm_block_size * adev->vm_manager.num_level); + else if (level == adev->vm_manager.num_level) + /* For the page tables on the leaves */ + return AMDGPU_VM_PTE_COUNT; + else + /* Everything in between */ + return 1 << amdgpu_vm_block_size; } /** - * amdgpu_vm_directory_size - returns the size of the page directory in bytes + * amdgpu_vm_bo_size - returns the size of the BOs in bytes * * @adev: amdgpu_device pointer * - * Calculate the size of the page directory in bytes. + * Calculate the size of the BO for a page directory or page table in bytes. */ -static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) +static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) { - return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); + return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); } /** @@ -107,15 +125,56 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, struct amdgpu_bo_list_entry *entry) { - entry->robj = vm->page_directory; + entry->robj = vm->root.bo; entry->priority = 0; - entry->tv.bo = &vm->page_directory->tbo; + entry->tv.bo = &entry->robj->tbo; entry->tv.shared = true; entry->user_pages = NULL; list_add(&entry->tv.head, validated); } /** + * amdgpu_vm_validate_layer - validate a single page table level + * + * @parent: parent page table level + * @validate: callback to do the validation + * @param: parameter for the validation callback + * + * Validate the page table BOs on command submission if neccessary. + */ +static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, + int (*validate)(void *, struct amdgpu_bo *), + void *param) +{ + unsigned i; + int r; + + if (!parent->entries) + return 0; + + for (i = 0; i <= parent->last_entry_used; ++i) { + struct amdgpu_vm_pt *entry = &parent->entries[i]; + + if (!entry->bo) + continue; + + r = validate(param, entry->bo); + if (r) + return r; + + /* + * Recurse into the sub directory. This is harmless because we + * have only a maximum of 5 layers. + */ + r = amdgpu_vm_validate_level(entry, validate, param); + if (r) + return r; + } + + return r; +} + +/** * amdgpu_vm_validate_pt_bos - validate the page table BOs * * @adev: amdgpu device pointer @@ -130,8 +189,6 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, void *param) { uint64_t num_evictions; - unsigned i; - int r; /* We only need to validate the page tables * if they aren't already valid. @@ -140,19 +197,33 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (num_evictions == vm->last_eviction_counter) return 0; - /* add the vm page table to the list */ - for (i = 0; i <= vm->max_pde_used; ++i) { - struct amdgpu_bo *bo = vm->page_tables[i].bo; + return amdgpu_vm_validate_level(&vm->root, validate, param); +} - if (!bo) +/** + * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail + * + * @adev: amdgpu device instance + * @vm: vm providing the BOs + * + * Move the PT BOs to the tail of the LRU. + */ +static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) +{ + unsigned i; + + if (!parent->entries) + return; + + for (i = 0; i <= parent->last_entry_used; ++i) { + struct amdgpu_vm_pt *entry = &parent->entries[i]; + + if (!entry->bo) continue; - r = validate(param, bo); - if (r) - return r; + ttm_bo_move_to_lru_tail(&entry->bo->tbo); + amdgpu_vm_move_level_in_lru(entry); } - - return 0; } /** @@ -167,18 +238,131 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct ttm_bo_global *glob = adev->mman.bdev.glob; - unsigned i; spin_lock(&glob->lru_lock); - for (i = 0; i <= vm->max_pde_used; ++i) { - struct amdgpu_bo *bo = vm->page_tables[i].bo; + amdgpu_vm_move_level_in_lru(&vm->root); + spin_unlock(&glob->lru_lock); +} - if (!bo) - continue; + /** + * amdgpu_vm_alloc_levels - allocate the PD/PT levels + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @saddr: start of the address range + * @eaddr: end of the address range + * + * Make sure the page directories and page tables are allocated + */ +static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_vm_pt *parent, + uint64_t saddr, uint64_t eaddr, + unsigned level) +{ + unsigned shift = (adev->vm_manager.num_level - level) * + amdgpu_vm_block_size; + unsigned pt_idx, from, to; + int r; + + if (!parent->entries) { + unsigned num_entries = amdgpu_vm_num_entries(adev, level); - ttm_bo_move_to_lru_tail(&bo->tbo); + parent->entries = drm_calloc_large(num_entries, + sizeof(struct amdgpu_vm_pt)); + if (!parent->entries) + return -ENOMEM; + memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); } - spin_unlock(&glob->lru_lock); + + from = saddr >> shift; + to = eaddr >> shift; + if (from >= amdgpu_vm_num_entries(adev, level) || + to >= amdgpu_vm_num_entries(adev, level)) + return -EINVAL; + + if (to > parent->last_entry_used) + parent->last_entry_used = to; + + ++level; + saddr = saddr & ((1 << shift) - 1); + eaddr = eaddr & ((1 << shift) - 1); + + /* walk over the address space and allocate the page tables */ + for (pt_idx = from; pt_idx <= to; ++pt_idx) { + struct reservation_object *resv = vm->root.bo->tbo.resv; + struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; + struct amdgpu_bo *pt; + + if (!entry->bo) { + r = amdgpu_bo_create(adev, + amdgpu_vm_bo_size(adev, level), + AMDGPU_GPU_PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_NO_CPU_ACCESS | + AMDGPU_GEM_CREATE_SHADOW | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED, + NULL, resv, &pt); + if (r) + return r; + + /* Keep a reference to the root directory to avoid + * freeing them up in the wrong order. + */ + pt->parent = amdgpu_bo_ref(vm->root.bo); + + entry->bo = pt; + entry->addr = 0; + } + + if (level < adev->vm_manager.num_level) { + uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; + uint64_t sub_eaddr = (pt_idx == to) ? eaddr : + ((1 << shift) - 1); + r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, + sub_eaddr, level); + if (r) + return r; + } + } + + return 0; +} + +/** + * amdgpu_vm_alloc_pts - Allocate page tables. + * + * @adev: amdgpu_device pointer + * @vm: VM to allocate page tables for + * @saddr: Start address which needs to be allocated + * @size: Size from start address we need. + * + * Make sure the page tables are allocated. + */ +int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + uint64_t saddr, uint64_t size) +{ + uint64_t last_pfn; + uint64_t eaddr; + + /* validate the parameters */ + if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) + return -EINVAL; + + eaddr = saddr + size - 1; + last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; + if (last_pfn >= adev->vm_manager.max_pfn) { + dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", + last_pfn, adev->vm_manager.max_pfn); + return -EINVAL; + } + + saddr /= AMDGPU_GPU_PAGE_SIZE; + eaddr /= AMDGPU_GPU_PAGE_SIZE; + + return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); } static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, @@ -369,6 +553,16 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) return false; } +static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) +{ + u64 addr = mc_addr; + + if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr) + addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr); + + return addr; +} + /** * amdgpu_vm_flush - hardware flush the vm * @@ -391,41 +585,59 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) id->oa_size != job->oa_size); int r; - if (ring->funcs->emit_pipeline_sync && ( - job->vm_needs_flush || gds_switch_needed || - amdgpu_vm_ring_has_compute_vm_bug(ring))) - amdgpu_ring_emit_pipeline_sync(ring); + if (job->vm_needs_flush || gds_switch_needed || + amdgpu_vm_is_gpu_reset(adev, id) || + amdgpu_vm_ring_has_compute_vm_bug(ring)) { + unsigned patch_offset = 0; - if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || - amdgpu_vm_is_gpu_reset(adev, id))) { - struct dma_fence *fence; + if (ring->funcs->init_cond_exec) + patch_offset = amdgpu_ring_init_cond_exec(ring); - trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); - amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); + if (ring->funcs->emit_pipeline_sync && + (job->vm_needs_flush || gds_switch_needed || + amdgpu_vm_ring_has_compute_vm_bug(ring))) + amdgpu_ring_emit_pipeline_sync(ring); - r = amdgpu_fence_emit(ring, &fence); - if (r) - return r; + if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || + amdgpu_vm_is_gpu_reset(adev, id))) { + struct dma_fence *fence; + u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr); - mutex_lock(&adev->vm_manager.lock); - dma_fence_put(id->last_flush); - id->last_flush = fence; - mutex_unlock(&adev->vm_manager.lock); - } + trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id); + amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr); - if (gds_switch_needed) { - id->gds_base = job->gds_base; - id->gds_size = job->gds_size; - id->gws_base = job->gws_base; - id->gws_size = job->gws_size; - id->oa_base = job->oa_base; - id->oa_size = job->oa_size; - amdgpu_ring_emit_gds_switch(ring, job->vm_id, - job->gds_base, job->gds_size, - job->gws_base, job->gws_size, - job->oa_base, job->oa_size); - } + r = amdgpu_fence_emit(ring, &fence); + if (r) + return r; + + mutex_lock(&adev->vm_manager.lock); + dma_fence_put(id->last_flush); + id->last_flush = fence; + mutex_unlock(&adev->vm_manager.lock); + } + + if (gds_switch_needed) { + id->gds_base = job->gds_base; + id->gds_size = job->gds_size; + id->gws_base = job->gws_base; + id->gws_size = job->gws_size; + id->oa_base = job->oa_base; + id->oa_size = job->oa_size; + amdgpu_ring_emit_gds_switch(ring, job->vm_id, + job->gds_base, job->gds_size, + job->gws_base, job->gws_size, + job->oa_base, job->oa_size); + } + + if (ring->funcs->patch_cond_exec) + amdgpu_ring_patch_cond_exec(ring, patch_offset); + /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ + if (ring->funcs->emit_switch_buffer) { + amdgpu_ring_emit_switch_buffer(ring); + amdgpu_ring_emit_switch_buffer(ring); + } + } return 0; } @@ -490,7 +702,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, - uint32_t flags) + uint64_t flags) { trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); @@ -519,7 +731,7 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, - uint32_t flags) + uint64_t flags) { uint64_t src = (params->src + (addr >> 12) * 8); @@ -554,24 +766,24 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) } /* - * amdgpu_vm_update_pdes - make sure that page directory is valid + * amdgpu_vm_update_level - update a single level in the hierarchy * * @adev: amdgpu_device pointer * @vm: requested vm - * @start: start of GPU address range - * @end: end of GPU address range + * @parent: parent directory * - * Allocates new page tables if necessary - * and updates the page directory. + * Makes sure all entries in @parent are up to date. * Returns 0 for success, error for failure. */ -int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, - struct amdgpu_vm *vm) +static int amdgpu_vm_update_level(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_vm_pt *parent, + unsigned level) { struct amdgpu_bo *shadow; struct amdgpu_ring *ring; uint64_t pd_addr, shadow_addr; - uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; + uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; unsigned count = 0, pt_idx, ndw; struct amdgpu_job *job; @@ -580,16 +792,19 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, int r; + if (!parent->entries) + return 0; ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - shadow = vm->page_directory->shadow; /* padding, etc. */ ndw = 64; /* assume the worst case */ - ndw += vm->max_pde_used * 6; + ndw += parent->last_entry_used * 6; + + pd_addr = amdgpu_bo_gpu_offset(parent->bo); - pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); + shadow = parent->bo->shadow; if (shadow) { r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); if (r) @@ -608,9 +823,9 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, params.adev = adev; params.ib = &job->ibs[0]; - /* walk over the address space and update the page directory */ - for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { - struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; + /* walk over the address space and update the directory */ + for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { + struct amdgpu_bo *bo = parent->entries[pt_idx].bo; uint64_t pde, pt; if (bo == NULL) @@ -626,10 +841,10 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, } pt = amdgpu_bo_gpu_offset(bo); - if (vm->page_tables[pt_idx].addr == pt) + if (parent->entries[pt_idx].addr == pt) continue; - vm->page_tables[pt_idx].addr = pt; + parent->entries[pt_idx].addr = pt; pde = pd_addr + pt_idx * 8; if (((last_pde + 8 * count) != pde) || @@ -637,15 +852,18 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { if (count) { + uint64_t pt_addr = + amdgpu_vm_adjust_mc_addr(adev, last_pt); + if (shadow) amdgpu_vm_do_set_ptes(¶ms, last_shadow, - last_pt, count, + pt_addr, count, incr, AMDGPU_PTE_VALID); amdgpu_vm_do_set_ptes(¶ms, last_pde, - last_pt, count, incr, + pt_addr, count, incr, AMDGPU_PTE_VALID); } @@ -659,36 +877,51 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, } if (count) { - if (vm->page_directory->shadow) - amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt, + uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt); + + if (vm->root.bo->shadow) + amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr, count, incr, AMDGPU_PTE_VALID); - amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt, + amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr, count, incr, AMDGPU_PTE_VALID); } if (params.ib->length_dw == 0) { amdgpu_job_free(job); - return 0; - } - - amdgpu_ring_pad_ib(ring, params.ib); - amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, - AMDGPU_FENCE_OWNER_VM); - if (shadow) - amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, + } else { + amdgpu_ring_pad_ib(ring, params.ib); + amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, AMDGPU_FENCE_OWNER_VM); + if (shadow) + amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, + AMDGPU_FENCE_OWNER_VM); - WARN_ON(params.ib->length_dw > ndw); - r = amdgpu_job_submit(job, ring, &vm->entity, - AMDGPU_FENCE_OWNER_VM, &fence); - if (r) - goto error_free; + WARN_ON(params.ib->length_dw > ndw); + r = amdgpu_job_submit(job, ring, &vm->entity, + AMDGPU_FENCE_OWNER_VM, &fence); + if (r) + goto error_free; + + amdgpu_bo_fence(parent->bo, fence, true); + dma_fence_put(vm->last_dir_update); + vm->last_dir_update = dma_fence_get(fence); + dma_fence_put(fence); + } + /* + * Recurse into the subdirectories. This recursion is harmless because + * we only have a maximum of 5 layers. + */ + for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { + struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; - amdgpu_bo_fence(vm->page_directory, fence, true); - dma_fence_put(vm->page_directory_fence); - vm->page_directory_fence = dma_fence_get(fence); - dma_fence_put(fence); + if (!entry->bo) + continue; + + r = amdgpu_vm_update_level(adev, vm, entry, level + 1); + if (r) + return r; + } return 0; @@ -697,6 +930,47 @@ error_free: return r; } +/* + * amdgpu_vm_update_directories - make sure that all directories are valid + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * + * Makes sure all directories are up to date. + * Returns 0 for success, error for failure. + */ +int amdgpu_vm_update_directories(struct amdgpu_device *adev, + struct amdgpu_vm *vm) +{ + return amdgpu_vm_update_level(adev, vm, &vm->root, 0); +} + +/** + * amdgpu_vm_find_pt - find the page table for an address + * + * @p: see amdgpu_pte_update_params definition + * @addr: virtual address in question + * + * Find the page table BO for a virtual address, return NULL when none found. + */ +static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, + uint64_t addr) +{ + struct amdgpu_vm_pt *entry = &p->vm->root; + unsigned idx, level = p->adev->vm_manager.num_level; + + while (entry->entries) { + idx = addr >> (amdgpu_vm_block_size * level--); + idx %= amdgpu_bo_size(entry->bo) / 8; + entry = &entry->entries[idx]; + } + + if (level) + return NULL; + + return entry->bo; +} + /** * amdgpu_vm_update_ptes - make sure that page tables are valid * @@ -710,23 +984,25 @@ error_free: * Update the page tables in the range @start - @end. */ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, - struct amdgpu_vm *vm, uint64_t start, uint64_t end, - uint64_t dst, uint32_t flags) + uint64_t dst, uint64_t flags) { const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; uint64_t cur_pe_start, cur_nptes, cur_dst; uint64_t addr; /* next GPU address to be updated */ - uint64_t pt_idx; struct amdgpu_bo *pt; unsigned nptes; /* next number of ptes to be updated */ uint64_t next_pe_start; /* initialize the variables */ addr = start; - pt_idx = addr >> amdgpu_vm_block_size; - pt = vm->page_tables[pt_idx].bo; + pt = amdgpu_vm_get_pt(params, addr); + if (!pt) { + pr_err("PT not found, aborting update_ptes\n"); + return; + } + if (params->shadow) { if (!pt->shadow) return; @@ -748,8 +1024,12 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, /* walk over the address space and update the page tables */ while (addr < end) { - pt_idx = addr >> amdgpu_vm_block_size; - pt = vm->page_tables[pt_idx].bo; + pt = amdgpu_vm_get_pt(params, addr); + if (!pt) { + pr_err("PT not found, aborting update_ptes\n"); + return; + } + if (params->shadow) { if (!pt->shadow) return; @@ -800,9 +1080,8 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, * @flags: hw mapping flags */ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, - struct amdgpu_vm *vm, uint64_t start, uint64_t end, - uint64_t dst, uint32_t flags) + uint64_t dst, uint64_t flags) { /** * The MC L1 TLB supports variable sized pages, based on a fragment @@ -834,25 +1113,25 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, if (params->src || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { - amdgpu_vm_update_ptes(params, vm, start, end, dst, flags); + amdgpu_vm_update_ptes(params, start, end, dst, flags); return; } /* handle the 4K area at the beginning */ if (start != frag_start) { - amdgpu_vm_update_ptes(params, vm, start, frag_start, + amdgpu_vm_update_ptes(params, start, frag_start, dst, flags); dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; } /* handle the area in the middle */ - amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst, + amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, flags | frag_flags); /* handle the 4K area at the end */ if (frag_end != end) { dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; - amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags); + amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); } } @@ -879,7 +1158,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, dma_addr_t *pages_addr, struct amdgpu_vm *vm, uint64_t start, uint64_t last, - uint32_t flags, uint64_t addr, + uint64_t flags, uint64_t addr, struct dma_fence **fence) { struct amdgpu_ring *ring; @@ -892,14 +1171,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, memset(¶ms, 0, sizeof(params)); params.adev = adev; + params.vm = vm; params.src = src; ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - memset(¶ms, 0, sizeof(params)); - params.adev = adev; - params.src = src; - /* sync to everything on unmapping */ if (!(flags & AMDGPU_PTE_VALID)) owner = AMDGPU_FENCE_OWNER_UNDEFINED; @@ -967,19 +1243,19 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_free; - r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, + r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, owner); if (r) goto error_free; - r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); + r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); if (r) goto error_free; params.shadow = true; - amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); + amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); params.shadow = false; - amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); + amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); amdgpu_ring_pad_ib(ring, params.ib); WARN_ON(params.ib->length_dw > ndw); @@ -988,12 +1264,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, if (r) goto error_free; - amdgpu_bo_fence(vm->page_directory, f, true); - if (fence) { - dma_fence_put(*fence); - *fence = dma_fence_get(f); - } - dma_fence_put(f); + amdgpu_bo_fence(vm->root.bo, f, true); + dma_fence_put(*fence); + *fence = f; return 0; error_free: @@ -1020,11 +1293,11 @@ error_free: */ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, struct dma_fence *exclusive, - uint32_t gtt_flags, + uint64_t gtt_flags, dma_addr_t *pages_addr, struct amdgpu_vm *vm, struct amdgpu_bo_va_mapping *mapping, - uint32_t flags, + uint64_t flags, struct drm_mm_node *nodes, struct dma_fence **fence) { @@ -1039,6 +1312,12 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) flags &= ~AMDGPU_PTE_WRITEABLE; + flags &= ~AMDGPU_PTE_EXECUTABLE; + flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; + + flags &= ~AMDGPU_PTE_MTYPE_MASK; + flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); + trace_amdgpu_vm_bo_update(mapping); pfn = mapping->offset >> PAGE_SHIFT; @@ -1111,13 +1390,13 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_vm *vm = bo_va->vm; struct amdgpu_bo_va_mapping *mapping; dma_addr_t *pages_addr = NULL; - uint32_t gtt_flags, flags; + uint64_t gtt_flags, flags; struct ttm_mem_reg *mem; struct drm_mm_node *nodes; struct dma_fence *exclusive; int r; - if (clear) { + if (clear || !bo_va->bo) { mem = NULL; nodes = NULL; exclusive = NULL; @@ -1134,9 +1413,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); } - flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); - gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && - adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? flags : 0; + if (bo_va->bo) { + flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); + gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && + adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? + flags : 0; + } else { + flags = 0x0; + gtt_flags = ~0x0; + } spin_lock(&vm->status_lock); if (!list_empty(&bo_va->vm_status)) @@ -1171,10 +1456,142 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, } /** + * amdgpu_vm_update_prt_state - update the global PRT state + */ +static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) +{ + unsigned long flags; + bool enable; + + spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); + enable = !!atomic_read(&adev->vm_manager.num_prt_users); + adev->gart.gart_funcs->set_prt(adev, enable); + spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); +} + +/** + * amdgpu_vm_prt_get - add a PRT user + */ +static void amdgpu_vm_prt_get(struct amdgpu_device *adev) +{ + if (!adev->gart.gart_funcs->set_prt) + return; + + if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) + amdgpu_vm_update_prt_state(adev); +} + +/** + * amdgpu_vm_prt_put - drop a PRT user + */ +static void amdgpu_vm_prt_put(struct amdgpu_device *adev) +{ + if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) + amdgpu_vm_update_prt_state(adev); +} + +/** + * amdgpu_vm_prt_cb - callback for updating the PRT status + */ +static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) +{ + struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); + + amdgpu_vm_prt_put(cb->adev); + kfree(cb); +} + +/** + * amdgpu_vm_add_prt_cb - add callback for updating the PRT status + */ +static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, + struct dma_fence *fence) +{ + struct amdgpu_prt_cb *cb; + + if (!adev->gart.gart_funcs->set_prt) + return; + + cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); + if (!cb) { + /* Last resort when we are OOM */ + if (fence) + dma_fence_wait(fence, false); + + amdgpu_vm_prt_put(cb->adev); + } else { + cb->adev = adev; + if (!fence || dma_fence_add_callback(fence, &cb->cb, + amdgpu_vm_prt_cb)) + amdgpu_vm_prt_cb(fence, &cb->cb); + } +} + +/** + * amdgpu_vm_free_mapping - free a mapping + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @mapping: mapping to be freed + * @fence: fence of the unmap operation + * + * Free a mapping and make sure we decrease the PRT usage count if applicable. + */ +static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_bo_va_mapping *mapping, + struct dma_fence *fence) +{ + if (mapping->flags & AMDGPU_PTE_PRT) + amdgpu_vm_add_prt_cb(adev, fence); + kfree(mapping); +} + +/** + * amdgpu_vm_prt_fini - finish all prt mappings + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * + * Register a cleanup callback to disable PRT support after VM dies. + */ +static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) +{ + struct reservation_object *resv = vm->root.bo->tbo.resv; + struct dma_fence *excl, **shared; + unsigned i, shared_count; + int r; + + r = reservation_object_get_fences_rcu(resv, &excl, + &shared_count, &shared); + if (r) { + /* Not enough memory to grab the fence list, as last resort + * block for all the fences to complete. + */ + reservation_object_wait_timeout_rcu(resv, true, false, + MAX_SCHEDULE_TIMEOUT); + return; + } + + /* Add a callback for each fence in the reservation object */ + amdgpu_vm_prt_get(adev); + amdgpu_vm_add_prt_cb(adev, excl); + + for (i = 0; i < shared_count; ++i) { + amdgpu_vm_prt_get(adev); + amdgpu_vm_add_prt_cb(adev, shared[i]); + } + + kfree(shared); +} + +/** * amdgpu_vm_clear_freed - clear freed BOs in the PT * * @adev: amdgpu_device pointer * @vm: requested vm + * @fence: optional resulting fence (unchanged if no work needed to be done + * or if an error occurred) * * Make sure all freed BOs are cleared in the PT. * Returns 0 for success. @@ -1182,9 +1599,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, * PTs have to be reserved and mutex must be locked! */ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, - struct amdgpu_vm *vm) + struct amdgpu_vm *vm, + struct dma_fence **fence) { struct amdgpu_bo_va_mapping *mapping; + struct dma_fence *f = NULL; int r; while (!list_empty(&vm->freed)) { @@ -1193,12 +1612,21 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, list_del(&mapping->list); r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, - 0, 0, NULL); - kfree(mapping); - if (r) + 0, 0, &f); + amdgpu_vm_free_mapping(adev, vm, mapping, f); + if (r) { + dma_fence_put(f); return r; + } + } + if (fence && f) { + dma_fence_put(*fence); + *fence = f; + } else { + dma_fence_put(f); } + return 0; } @@ -1271,7 +1699,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, INIT_LIST_HEAD(&bo_va->invalids); INIT_LIST_HEAD(&bo_va->vm_status); - list_add_tail(&bo_va->bo_list, &bo->va); + if (bo) + list_add_tail(&bo_va->bo_list, &bo->va); return bo_va; } @@ -1298,9 +1727,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping; struct amdgpu_vm *vm = bo_va->vm; struct interval_tree_node *it; - unsigned last_pfn, pt_idx; uint64_t eaddr; - int r; /* validate the parameters */ if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || @@ -1309,15 +1736,9 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, /* make sure object fit at this offset */ eaddr = saddr + size - 1; - if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) - return -EINVAL; - - last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; - if (last_pfn >= adev->vm_manager.max_pfn) { - dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", - last_pfn, adev->vm_manager.max_pfn); + if (saddr >= eaddr || + (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) return -EINVAL; - } saddr /= AMDGPU_GPU_PAGE_SIZE; eaddr /= AMDGPU_GPU_PAGE_SIZE; @@ -1330,15 +1751,12 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, tmp->it.start, tmp->it.last + 1); - r = -EINVAL; - goto error; + return -EINVAL; } mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); - if (!mapping) { - r = -ENOMEM; - goto error; - } + if (!mapping) + return -ENOMEM; INIT_LIST_HEAD(&mapping->list); mapping->it.start = saddr; @@ -1349,53 +1767,74 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, list_add(&mapping->list, &bo_va->invalids); interval_tree_insert(&mapping->it, &vm->va); - /* Make sure the page tables are allocated */ - saddr >>= amdgpu_vm_block_size; - eaddr >>= amdgpu_vm_block_size; - - BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); + if (flags & AMDGPU_PTE_PRT) + amdgpu_vm_prt_get(adev); - if (eaddr > vm->max_pde_used) - vm->max_pde_used = eaddr; + return 0; +} - /* walk over the address space and allocate the page tables */ - for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { - struct reservation_object *resv = vm->page_directory->tbo.resv; - struct amdgpu_bo *pt; +/** + * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings + * + * @adev: amdgpu_device pointer + * @bo_va: bo_va to store the address + * @saddr: where to map the BO + * @offset: requested offset in the BO + * @flags: attributes of pages (read/write/valid/etc.) + * + * Add a mapping of the BO at the specefied addr into the VM. Replace existing + * mappings as we do so. + * Returns 0 for success, error for failure. + * + * Object has to be reserved and unreserved outside! + */ +int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t saddr, uint64_t offset, + uint64_t size, uint64_t flags) +{ + struct amdgpu_bo_va_mapping *mapping; + struct amdgpu_vm *vm = bo_va->vm; + uint64_t eaddr; + int r; - if (vm->page_tables[pt_idx].bo) - continue; + /* validate the parameters */ + if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || + size == 0 || size & AMDGPU_GPU_PAGE_MASK) + return -EINVAL; - r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, - AMDGPU_GPU_PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_VRAM_CLEARED, - NULL, resv, &pt); - if (r) - goto error_free; + /* make sure object fit at this offset */ + eaddr = saddr + size - 1; + if (saddr >= eaddr || + (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) + return -EINVAL; - /* Keep a reference to the page table to avoid freeing - * them up in the wrong order. - */ - pt->parent = amdgpu_bo_ref(vm->page_directory); + /* Allocate all the needed memory */ + mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); + if (!mapping) + return -ENOMEM; - vm->page_tables[pt_idx].bo = pt; - vm->page_tables[pt_idx].addr = 0; + r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); + if (r) { + kfree(mapping); + return r; } - return 0; + saddr /= AMDGPU_GPU_PAGE_SIZE; + eaddr /= AMDGPU_GPU_PAGE_SIZE; -error_free: - list_del(&mapping->list); - interval_tree_remove(&mapping->it, &vm->va); - trace_amdgpu_vm_bo_unmap(bo_va, mapping); - kfree(mapping); + mapping->it.start = saddr; + mapping->it.last = eaddr; + mapping->offset = offset; + mapping->flags = flags; -error: - return r; + list_add(&mapping->list, &bo_va->invalids); + interval_tree_insert(&mapping->it, &vm->va); + + if (flags & AMDGPU_PTE_PRT) + amdgpu_vm_prt_get(adev); + + return 0; } /** @@ -1444,7 +1883,109 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, if (valid) list_add(&mapping->list, &vm->freed); else - kfree(mapping); + amdgpu_vm_free_mapping(adev, vm, mapping, + bo_va->last_pt_update); + + return 0; +} + +/** + * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range + * + * @adev: amdgpu_device pointer + * @vm: VM structure to use + * @saddr: start of the range + * @size: size of the range + * + * Remove all mappings in a range, split them as appropriate. + * Returns 0 for success, error for failure. + */ +int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + uint64_t saddr, uint64_t size) +{ + struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; + struct interval_tree_node *it; + LIST_HEAD(removed); + uint64_t eaddr; + + eaddr = saddr + size - 1; + saddr /= AMDGPU_GPU_PAGE_SIZE; + eaddr /= AMDGPU_GPU_PAGE_SIZE; + + /* Allocate all the needed memory */ + before = kzalloc(sizeof(*before), GFP_KERNEL); + if (!before) + return -ENOMEM; + INIT_LIST_HEAD(&before->list); + + after = kzalloc(sizeof(*after), GFP_KERNEL); + if (!after) { + kfree(before); + return -ENOMEM; + } + INIT_LIST_HEAD(&after->list); + + /* Now gather all removed mappings */ + it = interval_tree_iter_first(&vm->va, saddr, eaddr); + while (it) { + tmp = container_of(it, struct amdgpu_bo_va_mapping, it); + it = interval_tree_iter_next(it, saddr, eaddr); + + /* Remember mapping split at the start */ + if (tmp->it.start < saddr) { + before->it.start = tmp->it.start; + before->it.last = saddr - 1; + before->offset = tmp->offset; + before->flags = tmp->flags; + list_add(&before->list, &tmp->list); + } + + /* Remember mapping split at the end */ + if (tmp->it.last > eaddr) { + after->it.start = eaddr + 1; + after->it.last = tmp->it.last; + after->offset = tmp->offset; + after->offset += after->it.start - tmp->it.start; + after->flags = tmp->flags; + list_add(&after->list, &tmp->list); + } + + list_del(&tmp->list); + list_add(&tmp->list, &removed); + } + + /* And free them up */ + list_for_each_entry_safe(tmp, next, &removed, list) { + interval_tree_remove(&tmp->it, &vm->va); + list_del(&tmp->list); + + if (tmp->it.start < saddr) + tmp->it.start = saddr; + if (tmp->it.last > eaddr) + tmp->it.last = eaddr; + + list_add(&tmp->list, &vm->freed); + trace_amdgpu_vm_bo_unmap(NULL, tmp); + } + + /* Insert partial mapping before the range */ + if (!list_empty(&before->list)) { + interval_tree_insert(&before->it, &vm->va); + if (before->flags & AMDGPU_PTE_PRT) + amdgpu_vm_prt_get(adev); + } else { + kfree(before); + } + + /* Insert partial mapping after the range */ + if (!list_empty(&after->list)) { + interval_tree_insert(&after->it, &vm->va); + if (after->flags & AMDGPU_PTE_PRT) + amdgpu_vm_prt_get(adev); + } else { + kfree(after); + } return 0; } @@ -1480,7 +2021,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { list_del(&mapping->list); interval_tree_remove(&mapping->it, &vm->va); - kfree(mapping); + amdgpu_vm_free_mapping(adev, vm, mapping, + bo_va->last_pt_update); } dma_fence_put(bo_va->last_pt_update); @@ -1521,7 +2063,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) { const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, AMDGPU_VM_PTE_COUNT * 8); - unsigned pd_size, pd_entries; unsigned ring_instance; struct amdgpu_ring *ring; struct amd_sched_rq *rq; @@ -1536,16 +2077,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) INIT_LIST_HEAD(&vm->cleared); INIT_LIST_HEAD(&vm->freed); - pd_size = amdgpu_vm_directory_size(adev); - pd_entries = amdgpu_vm_num_pdes(adev); - - /* allocate page table array */ - vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); - if (vm->page_tables == NULL) { - DRM_ERROR("Cannot allocate memory for page table array\n"); - return -ENOMEM; - } - /* create scheduler entity for page table updates */ ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); @@ -1555,44 +2086,64 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) r = amd_sched_entity_init(&ring->sched, &vm->entity, rq, amdgpu_sched_jobs); if (r) - goto err; + return r; - vm->page_directory_fence = NULL; + vm->last_dir_update = NULL; - r = amdgpu_bo_create(adev, pd_size, align, true, + r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_SHADOW | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED, - NULL, NULL, &vm->page_directory); + NULL, NULL, &vm->root.bo); if (r) goto error_free_sched_entity; - r = amdgpu_bo_reserve(vm->page_directory, false); + r = amdgpu_bo_reserve(vm->root.bo, false); if (r) - goto error_free_page_directory; + goto error_free_root; vm->last_eviction_counter = atomic64_read(&adev->num_evictions); - amdgpu_bo_unreserve(vm->page_directory); + amdgpu_bo_unreserve(vm->root.bo); return 0; -error_free_page_directory: - amdgpu_bo_unref(&vm->page_directory->shadow); - amdgpu_bo_unref(&vm->page_directory); - vm->page_directory = NULL; +error_free_root: + amdgpu_bo_unref(&vm->root.bo->shadow); + amdgpu_bo_unref(&vm->root.bo); + vm->root.bo = NULL; error_free_sched_entity: amd_sched_entity_fini(&ring->sched, &vm->entity); -err: - drm_free_large(vm->page_tables); - return r; } /** + * amdgpu_vm_free_levels - free PD/PT levels + * + * @level: PD/PT starting level to free + * + * Free the page directory or page table level and all sub levels. + */ +static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) +{ + unsigned i; + + if (level->bo) { + amdgpu_bo_unref(&level->bo->shadow); + amdgpu_bo_unref(&level->bo); + } + + if (level->entries) + for (i = 0; i <= level->last_entry_used; i++) + amdgpu_vm_free_levels(&level->entries[i]); + + drm_free_large(level->entries); +} + +/** * amdgpu_vm_fini - tear down a vm instance * * @adev: amdgpu_device pointer @@ -1604,7 +2155,7 @@ err: void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdgpu_bo_va_mapping *mapping, *tmp; - int i; + bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; amd_sched_entity_fini(vm->entity.sched, &vm->entity); @@ -1617,24 +2168,17 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) kfree(mapping); } list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { - list_del(&mapping->list); - kfree(mapping); - } - - for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { - struct amdgpu_bo *pt = vm->page_tables[i].bo; - - if (!pt) - continue; + if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { + amdgpu_vm_prt_fini(adev, vm); + prt_fini_needed = false; + } - amdgpu_bo_unref(&pt->shadow); - amdgpu_bo_unref(&pt); + list_del(&mapping->list); + amdgpu_vm_free_mapping(adev, vm, mapping, NULL); } - drm_free_large(vm->page_tables); - amdgpu_bo_unref(&vm->page_directory->shadow); - amdgpu_bo_unref(&vm->page_directory); - dma_fence_put(vm->page_directory_fence); + amdgpu_vm_free_levels(&vm->root); + dma_fence_put(vm->last_dir_update); } /** @@ -1665,6 +2209,8 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); atomic64_set(&adev->vm_manager.client_counter, 0); + spin_lock_init(&adev->vm_manager.prt_lock); + atomic_set(&adev->vm_manager.num_prt_users, 0); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 18c72c0b478d..fbe17bf73a00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -53,17 +53,23 @@ struct amdgpu_bo_list_entry; /* LOG2 number of continuous pages for the fragment field */ #define AMDGPU_LOG2_PAGES_PER_FRAG 4 -#define AMDGPU_PTE_VALID (1 << 0) -#define AMDGPU_PTE_SYSTEM (1 << 1) -#define AMDGPU_PTE_SNOOPED (1 << 2) +#define AMDGPU_PTE_VALID (1ULL << 0) +#define AMDGPU_PTE_SYSTEM (1ULL << 1) +#define AMDGPU_PTE_SNOOPED (1ULL << 2) /* VI only */ -#define AMDGPU_PTE_EXECUTABLE (1 << 4) +#define AMDGPU_PTE_EXECUTABLE (1ULL << 4) -#define AMDGPU_PTE_READABLE (1 << 5) -#define AMDGPU_PTE_WRITEABLE (1 << 6) +#define AMDGPU_PTE_READABLE (1ULL << 5) +#define AMDGPU_PTE_WRITEABLE (1ULL << 6) -#define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7) +#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) + +#define AMDGPU_PTE_PRT (1ULL << 63) + +/* VEGA10 only */ +#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) +#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) /* How to programm VM fault handling */ #define AMDGPU_VM_FAULT_STOP_NEVER 0 @@ -73,6 +79,10 @@ struct amdgpu_bo_list_entry; struct amdgpu_vm_pt { struct amdgpu_bo *bo; uint64_t addr; + + /* array of page tables, one for each directory entry */ + struct amdgpu_vm_pt *entries; + unsigned last_entry_used; }; struct amdgpu_vm { @@ -92,14 +102,10 @@ struct amdgpu_vm { struct list_head freed; /* contains the page directory */ - struct amdgpu_bo *page_directory; - unsigned max_pde_used; - struct dma_fence *page_directory_fence; + struct amdgpu_vm_pt root; + struct dma_fence *last_dir_update; uint64_t last_eviction_counter; - /* array of page tables, one for each page directory entry */ - struct amdgpu_vm_pt *page_tables; - /* for id and flush management per ring */ struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; @@ -147,7 +153,8 @@ struct amdgpu_vm_manager { u64 fence_context; unsigned seqno[AMDGPU_MAX_RINGS]; - uint32_t max_pfn; + uint64_t max_pfn; + uint32_t num_level; /* vram base address for page table entry */ u64 vram_base_offset; /* is vm enabled? */ @@ -159,6 +166,10 @@ struct amdgpu_vm_manager { atomic_t vm_pte_next_ring; /* client id counter */ atomic64_t client_counter; + + /* partial resident texture handling */ + spinlock_t prt_lock; + atomic_t num_prt_users; }; void amdgpu_vm_manager_init(struct amdgpu_device *adev); @@ -173,15 +184,19 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, void *param); void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, struct amdgpu_vm *vm); +int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + uint64_t saddr, uint64_t size); int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync, struct dma_fence *fence, struct amdgpu_job *job); int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); -int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, - struct amdgpu_vm *vm); +int amdgpu_vm_update_directories(struct amdgpu_device *adev, + struct amdgpu_vm *vm); int amdgpu_vm_clear_freed(struct amdgpu_device *adev, - struct amdgpu_vm *vm); + struct amdgpu_vm *vm, + struct dma_fence **fence); int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_sync *sync); int amdgpu_vm_bo_update(struct amdgpu_device *adev, @@ -198,9 +213,16 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t addr, uint64_t offset, uint64_t size, uint64_t flags); +int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t addr, uint64_t offset, + uint64_t size, uint64_t flags); int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t addr); +int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + uint64_t saddr, uint64_t size); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 1b50e6c13fb3..d69aa2e179bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -166,7 +166,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, case ATOM_IIO_END: return temp; default: - printk(KERN_INFO "Unknown IIO opcode.\n"); + pr_info("Unknown IIO opcode\n"); return 0; } } @@ -190,22 +190,19 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, val = gctx->card->reg_read(gctx->card, idx); break; case ATOM_IO_PCI: - printk(KERN_INFO - "PCI registers are not implemented.\n"); + pr_info("PCI registers are not implemented\n"); return 0; case ATOM_IO_SYSIO: - printk(KERN_INFO - "SYSIO registers are not implemented.\n"); + pr_info("SYSIO registers are not implemented\n"); return 0; default: if (!(gctx->io_mode & 0x80)) { - printk(KERN_INFO "Bad IO mode.\n"); + pr_info("Bad IO mode\n"); return 0; } if (!gctx->iio[gctx->io_mode & 0x7F]) { - printk(KERN_INFO - "Undefined indirect IO read method %d.\n", - gctx->io_mode & 0x7F); + pr_info("Undefined indirect IO read method %d\n", + gctx->io_mode & 0x7F); return 0; } val = @@ -469,22 +466,19 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, gctx->card->reg_write(gctx->card, idx, val); break; case ATOM_IO_PCI: - printk(KERN_INFO - "PCI registers are not implemented.\n"); + pr_info("PCI registers are not implemented\n"); return; case ATOM_IO_SYSIO: - printk(KERN_INFO - "SYSIO registers are not implemented.\n"); + pr_info("SYSIO registers are not implemented\n"); return; default: if (!(gctx->io_mode & 0x80)) { - printk(KERN_INFO "Bad IO mode.\n"); + pr_info("Bad IO mode\n"); return; } if (!gctx->iio[gctx->io_mode & 0xFF]) { - printk(KERN_INFO - "Undefined indirect IO write method %d.\n", - gctx->io_mode & 0x7F); + pr_info("Undefined indirect IO write method %d\n", + gctx->io_mode & 0x7F); return; } atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], @@ -850,17 +844,17 @@ static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) { - printk(KERN_INFO "unimplemented!\n"); + pr_info("unimplemented!\n"); } static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) { - printk(KERN_INFO "unimplemented!\n"); + pr_info("unimplemented!\n"); } static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) { - printk(KERN_INFO "unimplemented!\n"); + pr_info("unimplemented!\n"); } static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) @@ -1023,7 +1017,7 @@ static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) } (*ptr) += 2; } else { - printk(KERN_INFO "Bad case.\n"); + pr_info("Bad case\n"); return; } (*ptr) += 2; @@ -1306,8 +1300,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) struct atom_context *ctx = kzalloc(sizeof(struct atom_context), GFP_KERNEL); char *str; - char name[512]; - int i; + u16 idx; if (!ctx) return NULL; @@ -1316,14 +1309,14 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) ctx->bios = bios; if (CU16(0) != ATOM_BIOS_MAGIC) { - printk(KERN_INFO "Invalid BIOS magic.\n"); + pr_info("Invalid BIOS magic\n"); kfree(ctx); return NULL; } if (strncmp (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, strlen(ATOM_ATI_MAGIC))) { - printk(KERN_INFO "Invalid ATI magic.\n"); + pr_info("Invalid ATI magic\n"); kfree(ctx); return NULL; } @@ -1332,7 +1325,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) if (strncmp (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, strlen(ATOM_ROM_MAGIC))) { - printk(KERN_INFO "Invalid ATOM magic.\n"); + pr_info("Invalid ATOM magic\n"); kfree(ctx); return NULL; } @@ -1345,18 +1338,13 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) return NULL; } - str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); - while (*str && ((*str == '\n') || (*str == '\r'))) - str++; - /* name string isn't always 0 terminated */ - for (i = 0; i < 511; i++) { - name[i] = str[i]; - if (name[i] < '.' || name[i] > 'z') { - name[i] = 0; - break; - } - } - printk(KERN_INFO "ATOM BIOS: %s\n", name); + idx = CU16(ATOM_ROM_PART_NUMBER_PTR); + if (idx == 0) + idx = 0x80; + + str = CSTR(idx); + if (*str != '\0') + pr_info("ATOM BIOS: %s\n", str); return ctx; } @@ -1429,29 +1417,3 @@ bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * return true; } -int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx) -{ - int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); - uint16_t data_offset; - int usage_bytes = 0; - struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; - - if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { - firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); - - DRM_DEBUG("atom firmware requested %08x %dkb\n", - le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), - le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); - - usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; - } - ctx->scratch_size_bytes = 0; - if (usage_bytes == 0) - usage_bytes = 20 * 1024; - /* allocate some scratch memory */ - ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); - if (!ctx->scratch) - return -ENOMEM; - ctx->scratch_size_bytes = usage_bytes; - return 0; -} diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index 49daf6d723e5..ddd8045accf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -32,6 +32,7 @@ #define ATOM_ATI_MAGIC_PTR 0x30 #define ATOM_ATI_MAGIC " 761295520" #define ATOM_ROM_TABLE_PTR 0x48 +#define ATOM_ROM_PART_NUMBER_PTR 0x6E #define ATOM_ROM_MAGIC "ATOM" #define ATOM_ROM_MAGIC_PTR 4 @@ -151,7 +152,6 @@ bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, uint16_t uint8_t *frev, uint8_t *crev, uint16_t *data_start); bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, uint8_t *crev); -int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx); #include "atom-types.h" #include "atombios.h" #include "ObjectID.h" diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index f97ecb49972e..11ccda83d767 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -3681,6 +3681,40 @@ static int ci_find_boot_level(struct ci_single_dpm_table *table, return ret; } +static void ci_save_default_power_profile(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct SMU7_Discrete_GraphicsLevel *levels = + pi->smc_state_table.GraphicsLevel; + uint32_t min_level = 0; + + pi->default_gfx_power_profile.activity_threshold = + be16_to_cpu(levels[0].ActivityLevel); + pi->default_gfx_power_profile.up_hyst = levels[0].UpH; + pi->default_gfx_power_profile.down_hyst = levels[0].DownH; + pi->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; + + pi->default_compute_power_profile = pi->default_gfx_power_profile; + pi->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; + + /* Optimize compute power profile: Use only highest + * 2 power levels (if more than 2 are available), Hysteresis: + * 0ms up, 5ms down + */ + if (pi->smc_state_table.GraphicsDpmLevelCount > 2) + min_level = pi->smc_state_table.GraphicsDpmLevelCount - 2; + else if (pi->smc_state_table.GraphicsDpmLevelCount == 2) + min_level = 1; + pi->default_compute_power_profile.min_sclk = + be32_to_cpu(levels[min_level].SclkFrequency); + + pi->default_compute_power_profile.up_hyst = 0; + pi->default_compute_power_profile.down_hyst = 5; + + pi->gfx_power_profile = pi->default_gfx_power_profile; + pi->compute_power_profile = pi->default_compute_power_profile; +} + static int ci_init_smc_table(struct amdgpu_device *adev) { struct ci_power_info *pi = ci_get_pi(adev); @@ -3826,6 +3860,8 @@ static int ci_init_smc_table(struct amdgpu_device *adev) if (ret) return ret; + ci_save_default_power_profile(adev); + return 0; } @@ -5804,9 +5840,7 @@ static int ci_dpm_init_microcode(struct amdgpu_device *adev) out: if (err) { - printk(KERN_ERR - "cik_smc: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name); release_firmware(adev->pm.fw); adev->pm.fw = NULL; } @@ -6250,11 +6284,13 @@ static int ci_dpm_sw_init(void *handle) int ret; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); + ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, + &adev->pm.dpm.thermal.irq); if (ret) return ret; - ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); + ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, + &adev->pm.dpm.thermal.irq); if (ret) return ret; @@ -6688,6 +6724,260 @@ static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) return 0; } +static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev, + struct amd_pp_profile *query) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!pi || !query) + return -EINVAL; + + if (query->type == AMD_PP_GFX_PROFILE) + memcpy(query, &pi->gfx_power_profile, + sizeof(struct amd_pp_profile)); + else if (query->type == AMD_PP_COMPUTE_PROFILE) + memcpy(query, &pi->compute_power_profile, + sizeof(struct amd_pp_profile)); + else + return -EINVAL; + + return 0; +} + +static int ci_populate_requested_graphic_levels(struct amdgpu_device *adev, + struct amd_pp_profile *request) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_dpm_table *dpm_table = &(pi->dpm_table); + struct SMU7_Discrete_GraphicsLevel *levels = + pi->smc_state_table.GraphicsLevel; + uint32_t array = pi->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); + uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) * + SMU7_MAX_LEVELS_GRAPHICS; + uint32_t i; + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + levels[i].ActivityLevel = + cpu_to_be16(request->activity_threshold); + levels[i].EnabledForActivity = 1; + levels[i].UpH = request->up_hyst; + levels[i].DownH = request->down_hyst; + } + + return amdgpu_ci_copy_bytes_to_smc(adev, array, (uint8_t *)levels, + array_size, pi->sram_end); +} + +static void ci_find_min_clock_masks(struct amdgpu_device *adev, + uint32_t *sclk_mask, uint32_t *mclk_mask, + uint32_t min_sclk, uint32_t min_mclk) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_dpm_table *dpm_table = &(pi->dpm_table); + uint32_t i; + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + if (dpm_table->sclk_table.dpm_levels[i].enabled && + dpm_table->sclk_table.dpm_levels[i].value >= min_sclk) + *sclk_mask |= 1 << i; + } + + for (i = 0; i < dpm_table->mclk_table.count; i++) { + if (dpm_table->mclk_table.dpm_levels[i].enabled && + dpm_table->mclk_table.dpm_levels[i].value >= min_mclk) + *mclk_mask |= 1 << i; + } +} + +static int ci_set_power_profile_state(struct amdgpu_device *adev, + struct amd_pp_profile *request) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int tmp_result, result = 0; + uint32_t sclk_mask = 0, mclk_mask = 0; + + tmp_result = ci_freeze_sclk_mclk_dpm(adev); + if (tmp_result) { + DRM_ERROR("Failed to freeze SCLK MCLK DPM!"); + result = tmp_result; + } + + tmp_result = ci_populate_requested_graphic_levels(adev, + request); + if (tmp_result) { + DRM_ERROR("Failed to populate requested graphic levels!"); + result = tmp_result; + } + + tmp_result = ci_unfreeze_sclk_mclk_dpm(adev); + if (tmp_result) { + DRM_ERROR("Failed to unfreeze SCLK MCLK DPM!"); + result = tmp_result; + } + + ci_find_min_clock_masks(adev, &sclk_mask, &mclk_mask, + request->min_sclk, request->min_mclk); + + if (sclk_mask) { + if (!pi->sclk_dpm_key_disabled) + amdgpu_ci_send_msg_to_smc_with_parameter( + adev, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + pi->dpm_level_enable_mask. + sclk_dpm_enable_mask & + sclk_mask); + } + + if (mclk_mask) { + if (!pi->mclk_dpm_key_disabled) + amdgpu_ci_send_msg_to_smc_with_parameter( + adev, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + pi->dpm_level_enable_mask. + mclk_dpm_enable_mask & + mclk_mask); + } + + + return result; +} + +static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev, + struct amd_pp_profile *request) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret = -1; + + if (!pi || !request) + return -EINVAL; + + if (adev->pm.dpm.forced_level != + AMD_DPM_FORCED_LEVEL_AUTO) + return -EINVAL; + + if (request->min_sclk || + request->min_mclk || + request->activity_threshold || + request->up_hyst || + request->down_hyst) { + if (request->type == AMD_PP_GFX_PROFILE) + memcpy(&pi->gfx_power_profile, request, + sizeof(struct amd_pp_profile)); + else if (request->type == AMD_PP_COMPUTE_PROFILE) + memcpy(&pi->compute_power_profile, request, + sizeof(struct amd_pp_profile)); + else + return -EINVAL; + + if (request->type == pi->current_power_profile) + ret = ci_set_power_profile_state( + adev, + request); + } else { + /* set power profile if it exists */ + switch (request->type) { + case AMD_PP_GFX_PROFILE: + ret = ci_set_power_profile_state( + adev, + &pi->gfx_power_profile); + break; + case AMD_PP_COMPUTE_PROFILE: + ret = ci_set_power_profile_state( + adev, + &pi->compute_power_profile); + break; + default: + return -EINVAL; + } + } + + if (!ret) + pi->current_power_profile = request->type; + + return 0; +} + +static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev, + struct amd_pp_profile *request) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!pi || !request) + return -EINVAL; + + if (request->type == AMD_PP_GFX_PROFILE) { + pi->gfx_power_profile = pi->default_gfx_power_profile; + return ci_dpm_set_power_profile_state(adev, + &pi->gfx_power_profile); + } else if (request->type == AMD_PP_COMPUTE_PROFILE) { + pi->compute_power_profile = + pi->default_compute_power_profile; + return ci_dpm_set_power_profile_state(adev, + &pi->compute_power_profile); + } else + return -EINVAL; +} + +static int ci_dpm_switch_power_profile(struct amdgpu_device *adev, + enum amd_pp_profile_type type) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amd_pp_profile request = {0}; + + if (!pi) + return -EINVAL; + + if (pi->current_power_profile != type) { + request.type = type; + return ci_dpm_set_power_profile_state(adev, &request); + } + + return 0; +} + +static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx, + void *value, int *size) +{ + u32 activity_percent = 50; + int ret; + + /* size must be at least 4 bytes for all sensors */ + if (*size < 4) + return -EINVAL; + + switch (idx) { + case AMDGPU_PP_SENSOR_GFX_SCLK: + *((uint32_t *)value) = ci_get_average_sclk_freq(adev); + *size = 4; + return 0; + case AMDGPU_PP_SENSOR_GFX_MCLK: + *((uint32_t *)value) = ci_get_average_mclk_freq(adev); + *size = 4; + return 0; + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = ci_dpm_get_temp(adev); + *size = 4; + return 0; + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = ci_read_smc_soft_register(adev, + offsetof(SMU7_SoftRegisters, + AverageGraphicsA), + &activity_percent); + if (ret == 0) { + activity_percent += 0x80; + activity_percent >>= 8; + activity_percent = + activity_percent > 100 ? 100 : activity_percent; + } + *((uint32_t *)value) = activity_percent; + *size = 4; + return 0; + default: + return -EINVAL; + } +} + const struct amd_ip_funcs ci_dpm_ip_funcs = { .name = "ci_dpm", .early_init = ci_dpm_early_init, @@ -6730,6 +7020,11 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = { .set_mclk_od = ci_dpm_set_mclk_od, .check_state_equal = ci_check_state_equal, .get_vce_clock_state = amdgpu_get_vce_clock_state, + .get_power_profile_state = ci_dpm_get_power_profile_state, + .set_power_profile_state = ci_dpm_set_power_profile_state, + .reset_power_profile_state = ci_dpm_reset_power_profile_state, + .switch_power_profile = ci_dpm_switch_power_profile, + .read_sensor = ci_dpm_read_sensor, }; static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.h b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h index 91be2996ae7c..84cbc9c45f4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h @@ -295,6 +295,13 @@ struct ci_power_info { bool fan_is_controlled_by_smc; u32 t_min; u32 fan_ctrl_default_mode; + + /* power profile */ + struct amd_pp_profile gfx_power_profile; + struct amd_pp_profile compute_power_profile; + struct amd_pp_profile default_gfx_power_profile; + struct amd_pp_profile default_compute_power_profile; + enum amd_pp_profile_type current_power_profile; }; #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index c4d4b35e54ec..9d33e5641419 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1212,6 +1212,11 @@ static int cik_asic_reset(struct amdgpu_device *adev) return r; } +static u32 cik_get_config_memsize(struct amdgpu_device *adev) +{ + return RREG32(mmCONFIG_MEMSIZE); +} + static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, u32 cntl_reg, u32 status_reg) { @@ -1641,6 +1646,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .get_xclk = &cik_get_xclk, .set_uvd_clocks = &cik_set_uvd_clocks, .set_vce_clocks = &cik_set_vce_clocks, + .get_config_memsize = &cik_get_config_memsize, }; static int cik_common_early_init(void *handle) @@ -1779,6 +1785,8 @@ static int cik_common_early_init(void *handle) return -EINVAL; } + adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); + amdgpu_get_pcie_info(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 319b32cdea84..c57c3f18af01 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -248,8 +248,9 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev, dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; entry->src_id = dw[0] & 0xff; - entry->src_data = dw[1] & 0xfffffff; + entry->src_data[0] = dw[1] & 0xfffffff; entry->ring_id = dw[2] & 0xff; entry->vm_id = (dw[2] >> 8) & 0xff; entry->pas_id = (dw[2] >> 16) & 0xffff; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 810bba533975..c216e16826c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -142,9 +142,7 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev) } out: if (err) { - printk(KERN_ERR - "cik_sdma: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); for (i = 0; i < adev->sdma.num_instances; i++) { release_firmware(adev->sdma.instance[i].fw); adev->sdma.instance[i].fw = NULL; @@ -160,7 +158,7 @@ out: * * Get the current rptr from the hardware (CIK+). */ -static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) { u32 rptr; @@ -176,7 +174,7 @@ static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) * * Get the current wptr from the hardware (CIK+). */ -static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; @@ -196,7 +194,8 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], + (lower_32_bits(ring->wptr) << 2) & 0x3fffc); } static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) @@ -227,7 +226,7 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, u32 extra_bits = vm_id & 0xf; /* IB packet must end on a 8 DW boundary */ - cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); + cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ @@ -434,7 +433,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); ring->wptr = 0; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); /* enable DMA RB */ WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], @@ -750,14 +749,14 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, */ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, - uint32_t incr, uint32_t flags) + uint32_t incr, uint64_t flags) { /* for physically contiguous pages (vram) */ ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ @@ -924,17 +923,20 @@ static int cik_sdma_sw_init(void *handle) } /* SDMA trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, + &adev->sdma.trap_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, + &adev->sdma.illegal_inst_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, + &adev->sdma.illegal_inst_irq); if (r) return r; @@ -1211,6 +1213,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, .align_mask = 0xf, .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), + .support_64bit_ptrs = false, .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, .set_wptr = cik_sdma_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h index 6cbd913fd12e..6a9e38a3d2a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/cikd.h +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -502,7 +502,7 @@ # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 #define SDMA_OPCODE_WRITE 2 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 -# define SDMA_WRTIE_SUB_OPCODE_TILED 1 +# define SDMA_WRITE_SUB_OPCODE_TILED 1 #define SDMA_OPCODE_INDIRECT_BUFFER 4 #define SDMA_OPCODE_FENCE 5 #define SDMA_OPCODE_TRAP 6 diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h new file mode 100644 index 000000000000..18fd01f3e4b2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h @@ -0,0 +1,941 @@ + +/* +*************************************************************************************************** +* +* Trade secret of Advanced Micro Devices, Inc. +* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished) +* +* All rights reserved. This notice is intended as a precaution against inadvertent publication and +* does not imply publication or any waiver of confidentiality. The year included in the foregoing +* notice is the year of creation of the work. +* +*************************************************************************************************** +*/ +/** +*************************************************************************************************** +* @brief gfx9 Clearstate Definitions +*************************************************************************************************** +* +* Do not edit! This is a machine-generated file! +* +*/ + +static const unsigned int gfx9_SECT_CONTEXT_def_1[] = +{ + 0x00000000, // DB_RENDER_CONTROL + 0x00000000, // DB_COUNT_CONTROL + 0x00000000, // DB_DEPTH_VIEW + 0x00000000, // DB_RENDER_OVERRIDE + 0x00000000, // DB_RENDER_OVERRIDE2 + 0x00000000, // DB_HTILE_DATA_BASE + 0x00000000, // DB_HTILE_DATA_BASE_HI + 0x00000000, // DB_DEPTH_SIZE + 0x00000000, // DB_DEPTH_BOUNDS_MIN + 0x00000000, // DB_DEPTH_BOUNDS_MAX + 0x00000000, // DB_STENCIL_CLEAR + 0x00000000, // DB_DEPTH_CLEAR + 0x00000000, // PA_SC_SCREEN_SCISSOR_TL + 0x40004000, // PA_SC_SCREEN_SCISSOR_BR + 0x00000000, // DB_Z_INFO + 0x00000000, // DB_STENCIL_INFO + 0x00000000, // DB_Z_READ_BASE + 0x00000000, // DB_Z_READ_BASE_HI + 0x00000000, // DB_STENCIL_READ_BASE + 0x00000000, // DB_STENCIL_READ_BASE_HI + 0x00000000, // DB_Z_WRITE_BASE + 0x00000000, // DB_Z_WRITE_BASE_HI + 0x00000000, // DB_STENCIL_WRITE_BASE + 0x00000000, // DB_STENCIL_WRITE_BASE_HI + 0x00000000, // DB_DFSM_CONTROL + 0x00000000, // DB_RENDER_FILTER + 0x00000000, // DB_Z_INFO2 + 0x00000000, // DB_STENCIL_INFO2 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // TA_BC_BASE_ADDR + 0x00000000, // TA_BC_BASE_ADDR_HI + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // COHER_DEST_BASE_HI_0 + 0x00000000, // COHER_DEST_BASE_HI_1 + 0x00000000, // COHER_DEST_BASE_HI_2 + 0x00000000, // COHER_DEST_BASE_HI_3 + 0x00000000, // COHER_DEST_BASE_2 + 0x00000000, // COHER_DEST_BASE_3 + 0x00000000, // PA_SC_WINDOW_OFFSET + 0x80000000, // PA_SC_WINDOW_SCISSOR_TL + 0x40004000, // PA_SC_WINDOW_SCISSOR_BR + 0x0000ffff, // PA_SC_CLIPRECT_RULE + 0x00000000, // PA_SC_CLIPRECT_0_TL + 0x40004000, // PA_SC_CLIPRECT_0_BR + 0x00000000, // PA_SC_CLIPRECT_1_TL + 0x40004000, // PA_SC_CLIPRECT_1_BR + 0x00000000, // PA_SC_CLIPRECT_2_TL + 0x40004000, // PA_SC_CLIPRECT_2_BR + 0x00000000, // PA_SC_CLIPRECT_3_TL + 0x40004000, // PA_SC_CLIPRECT_3_BR + 0xaa99aaaa, // PA_SC_EDGERULE + 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET + 0xffffffff, // CB_TARGET_MASK + 0xffffffff, // CB_SHADER_MASK + 0x80000000, // PA_SC_GENERIC_SCISSOR_TL + 0x40004000, // PA_SC_GENERIC_SCISSOR_BR + 0x00000000, // COHER_DEST_BASE_0 + 0x00000000, // COHER_DEST_BASE_1 + 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR + 0x00000000, // PA_SC_VPORT_ZMIN_0 + 0x3f800000, // PA_SC_VPORT_ZMAX_0 + 0x00000000, // PA_SC_VPORT_ZMIN_1 + 0x3f800000, // PA_SC_VPORT_ZMAX_1 + 0x00000000, // PA_SC_VPORT_ZMIN_2 + 0x3f800000, // PA_SC_VPORT_ZMAX_2 + 0x00000000, // PA_SC_VPORT_ZMIN_3 + 0x3f800000, // PA_SC_VPORT_ZMAX_3 + 0x00000000, // PA_SC_VPORT_ZMIN_4 + 0x3f800000, // PA_SC_VPORT_ZMAX_4 + 0x00000000, // PA_SC_VPORT_ZMIN_5 + 0x3f800000, // PA_SC_VPORT_ZMAX_5 + 0x00000000, // PA_SC_VPORT_ZMIN_6 + 0x3f800000, // PA_SC_VPORT_ZMAX_6 + 0x00000000, // PA_SC_VPORT_ZMIN_7 + 0x3f800000, // PA_SC_VPORT_ZMAX_7 + 0x00000000, // PA_SC_VPORT_ZMIN_8 + 0x3f800000, // PA_SC_VPORT_ZMAX_8 + 0x00000000, // PA_SC_VPORT_ZMIN_9 + 0x3f800000, // PA_SC_VPORT_ZMAX_9 + 0x00000000, // PA_SC_VPORT_ZMIN_10 + 0x3f800000, // PA_SC_VPORT_ZMAX_10 + 0x00000000, // PA_SC_VPORT_ZMIN_11 + 0x3f800000, // PA_SC_VPORT_ZMAX_11 + 0x00000000, // PA_SC_VPORT_ZMIN_12 + 0x3f800000, // PA_SC_VPORT_ZMAX_12 + 0x00000000, // PA_SC_VPORT_ZMIN_13 + 0x3f800000, // PA_SC_VPORT_ZMAX_13 + 0x00000000, // PA_SC_VPORT_ZMIN_14 + 0x3f800000, // PA_SC_VPORT_ZMAX_14 + 0x00000000, // PA_SC_VPORT_ZMIN_15 + 0x3f800000, // PA_SC_VPORT_ZMAX_15 +}; +static const unsigned int gfx9_SECT_CONTEXT_def_2[] = +{ + 0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL + 0x00000000, // PA_SC_TILE_STEERING_OVERRIDE + 0x00000000, // CP_PERFMON_CNTX_CNTL + 0x00000000, // CP_RINGID + 0x00000000, // CP_VMID + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // PA_SC_RIGHT_VERT_GRID + 0x00000000, // PA_SC_LEFT_VERT_GRID + 0x00000000, // PA_SC_HORIZ_GRID + 0x00000000, // PA_SC_FOV_WINDOW_LR + 0x00000000, // PA_SC_FOV_WINDOW_TB + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX + 0, // HOLE + 0x00000000, // CB_BLEND_RED + 0x00000000, // CB_BLEND_GREEN + 0x00000000, // CB_BLEND_BLUE + 0x00000000, // CB_BLEND_ALPHA + 0x00000000, // CB_DCC_CONTROL + 0, // HOLE + 0x00000000, // DB_STENCIL_CONTROL + 0x01000000, // DB_STENCILREFMASK + 0x01000000, // DB_STENCILREFMASK_BF + 0, // HOLE + 0x00000000, // PA_CL_VPORT_XSCALE + 0x00000000, // PA_CL_VPORT_XOFFSET + 0x00000000, // PA_CL_VPORT_YSCALE + 0x00000000, // PA_CL_VPORT_YOFFSET + 0x00000000, // PA_CL_VPORT_ZSCALE + 0x00000000, // PA_CL_VPORT_ZOFFSET + 0x00000000, // PA_CL_VPORT_XSCALE_1 + 0x00000000, // PA_CL_VPORT_XOFFSET_1 + 0x00000000, // PA_CL_VPORT_YSCALE_1 + 0x00000000, // PA_CL_VPORT_YOFFSET_1 + 0x00000000, // PA_CL_VPORT_ZSCALE_1 + 0x00000000, // PA_CL_VPORT_ZOFFSET_1 + 0x00000000, // PA_CL_VPORT_XSCALE_2 + 0x00000000, // PA_CL_VPORT_XOFFSET_2 + 0x00000000, // PA_CL_VPORT_YSCALE_2 + 0x00000000, // PA_CL_VPORT_YOFFSET_2 + 0x00000000, // PA_CL_VPORT_ZSCALE_2 + 0x00000000, // PA_CL_VPORT_ZOFFSET_2 + 0x00000000, // PA_CL_VPORT_XSCALE_3 + 0x00000000, // PA_CL_VPORT_XOFFSET_3 + 0x00000000, // PA_CL_VPORT_YSCALE_3 + 0x00000000, // PA_CL_VPORT_YOFFSET_3 + 0x00000000, // PA_CL_VPORT_ZSCALE_3 + 0x00000000, // PA_CL_VPORT_ZOFFSET_3 + 0x00000000, // PA_CL_VPORT_XSCALE_4 + 0x00000000, // PA_CL_VPORT_XOFFSET_4 + 0x00000000, // PA_CL_VPORT_YSCALE_4 + 0x00000000, // PA_CL_VPORT_YOFFSET_4 + 0x00000000, // PA_CL_VPORT_ZSCALE_4 + 0x00000000, // PA_CL_VPORT_ZOFFSET_4 + 0x00000000, // PA_CL_VPORT_XSCALE_5 + 0x00000000, // PA_CL_VPORT_XOFFSET_5 + 0x00000000, // PA_CL_VPORT_YSCALE_5 + 0x00000000, // PA_CL_VPORT_YOFFSET_5 + 0x00000000, // PA_CL_VPORT_ZSCALE_5 + 0x00000000, // PA_CL_VPORT_ZOFFSET_5 + 0x00000000, // PA_CL_VPORT_XSCALE_6 + 0x00000000, // PA_CL_VPORT_XOFFSET_6 + 0x00000000, // PA_CL_VPORT_YSCALE_6 + 0x00000000, // PA_CL_VPORT_YOFFSET_6 + 0x00000000, // PA_CL_VPORT_ZSCALE_6 + 0x00000000, // PA_CL_VPORT_ZOFFSET_6 + 0x00000000, // PA_CL_VPORT_XSCALE_7 + 0x00000000, // PA_CL_VPORT_XOFFSET_7 + 0x00000000, // PA_CL_VPORT_YSCALE_7 + 0x00000000, // PA_CL_VPORT_YOFFSET_7 + 0x00000000, // PA_CL_VPORT_ZSCALE_7 + 0x00000000, // PA_CL_VPORT_ZOFFSET_7 + 0x00000000, // PA_CL_VPORT_XSCALE_8 + 0x00000000, // PA_CL_VPORT_XOFFSET_8 + 0x00000000, // PA_CL_VPORT_YSCALE_8 + 0x00000000, // PA_CL_VPORT_YOFFSET_8 + 0x00000000, // PA_CL_VPORT_ZSCALE_8 + 0x00000000, // PA_CL_VPORT_ZOFFSET_8 + 0x00000000, // PA_CL_VPORT_XSCALE_9 + 0x00000000, // PA_CL_VPORT_XOFFSET_9 + 0x00000000, // PA_CL_VPORT_YSCALE_9 + 0x00000000, // PA_CL_VPORT_YOFFSET_9 + 0x00000000, // PA_CL_VPORT_ZSCALE_9 + 0x00000000, // PA_CL_VPORT_ZOFFSET_9 + 0x00000000, // PA_CL_VPORT_XSCALE_10 + 0x00000000, // PA_CL_VPORT_XOFFSET_10 + 0x00000000, // PA_CL_VPORT_YSCALE_10 + 0x00000000, // PA_CL_VPORT_YOFFSET_10 + 0x00000000, // PA_CL_VPORT_ZSCALE_10 + 0x00000000, // PA_CL_VPORT_ZOFFSET_10 + 0x00000000, // PA_CL_VPORT_XSCALE_11 + 0x00000000, // PA_CL_VPORT_XOFFSET_11 + 0x00000000, // PA_CL_VPORT_YSCALE_11 + 0x00000000, // PA_CL_VPORT_YOFFSET_11 + 0x00000000, // PA_CL_VPORT_ZSCALE_11 + 0x00000000, // PA_CL_VPORT_ZOFFSET_11 + 0x00000000, // PA_CL_VPORT_XSCALE_12 + 0x00000000, // PA_CL_VPORT_XOFFSET_12 + 0x00000000, // PA_CL_VPORT_YSCALE_12 + 0x00000000, // PA_CL_VPORT_YOFFSET_12 + 0x00000000, // PA_CL_VPORT_ZSCALE_12 + 0x00000000, // PA_CL_VPORT_ZOFFSET_12 + 0x00000000, // PA_CL_VPORT_XSCALE_13 + 0x00000000, // PA_CL_VPORT_XOFFSET_13 + 0x00000000, // PA_CL_VPORT_YSCALE_13 + 0x00000000, // PA_CL_VPORT_YOFFSET_13 + 0x00000000, // PA_CL_VPORT_ZSCALE_13 + 0x00000000, // PA_CL_VPORT_ZOFFSET_13 + 0x00000000, // PA_CL_VPORT_XSCALE_14 + 0x00000000, // PA_CL_VPORT_XOFFSET_14 + 0x00000000, // PA_CL_VPORT_YSCALE_14 + 0x00000000, // PA_CL_VPORT_YOFFSET_14 + 0x00000000, // PA_CL_VPORT_ZSCALE_14 + 0x00000000, // PA_CL_VPORT_ZOFFSET_14 + 0x00000000, // PA_CL_VPORT_XSCALE_15 + 0x00000000, // PA_CL_VPORT_XOFFSET_15 + 0x00000000, // PA_CL_VPORT_YSCALE_15 + 0x00000000, // PA_CL_VPORT_YOFFSET_15 + 0x00000000, // PA_CL_VPORT_ZSCALE_15 + 0x00000000, // PA_CL_VPORT_ZOFFSET_15 + 0x00000000, // PA_CL_UCP_0_X + 0x00000000, // PA_CL_UCP_0_Y + 0x00000000, // PA_CL_UCP_0_Z + 0x00000000, // PA_CL_UCP_0_W + 0x00000000, // PA_CL_UCP_1_X + 0x00000000, // PA_CL_UCP_1_Y + 0x00000000, // PA_CL_UCP_1_Z + 0x00000000, // PA_CL_UCP_1_W + 0x00000000, // PA_CL_UCP_2_X + 0x00000000, // PA_CL_UCP_2_Y + 0x00000000, // PA_CL_UCP_2_Z + 0x00000000, // PA_CL_UCP_2_W + 0x00000000, // PA_CL_UCP_3_X + 0x00000000, // PA_CL_UCP_3_Y + 0x00000000, // PA_CL_UCP_3_Z + 0x00000000, // PA_CL_UCP_3_W + 0x00000000, // PA_CL_UCP_4_X + 0x00000000, // PA_CL_UCP_4_Y + 0x00000000, // PA_CL_UCP_4_Z + 0x00000000, // PA_CL_UCP_4_W + 0x00000000, // PA_CL_UCP_5_X + 0x00000000, // PA_CL_UCP_5_Y + 0x00000000, // PA_CL_UCP_5_Z + 0x00000000, // PA_CL_UCP_5_W + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SPI_PS_INPUT_CNTL_0 + 0x00000000, // SPI_PS_INPUT_CNTL_1 + 0x00000000, // SPI_PS_INPUT_CNTL_2 + 0x00000000, // SPI_PS_INPUT_CNTL_3 + 0x00000000, // SPI_PS_INPUT_CNTL_4 + 0x00000000, // SPI_PS_INPUT_CNTL_5 + 0x00000000, // SPI_PS_INPUT_CNTL_6 + 0x00000000, // SPI_PS_INPUT_CNTL_7 + 0x00000000, // SPI_PS_INPUT_CNTL_8 + 0x00000000, // SPI_PS_INPUT_CNTL_9 + 0x00000000, // SPI_PS_INPUT_CNTL_10 + 0x00000000, // SPI_PS_INPUT_CNTL_11 + 0x00000000, // SPI_PS_INPUT_CNTL_12 + 0x00000000, // SPI_PS_INPUT_CNTL_13 + 0x00000000, // SPI_PS_INPUT_CNTL_14 + 0x00000000, // SPI_PS_INPUT_CNTL_15 + 0x00000000, // SPI_PS_INPUT_CNTL_16 + 0x00000000, // SPI_PS_INPUT_CNTL_17 + 0x00000000, // SPI_PS_INPUT_CNTL_18 + 0x00000000, // SPI_PS_INPUT_CNTL_19 + 0x00000000, // SPI_PS_INPUT_CNTL_20 + 0x00000000, // SPI_PS_INPUT_CNTL_21 + 0x00000000, // SPI_PS_INPUT_CNTL_22 + 0x00000000, // SPI_PS_INPUT_CNTL_23 + 0x00000000, // SPI_PS_INPUT_CNTL_24 + 0x00000000, // SPI_PS_INPUT_CNTL_25 + 0x00000000, // SPI_PS_INPUT_CNTL_26 + 0x00000000, // SPI_PS_INPUT_CNTL_27 + 0x00000000, // SPI_PS_INPUT_CNTL_28 + 0x00000000, // SPI_PS_INPUT_CNTL_29 + 0x00000000, // SPI_PS_INPUT_CNTL_30 + 0x00000000, // SPI_PS_INPUT_CNTL_31 + 0x00000000, // SPI_VS_OUT_CONFIG + 0, // HOLE + 0x00000000, // SPI_PS_INPUT_ENA + 0x00000000, // SPI_PS_INPUT_ADDR + 0x00000000, // SPI_INTERP_CONTROL_0 + 0x00000002, // SPI_PS_IN_CONTROL + 0, // HOLE + 0x00000000, // SPI_BARYC_CNTL + 0, // HOLE + 0x00000000, // SPI_TMPRING_SIZE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SPI_SHADER_POS_FORMAT + 0x00000000, // SPI_SHADER_Z_FORMAT + 0x00000000, // SPI_SHADER_COL_FORMAT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SX_PS_DOWNCONVERT + 0x00000000, // SX_BLEND_OPT_EPSILON + 0x00000000, // SX_BLEND_OPT_CONTROL + 0x00000000, // SX_MRT0_BLEND_OPT + 0x00000000, // SX_MRT1_BLEND_OPT + 0x00000000, // SX_MRT2_BLEND_OPT + 0x00000000, // SX_MRT3_BLEND_OPT + 0x00000000, // SX_MRT4_BLEND_OPT + 0x00000000, // SX_MRT5_BLEND_OPT + 0x00000000, // SX_MRT6_BLEND_OPT + 0x00000000, // SX_MRT7_BLEND_OPT + 0x00000000, // CB_BLEND0_CONTROL + 0x00000000, // CB_BLEND1_CONTROL + 0x00000000, // CB_BLEND2_CONTROL + 0x00000000, // CB_BLEND3_CONTROL + 0x00000000, // CB_BLEND4_CONTROL + 0x00000000, // CB_BLEND5_CONTROL + 0x00000000, // CB_BLEND6_CONTROL + 0x00000000, // CB_BLEND7_CONTROL + 0x00000000, // CB_MRT0_EPITCH + 0x00000000, // CB_MRT1_EPITCH + 0x00000000, // CB_MRT2_EPITCH + 0x00000000, // CB_MRT3_EPITCH + 0x00000000, // CB_MRT4_EPITCH + 0x00000000, // CB_MRT5_EPITCH + 0x00000000, // CB_MRT6_EPITCH + 0x00000000, // CB_MRT7_EPITCH +}; +static const unsigned int gfx9_SECT_CONTEXT_def_3[] = +{ + 0x00000000, // PA_CL_POINT_X_RAD + 0x00000000, // PA_CL_POINT_Y_RAD + 0x00000000, // PA_CL_POINT_SIZE + 0x00000000, // PA_CL_POINT_CULL_RAD +}; +static const unsigned int gfx9_SECT_CONTEXT_def_4[] = +{ + 0x00000000, // DB_DEPTH_CONTROL + 0x00000000, // DB_EQAA + 0x00000000, // CB_COLOR_CONTROL + 0x00000000, // DB_SHADER_CONTROL + 0x00090000, // PA_CL_CLIP_CNTL + 0x00000004, // PA_SU_SC_MODE_CNTL + 0x00000000, // PA_CL_VTE_CNTL + 0x00000000, // PA_CL_VS_OUT_CNTL + 0x00000000, // PA_CL_NANINF_CNTL + 0x00000000, // PA_SU_LINE_STIPPLE_CNTL + 0x00000000, // PA_SU_LINE_STIPPLE_SCALE + 0x00000000, // PA_SU_PRIM_FILTER_CNTL + 0x00000000, // PA_SU_SMALL_PRIM_FILTER_CNTL + 0x00000000, // PA_CL_OBJPRIM_ID_CNTL + 0x00000000, // PA_CL_NGG_CNTL + 0x00000000, // PA_SU_OVER_RASTERIZATION_CNTL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // PA_SU_POINT_SIZE + 0x00000000, // PA_SU_POINT_MINMAX + 0x00000000, // PA_SU_LINE_CNTL + 0x00000000, // PA_SC_LINE_STIPPLE + 0x00000000, // VGT_OUTPUT_PATH_CNTL + 0x00000000, // VGT_HOS_CNTL + 0x00000000, // VGT_HOS_MAX_TESS_LEVEL + 0x00000000, // VGT_HOS_MIN_TESS_LEVEL + 0x00000000, // VGT_HOS_REUSE_DEPTH + 0x00000000, // VGT_GROUP_PRIM_TYPE + 0x00000000, // VGT_GROUP_FIRST_DECR + 0x00000000, // VGT_GROUP_DECR + 0x00000000, // VGT_GROUP_VECT_0_CNTL + 0x00000000, // VGT_GROUP_VECT_1_CNTL + 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL + 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL + 0x00000000, // VGT_GS_MODE + 0x00000000, // VGT_GS_ONCHIP_CNTL + 0x00000000, // PA_SC_MODE_CNTL_0 + 0x00000000, // PA_SC_MODE_CNTL_1 + 0x00000000, // VGT_ENHANCE + 0x00000100, // VGT_GS_PER_ES + 0x00000080, // VGT_ES_PER_GS + 0x00000002, // VGT_GS_PER_VS + 0x00000000, // VGT_GSVS_RING_OFFSET_1 + 0x00000000, // VGT_GSVS_RING_OFFSET_2 + 0x00000000, // VGT_GSVS_RING_OFFSET_3 + 0x00000000, // VGT_GS_OUT_PRIM_TYPE + 0x00000000, // IA_ENHANCE +}; +static const unsigned int gfx9_SECT_CONTEXT_def_5[] = +{ + 0x00000000, // WD_ENHANCE + 0x00000000, // VGT_PRIMITIVEID_EN +}; +static const unsigned int gfx9_SECT_CONTEXT_def_6[] = +{ + 0x00000000, // VGT_PRIMITIVEID_RESET +}; +static const unsigned int gfx9_SECT_CONTEXT_def_7[] = +{ + 0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP + 0x00000000, // VGT_DRAW_PAYLOAD_CNTL + 0x00000000, // VGT_INDEX_PAYLOAD_CNTL + 0x00000000, // VGT_INSTANCE_STEP_RATE_0 + 0x00000000, // VGT_INSTANCE_STEP_RATE_1 + 0, // HOLE + 0x00000000, // VGT_ESGS_RING_ITEMSIZE + 0x00000000, // VGT_GSVS_RING_ITEMSIZE + 0x00000000, // VGT_REUSE_OFF + 0x00000000, // VGT_VTX_CNT_EN + 0x00000000, // DB_HTILE_SURFACE + 0x00000000, // DB_SRESULTS_COMPARE_STATE0 + 0x00000000, // DB_SRESULTS_COMPARE_STATE1 + 0x00000000, // DB_PRELOAD_CONTROL + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE + 0, // HOLE + 0x00000000, // VGT_GS_MAX_VERT_OUT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_TESS_DISTRIBUTION + 0x00000000, // VGT_SHADER_STAGES_EN + 0x00000000, // VGT_LS_HS_CONFIG + 0x00000000, // VGT_GS_VERT_ITEMSIZE + 0x00000000, // VGT_GS_VERT_ITEMSIZE_1 + 0x00000000, // VGT_GS_VERT_ITEMSIZE_2 + 0x00000000, // VGT_GS_VERT_ITEMSIZE_3 + 0x00000000, // VGT_TF_PARAM + 0x00000000, // DB_ALPHA_TO_MASK + 0x00000000, // VGT_DISPATCH_DRAW_INDEX + 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL + 0x00000000, // PA_SU_POLY_OFFSET_CLAMP + 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE + 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET + 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE + 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET + 0x00000000, // VGT_GS_INSTANCE_CNT + 0x00000000, // VGT_STRMOUT_CONFIG + 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG +}; +static const unsigned int gfx9_SECT_CONTEXT_def_8[] = +{ + 0x00000000, // PA_SC_CENTROID_PRIORITY_0 + 0x00000000, // PA_SC_CENTROID_PRIORITY_1 + 0x00001000, // PA_SC_LINE_CNTL + 0x00000000, // PA_SC_AA_CONFIG + 0x00000005, // PA_SU_VTX_CNTL + 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ + 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ + 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ + 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 + 0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0 + 0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1 + 0x00000000, // PA_SC_SHADER_CONTROL + 0x00000003, // PA_SC_BINNER_CNTL_0 + 0x00000000, // PA_SC_BINNER_CNTL_1 + 0x00000000, // PA_SC_CONSERVATIVE_RASTERIZATION_CNTL + 0x00000000, // PA_SC_NGG_MODE_CNTL + 0, // HOLE + 0x0000001e, // VGT_VERTEX_REUSE_BLOCK_CNTL + 0x00000020, // VGT_OUT_DEALLOC_CNTL + 0x00000000, // CB_COLOR0_BASE + 0x00000000, // CB_COLOR0_BASE_EXT + 0x00000000, // CB_COLOR0_ATTRIB2 + 0x00000000, // CB_COLOR0_VIEW + 0x00000000, // CB_COLOR0_INFO + 0x00000000, // CB_COLOR0_ATTRIB + 0x00000000, // CB_COLOR0_DCC_CONTROL + 0x00000000, // CB_COLOR0_CMASK + 0x00000000, // CB_COLOR0_CMASK_BASE_EXT + 0x00000000, // CB_COLOR0_FMASK + 0x00000000, // CB_COLOR0_FMASK_BASE_EXT + 0x00000000, // CB_COLOR0_CLEAR_WORD0 + 0x00000000, // CB_COLOR0_CLEAR_WORD1 + 0x00000000, // CB_COLOR0_DCC_BASE + 0x00000000, // CB_COLOR0_DCC_BASE_EXT + 0x00000000, // CB_COLOR1_BASE + 0x00000000, // CB_COLOR1_BASE_EXT + 0x00000000, // CB_COLOR1_ATTRIB2 + 0x00000000, // CB_COLOR1_VIEW + 0x00000000, // CB_COLOR1_INFO + 0x00000000, // CB_COLOR1_ATTRIB + 0x00000000, // CB_COLOR1_DCC_CONTROL + 0x00000000, // CB_COLOR1_CMASK + 0x00000000, // CB_COLOR1_CMASK_BASE_EXT + 0x00000000, // CB_COLOR1_FMASK + 0x00000000, // CB_COLOR1_FMASK_BASE_EXT + 0x00000000, // CB_COLOR1_CLEAR_WORD0 + 0x00000000, // CB_COLOR1_CLEAR_WORD1 + 0x00000000, // CB_COLOR1_DCC_BASE + 0x00000000, // CB_COLOR1_DCC_BASE_EXT + 0x00000000, // CB_COLOR2_BASE + 0x00000000, // CB_COLOR2_BASE_EXT + 0x00000000, // CB_COLOR2_ATTRIB2 + 0x00000000, // CB_COLOR2_VIEW + 0x00000000, // CB_COLOR2_INFO + 0x00000000, // CB_COLOR2_ATTRIB + 0x00000000, // CB_COLOR2_DCC_CONTROL + 0x00000000, // CB_COLOR2_CMASK + 0x00000000, // CB_COLOR2_CMASK_BASE_EXT + 0x00000000, // CB_COLOR2_FMASK + 0x00000000, // CB_COLOR2_FMASK_BASE_EXT + 0x00000000, // CB_COLOR2_CLEAR_WORD0 + 0x00000000, // CB_COLOR2_CLEAR_WORD1 + 0x00000000, // CB_COLOR2_DCC_BASE + 0x00000000, // CB_COLOR2_DCC_BASE_EXT + 0x00000000, // CB_COLOR3_BASE + 0x00000000, // CB_COLOR3_BASE_EXT + 0x00000000, // CB_COLOR3_ATTRIB2 + 0x00000000, // CB_COLOR3_VIEW + 0x00000000, // CB_COLOR3_INFO + 0x00000000, // CB_COLOR3_ATTRIB + 0x00000000, // CB_COLOR3_DCC_CONTROL + 0x00000000, // CB_COLOR3_CMASK + 0x00000000, // CB_COLOR3_CMASK_BASE_EXT + 0x00000000, // CB_COLOR3_FMASK + 0x00000000, // CB_COLOR3_FMASK_BASE_EXT + 0x00000000, // CB_COLOR3_CLEAR_WORD0 + 0x00000000, // CB_COLOR3_CLEAR_WORD1 + 0x00000000, // CB_COLOR3_DCC_BASE + 0x00000000, // CB_COLOR3_DCC_BASE_EXT + 0x00000000, // CB_COLOR4_BASE + 0x00000000, // CB_COLOR4_BASE_EXT + 0x00000000, // CB_COLOR4_ATTRIB2 + 0x00000000, // CB_COLOR4_VIEW + 0x00000000, // CB_COLOR4_INFO + 0x00000000, // CB_COLOR4_ATTRIB + 0x00000000, // CB_COLOR4_DCC_CONTROL + 0x00000000, // CB_COLOR4_CMASK + 0x00000000, // CB_COLOR4_CMASK_BASE_EXT + 0x00000000, // CB_COLOR4_FMASK + 0x00000000, // CB_COLOR4_FMASK_BASE_EXT + 0x00000000, // CB_COLOR4_CLEAR_WORD0 + 0x00000000, // CB_COLOR4_CLEAR_WORD1 + 0x00000000, // CB_COLOR4_DCC_BASE + 0x00000000, // CB_COLOR4_DCC_BASE_EXT + 0x00000000, // CB_COLOR5_BASE + 0x00000000, // CB_COLOR5_BASE_EXT + 0x00000000, // CB_COLOR5_ATTRIB2 + 0x00000000, // CB_COLOR5_VIEW + 0x00000000, // CB_COLOR5_INFO + 0x00000000, // CB_COLOR5_ATTRIB + 0x00000000, // CB_COLOR5_DCC_CONTROL + 0x00000000, // CB_COLOR5_CMASK + 0x00000000, // CB_COLOR5_CMASK_BASE_EXT + 0x00000000, // CB_COLOR5_FMASK + 0x00000000, // CB_COLOR5_FMASK_BASE_EXT + 0x00000000, // CB_COLOR5_CLEAR_WORD0 + 0x00000000, // CB_COLOR5_CLEAR_WORD1 + 0x00000000, // CB_COLOR5_DCC_BASE + 0x00000000, // CB_COLOR5_DCC_BASE_EXT + 0x00000000, // CB_COLOR6_BASE + 0x00000000, // CB_COLOR6_BASE_EXT + 0x00000000, // CB_COLOR6_ATTRIB2 + 0x00000000, // CB_COLOR6_VIEW + 0x00000000, // CB_COLOR6_INFO + 0x00000000, // CB_COLOR6_ATTRIB + 0x00000000, // CB_COLOR6_DCC_CONTROL + 0x00000000, // CB_COLOR6_CMASK + 0x00000000, // CB_COLOR6_CMASK_BASE_EXT + 0x00000000, // CB_COLOR6_FMASK + 0x00000000, // CB_COLOR6_FMASK_BASE_EXT + 0x00000000, // CB_COLOR6_CLEAR_WORD0 + 0x00000000, // CB_COLOR6_CLEAR_WORD1 + 0x00000000, // CB_COLOR6_DCC_BASE + 0x00000000, // CB_COLOR6_DCC_BASE_EXT + 0x00000000, // CB_COLOR7_BASE + 0x00000000, // CB_COLOR7_BASE_EXT + 0x00000000, // CB_COLOR7_ATTRIB2 + 0x00000000, // CB_COLOR7_VIEW + 0x00000000, // CB_COLOR7_INFO + 0x00000000, // CB_COLOR7_ATTRIB + 0x00000000, // CB_COLOR7_DCC_CONTROL + 0x00000000, // CB_COLOR7_CMASK + 0x00000000, // CB_COLOR7_CMASK_BASE_EXT + 0x00000000, // CB_COLOR7_FMASK + 0x00000000, // CB_COLOR7_FMASK_BASE_EXT + 0x00000000, // CB_COLOR7_CLEAR_WORD0 + 0x00000000, // CB_COLOR7_CLEAR_WORD1 + 0x00000000, // CB_COLOR7_DCC_BASE + 0x00000000, // CB_COLOR7_DCC_BASE_EXT +}; +static const struct cs_extent_def gfx9_SECT_CONTEXT_defs[] = +{ + {gfx9_SECT_CONTEXT_def_1, 0x0000a000, 212 }, + {gfx9_SECT_CONTEXT_def_2, 0x0000a0d6, 282 }, + {gfx9_SECT_CONTEXT_def_3, 0x0000a1f5, 4 }, + {gfx9_SECT_CONTEXT_def_4, 0x0000a200, 157 }, + {gfx9_SECT_CONTEXT_def_5, 0x0000a2a0, 2 }, + {gfx9_SECT_CONTEXT_def_6, 0x0000a2a3, 1 }, + {gfx9_SECT_CONTEXT_def_7, 0x0000a2a5, 66 }, + {gfx9_SECT_CONTEXT_def_8, 0x0000a2f5, 155 }, + { 0, 0, 0 } +}; +static const struct cs_section_def gfx9_cs_data[] = { + { gfx9_SECT_CONTEXT_defs, SECT_CONTEXT }, + { 0, SECT_NONE } +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index fe7cbb24da7b..a5f294ebff5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -227,8 +227,9 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev, dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; entry->src_id = dw[0] & 0xff; - entry->src_data = dw[1] & 0xfffffff; + entry->src_data[0] = dw[1] & 0xfffffff; entry->ring_id = dw[2] & 0xff; entry->vm_id = (dw[2] >> 8) & 0xff; entry->pas_id = (dw[2] >> 16) & 0xffff; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index d4452d8f76ca..f525ae4e0576 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2947,19 +2947,19 @@ static int dce_v10_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); if (r) return r; } for (i = 8; i < 20; i += 2) { - r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); if (r) return r; } /* HPD hotplug */ - r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); if (r) return r; @@ -3398,7 +3398,7 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); - switch (entry->src_data) { + switch (entry->src_data[0]) { case 0: /* vblank */ if (disp_int & interrupt_status_offsets[crtc].vblank) dce_v10_0_crtc_vblank_int_ack(adev, crtc); @@ -3421,7 +3421,7 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); break; } @@ -3435,12 +3435,12 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, uint32_t disp_int, mask; unsigned hpd; - if (entry->src_data >= adev->mode_info.num_hpd) { - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + if (entry->src_data[0] >= adev->mode_info.num_hpd) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); return 0; } - hpd = entry->src_data; + hpd = entry->src_data[0]; disp_int = RREG32(interrupt_status_offsets[hpd].reg); mask = interrupt_status_offsets[hpd].hpd; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 5b24e89552ec..3eac27f24d94 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3007,19 +3007,19 @@ static int dce_v11_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); if (r) return r; } for (i = 8; i < 20; i += 2) { - r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); if (r) return r; } /* HPD hotplug */ - r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); if (r) return r; @@ -3462,7 +3462,7 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); - switch (entry->src_data) { + switch (entry->src_data[0]) { case 0: /* vblank */ if (disp_int & interrupt_status_offsets[crtc].vblank) dce_v11_0_crtc_vblank_int_ack(adev, crtc); @@ -3485,7 +3485,7 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); break; } @@ -3499,12 +3499,12 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, uint32_t disp_int, mask; unsigned hpd; - if (entry->src_data >= adev->mode_info.num_hpd) { - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + if (entry->src_data[0] >= adev->mode_info.num_hpd) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); return 0; } - hpd = entry->src_data; + hpd = entry->src_data[0]; disp_int = RREG32(interrupt_status_offsets[hpd].reg); mask = interrupt_status_offsets[hpd].hpd; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 809aa94a0cc1..838cf1a778f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2295,19 +2295,19 @@ static int dce_v6_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); if (r) return r; } for (i = 8; i < 20; i += 2) { - r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); if (r) return r; } /* HPD hotplug */ - r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); if (r) return r; @@ -2592,7 +2592,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); - switch (entry->src_data) { + switch (entry->src_data[0]) { case 0: /* vblank */ if (disp_int & interrupt_status_offsets[crtc].vblank) WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); @@ -2613,7 +2613,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: D%d vline\n", crtc + 1); break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); break; } @@ -2703,12 +2703,12 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, uint32_t disp_int, mask, tmp; unsigned hpd; - if (entry->src_data >= adev->mode_info.num_hpd) { - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + if (entry->src_data[0] >= adev->mode_info.num_hpd) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); return 0; } - hpd = entry->src_data; + hpd = entry->src_data[0]; disp_int = RREG32(interrupt_status_offsets[hpd].reg); mask = interrupt_status_offsets[hpd].hpd; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index d2590d75aa11..1b0717b11efe 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2794,19 +2794,19 @@ static int dce_v8_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); if (r) return r; } for (i = 8; i < 20; i += 2) { - r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); if (r) return r; } /* HPD hotplug */ - r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); if (r) return r; @@ -3159,7 +3159,7 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); - switch (entry->src_data) { + switch (entry->src_data[0]) { case 0: /* vblank */ if (disp_int & interrupt_status_offsets[crtc].vblank) WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); @@ -3180,7 +3180,7 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, DRM_DEBUG("IH: D%d vline\n", crtc + 1); break; default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); break; } @@ -3270,12 +3270,12 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, uint32_t disp_int, mask, tmp; unsigned hpd; - if (entry->src_data >= adev->mode_info.num_hpd) { - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + if (entry->src_data[0] >= adev->mode_info.num_hpd) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); return 0; } - hpd = entry->src_data; + hpd = entry->src_data[0]; disp_int = RREG32(interrupt_status_offsets[hpd].reg); mask = interrupt_status_offsets[hpd].hpd; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index e9a176891e13..5c51f9a97811 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -122,8 +122,9 @@ static void dce_virtual_stop_mc_access(struct amdgpu_device *adev, break; case CHIP_CARRIZO: case CHIP_STONEY: - case CHIP_POLARIS11: case CHIP_POLARIS10: + case CHIP_POLARIS11: + case CHIP_POLARIS12: dce_v11_0_disable_dce(adev); break; case CHIP_TOPAZ: @@ -203,6 +204,9 @@ static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); unsigned type; + if (amdgpu_sriov_vf(adev)) + return; + switch (mode) { case DRM_MODE_DPMS_ON: amdgpu_crtc->enabled = true; @@ -463,7 +467,7 @@ static int dce_virtual_sw_init(void *handle) int r, i; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - r = amdgpu_irq_add_id(adev, 229, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 2086e7e68de4..4c4874fdf59f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -378,9 +378,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - printk(KERN_ERR - "gfx6: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -1579,6 +1577,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) mutex_unlock(&adev->grbm_idx_mutex); } +static void gfx_v6_0_config_init(struct amdgpu_device *adev) +{ + adev->gfx.config.double_offchip_lds_buf = 1; +} + static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) { u32 gb_addr_config = 0; @@ -1736,6 +1739,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) gfx_v6_0_setup_spi(adev); gfx_v6_0_get_cu_info(adev); + gfx_v6_0_config_init(adev); WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); @@ -2188,12 +2192,12 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) return 0; } -static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) +static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->rptr_offs]; } -static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) +static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -2211,7 +2215,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(mmCP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); (void)RREG32(mmCP_RB0_WPTR); } @@ -2220,10 +2224,10 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->gfx.compute_ring[0]) { - WREG32(mmCP_RB1_WPTR, ring->wptr); + WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); (void)RREG32(mmCP_RB1_WPTR); } else if (ring == &adev->gfx.compute_ring[1]) { - WREG32(mmCP_RB2_WPTR, ring->wptr); + WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); (void)RREG32(mmCP_RB2_WPTR); } else { BUG(); @@ -3238,15 +3242,15 @@ static int gfx_v6_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i, r; - r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); if (r) return r; - r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); if (r) return r; - r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); if (r) return r; @@ -3304,10 +3308,6 @@ static int gfx_v6_0_sw_fini(void *handle) int i; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_bo_unref(&adev->gds.oa_gfx_bo); - amdgpu_bo_unref(&adev->gds.gws_gfx_bo); - amdgpu_bo_unref(&adev->gds.gds_gfx_bo); - for (i = 0; i < adev->gfx.num_gfx_rings; i++) amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); for (i = 0; i < adev->gfx.num_compute_rings; i++) @@ -3627,6 +3627,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .type = AMDGPU_RING_TYPE_GFX, .align_mask = 0xff, .nop = 0x80000000, + .support_64bit_ptrs = false, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_gfx, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 1f9354541f29..8a8bc2fe6f2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -972,9 +972,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - printk(KERN_ERR - "gfx7: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -1876,6 +1874,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); } +static void gfx_v7_0_config_init(struct amdgpu_device *adev) +{ + adev->gfx.config.double_offchip_lds_buf = 1; +} + /** * gfx_v7_0_gpu_init - setup the 3D engine * @@ -1886,7 +1889,8 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) */ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) { - u32 tmp, sh_mem_cfg; + u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; + u32 tmp; int i; WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); @@ -1899,6 +1903,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) gfx_v7_0_setup_rb(adev); gfx_v7_0_get_cu_info(adev); + gfx_v7_0_config_init(adev); /* set HW defaults for 3D engine */ WREG32(mmCP_MEQ_THRESHOLDS, @@ -1916,15 +1921,32 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) /* where to put LDS, scratch, GPUVM in FSA64 space */ sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); + sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, + MTYPE_NC); + sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, + MTYPE_UC); + sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); + + sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, + SWIZZLE_ENABLE, 1); + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, + ELEMENT_SIZE, 1); + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, + INDEX_STRIDE, 3); mutex_lock(&adev->srbm_mutex); - for (i = 0; i < 16; i++) { + for (i = 0; i < adev->vm_manager.num_ids; i++) { + if (i == 0) + sh_mem_base = 0; + else + sh_mem_base = adev->mc.shared_aperture_start >> 48; cik_srbm_select(adev, 0, 0, 0, i); /* CP and shaders */ WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); - WREG32(mmSH_MEM_BASES, 0); + WREG32(mmSH_MEM_BASES, sh_mem_base); + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); } cik_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); @@ -2607,7 +2629,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) /* Initialize the ring buffer's read and write pointers */ WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(mmCP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); /* set the wb address wether it's enabled or not */ rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); @@ -2636,12 +2658,12 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) return 0; } -static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) +static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->rptr_offs]; } -static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) +static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -2652,11 +2674,11 @@ static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(mmCP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); (void)RREG32(mmCP_RB0_WPTR); } -static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) +static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) { /* XXX check if swapping is necessary on BE */ return ring->adev->wb.wb[ring->wptr_offs]; @@ -2667,8 +2689,8 @@ static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; /* XXX check if swapping is necessary on BE */ - adev->wb.wb[ring->wptr_offs] = ring->wptr; - WDOORBELL32(ring->doorbell_index, ring->wptr); + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); } /** @@ -3138,7 +3160,7 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ ring->wptr = 0; - mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; + mqd->queue_state.cp_hqd_pq_wptr = lower_32_bits(ring->wptr); WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); @@ -4647,17 +4669,19 @@ static int gfx_v7_0_sw_init(void *handle) int i, r; /* EOP Event */ - r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); if (r) return r; /* Privileged reg */ - r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, + &adev->gfx.priv_reg_irq); if (r) return r; /* Privileged inst */ - r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, + &adev->gfx.priv_inst_irq); if (r) return r; @@ -5184,6 +5208,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .type = AMDGPU_RING_TYPE_GFX, .align_mask = 0xff, .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = false, .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5214,6 +5239,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .type = AMDGPU_RING_TYPE_COMPUTE, .align_mask = 0xff, .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = false, .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_compute, .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 67afc901905c..e0fa0d30e162 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -659,6 +659,8 @@ static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t addr); static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t addr); +static int gfx_v8_0_compute_mqd_sw_init(struct amdgpu_device *adev); +static void gfx_v8_0_compute_mqd_sw_fini(struct amdgpu_device *adev); static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) { @@ -1038,7 +1040,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) } } - if (adev->firmware.smu_load) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; info->fw = adev->gfx.pfp_fw; @@ -1375,13 +1377,12 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_irq_src *irq) { + struct amdgpu_kiq *kiq = &adev->gfx.kiq; int r = 0; - if (amdgpu_sriov_vf(adev)) { - r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); - if (r) - return r; - } + r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); + if (r) + return r; ring->adev = NULL; ring->ring_obj = NULL; @@ -1395,8 +1396,8 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev, ring->pipe = 1; } - irq->data = ring; ring->queue = 0; + ring->eop_gpu_addr = kiq->eop_gpu_addr; sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); @@ -1405,15 +1406,11 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device *adev, return r; } - static void gfx_v8_0_kiq_free_ring(struct amdgpu_ring *ring, struct amdgpu_irq_src *irq) { - if (amdgpu_sriov_vf(ring->adev)) - amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); - + amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); amdgpu_ring_fini(ring); - irq->data = NULL; } #define MEC_HPD_SIZE 2048 @@ -1475,7 +1472,6 @@ static void gfx_v8_0_kiq_fini(struct amdgpu_device *adev) struct amdgpu_kiq *kiq = &adev->gfx.kiq; amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); - kiq->eop_obj = NULL; } static int gfx_v8_0_kiq_init(struct amdgpu_device *adev) @@ -1494,7 +1490,11 @@ static int gfx_v8_0_kiq_init(struct amdgpu_device *adev) memset(hpd, 0, MEC_HPD_SIZE); + r = amdgpu_bo_reserve(kiq->eop_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); amdgpu_bo_kunmap(kiq->eop_obj); + amdgpu_bo_unreserve(kiq->eop_obj); return 0; } @@ -2079,22 +2079,24 @@ static int gfx_v8_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* KIQ event */ - r = amdgpu_irq_add_id(adev, 178, &adev->gfx.kiq.irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq); if (r) return r; /* EOP Event */ - r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); if (r) return r; /* Privileged reg */ - r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, + &adev->gfx.priv_reg_irq); if (r) return r; /* Privileged inst */ - r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, + &adev->gfx.priv_inst_irq); if (r) return r; @@ -2120,17 +2122,6 @@ static int gfx_v8_0_sw_init(void *handle) return r; } - r = gfx_v8_0_kiq_init(adev); - if (r) { - DRM_ERROR("Failed to init KIQ BOs!\n"); - return r; - } - - kiq = &adev->gfx.kiq; - r = gfx_v8_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); - if (r) - return r; - /* set up the gfx ring */ for (i = 0; i < adev->gfx.num_gfx_rings; i++) { ring = &adev->gfx.gfx_ring[i]; @@ -2164,6 +2155,7 @@ static int gfx_v8_0_sw_init(void *handle) ring->me = 1; /* first MEC */ ring->pipe = i / 8; ring->queue = i % 8; + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ @@ -2173,6 +2165,24 @@ static int gfx_v8_0_sw_init(void *handle) return r; } + if (amdgpu_sriov_vf(adev)) { + r = gfx_v8_0_kiq_init(adev); + if (r) { + DRM_ERROR("Failed to init KIQ BOs!\n"); + return r; + } + + kiq = &adev->gfx.kiq; + r = gfx_v8_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); + if (r) + return r; + + /* create MQD for all compute queues as wel as KIQ for SRIOV case */ + r = gfx_v8_0_compute_mqd_sw_init(adev); + if (r) + return r; + } + /* reserve GDS, GWS and OA resource for gfx */ r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, @@ -2214,9 +2224,13 @@ static int gfx_v8_0_sw_fini(void *handle) amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); for (i = 0; i < adev->gfx.num_compute_rings; i++) amdgpu_ring_fini(&adev->gfx.compute_ring[i]); - gfx_v8_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); - gfx_v8_0_kiq_fini(adev); + if (amdgpu_sriov_vf(adev)) { + gfx_v8_0_compute_mqd_sw_fini(adev); + gfx_v8_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); + gfx_v8_0_kiq_fini(adev); + } + gfx_v8_0_mec_fini(adev); gfx_v8_0_rlc_fini(adev); gfx_v8_0_free_microcode(adev); @@ -3839,9 +3853,22 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); } +static void gfx_v8_0_config_init(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + default: + adev->gfx.config.double_offchip_lds_buf = 1; + break; + case CHIP_CARRIZO: + case CHIP_STONEY: + adev->gfx.config.double_offchip_lds_buf = 0; + break; + } +} + static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) { - u32 tmp; + u32 tmp, sh_static_mem_cfg; int i; WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); @@ -3852,11 +3879,18 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) gfx_v8_0_tiling_mode_table_init(adev); gfx_v8_0_setup_rb(adev); gfx_v8_0_get_cu_info(adev); + gfx_v8_0_config_init(adev); /* XXX SH_MEM regs */ /* where to put LDS, scratch, GPUVM in FSA64 space */ + sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, + SWIZZLE_ENABLE, 1); + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, + ELEMENT_SIZE, 1); + sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, + INDEX_STRIDE, 3); mutex_lock(&adev->srbm_mutex); - for (i = 0; i < 16; i++) { + for (i = 0; i < adev->vm_manager.num_ids; i++) { vi_srbm_select(adev, 0, 0, 0, i); /* CP and shaders */ if (i == 0) { @@ -3865,17 +3899,20 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); WREG32(mmSH_MEM_CONFIG, tmp); + WREG32(mmSH_MEM_BASES, 0); } else { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); WREG32(mmSH_MEM_CONFIG, tmp); + tmp = adev->mc.shared_aperture_start >> 48; + WREG32(mmSH_MEM_BASES, tmp); } WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); - WREG32(mmSH_MEM_BASES, 0); + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); } vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); @@ -4069,10 +4106,8 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) data = mmRLC_SRM_INDEX_CNTL_DATA_0; for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) { if (unique_indices[i] != 0) { - amdgpu_mm_wreg(adev, temp + i, - unique_indices[i] & 0x3FFFF, false); - amdgpu_mm_wreg(adev, data + i, - unique_indices[i] >> 20, false); + WREG32(temp + i, unique_indices[i] & 0x3FFFF); + WREG32(data + i, unique_indices[i] >> 20); } } kfree(register_list_format); @@ -4218,7 +4253,7 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) gfx_v8_0_init_pg(adev); if (!adev->pp_enabled) { - if (!adev->firmware.smu_load) { + if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { /* legacy rlc firmware loading */ r = gfx_v8_0_rlc_load_microcode(adev); if (r) @@ -4464,7 +4499,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) /* Initialize the ring buffer's read and write pointers */ WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(mmCP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); /* set the wb address wether it's enabled or not */ rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); @@ -4510,6 +4545,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) } /* start the ring */ + amdgpu_ring_clear_ring(ring); gfx_v8_0_cp_gfx_start(adev); ring->ready = true; r = amdgpu_ring_test_ring(ring); @@ -4596,6 +4632,8 @@ static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) amdgpu_bo_unref(&ring->mqd_obj); ring->mqd_obj = NULL; + ring->mqd_ptr = NULL; + ring->mqd_gpu_addr = 0; } } } @@ -4656,12 +4694,10 @@ static void gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring, udelay(50); } -static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, - struct vi_mqd *mqd, - uint64_t mqd_gpu_addr, - uint64_t eop_gpu_addr, - struct amdgpu_ring *ring) +static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + struct vi_mqd *mqd = ring->mqd_ptr; uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; uint32_t tmp; @@ -4673,7 +4709,7 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, mqd->compute_static_thread_mgmt_se3 = 0xffffffff; mqd->compute_misc_reserved = 0x00000003; - eop_base_addr = eop_gpu_addr >> 8; + eop_base_addr = ring->eop_gpu_addr >> 8; mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); @@ -4702,8 +4738,8 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_pq_wptr = 0; /* set the pointer to the MQD */ - mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; - mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); /* set MQD vmid to 0 */ tmp = RREG32(mmCP_MQD_CONTROL); @@ -4776,10 +4812,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, return 0; } -static int gfx_v8_0_kiq_init_register(struct amdgpu_device *adev, - struct vi_mqd *mqd, - struct amdgpu_ring *ring) +static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring) { + struct amdgpu_device *adev = ring->adev; + struct vi_mqd *mqd = ring->mqd_ptr; uint32_t tmp; int j; @@ -4867,35 +4903,49 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_device *adev, return 0; } -static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring, - struct vi_mqd *mqd, - u64 mqd_gpu_addr) +static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; struct amdgpu_kiq *kiq = &adev->gfx.kiq; - uint64_t eop_gpu_addr; - bool is_kiq = false; - - if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) - is_kiq = true; + struct vi_mqd *mqd = ring->mqd_ptr; + bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); + int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; if (is_kiq) { - eop_gpu_addr = kiq->eop_gpu_addr; gfx_v8_0_kiq_setting(&kiq->ring); - } else - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + - ring->queue * MEC_HPD_SIZE; - - mutex_lock(&adev->srbm_mutex); - vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + } else { + mqd_idx = ring - &adev->gfx.compute_ring[0]; + } - gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring); + if (!adev->gfx.in_reset) { + memset((void *)mqd, 0, sizeof(*mqd)); + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v8_0_mqd_init(ring); + if (is_kiq) + gfx_v8_0_kiq_init_register(ring); + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); - if (is_kiq) - gfx_v8_0_kiq_init_register(adev, mqd, ring); + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); + } else { /* for GPU_RESET case */ + /* reset MQD to a clean status */ + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); + /* reset ring buffer */ + ring->wptr = 0; + amdgpu_ring_clear_ring(ring); + + if (is_kiq) { + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v8_0_kiq_init_register(ring); + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } + } if (is_kiq) gfx_v8_0_kiq_enable(ring); @@ -4905,86 +4955,60 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring, return 0; } -static void gfx_v8_0_kiq_free_queue(struct amdgpu_device *adev) +static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) { struct amdgpu_ring *ring = NULL; - int i; + int r = 0, i; - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); - ring->mqd_obj = NULL; - } + gfx_v8_0_cp_compute_enable(adev, true); ring = &adev->gfx.kiq.ring; - amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); - ring->mqd_obj = NULL; -} -static int gfx_v8_0_kiq_setup_queue(struct amdgpu_device *adev, - struct amdgpu_ring *ring) -{ - struct vi_mqd *mqd; - u64 mqd_gpu_addr; - u32 *buf; - int r = 0; + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + goto done; - r = amdgpu_bo_create_kernel(adev, sizeof(struct vi_mqd), PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, - &mqd_gpu_addr, (void **)&buf); - if (r) { - dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); - return r; + r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); + if (!r) { + r = gfx_v8_0_kiq_init_queue(ring); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; } - - /* init the mqd struct */ - memset(buf, 0, sizeof(struct vi_mqd)); - mqd = (struct vi_mqd *)buf; - - r = gfx_v8_0_kiq_init_queue(ring, mqd, mqd_gpu_addr); - if (r) - return r; - - amdgpu_bo_kunmap(ring->mqd_obj); - - return 0; -} - -static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) -{ - struct amdgpu_ring *ring = NULL; - int r, i; - - ring = &adev->gfx.kiq.ring; - r = gfx_v8_0_kiq_setup_queue(adev, ring); + amdgpu_bo_unreserve(ring->mqd_obj); if (r) - return r; + goto done; - for (i = 0; i < adev->gfx.num_compute_rings; i++) { - ring = &adev->gfx.compute_ring[i]; - r = gfx_v8_0_kiq_setup_queue(adev, ring); - if (r) - return r; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; } - gfx_v8_0_cp_compute_enable(adev, true); - for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + goto done; + r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); + if (!r) { + r = gfx_v8_0_kiq_init_queue(ring); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) + goto done; + ring->ready = true; r = amdgpu_ring_test_ring(ring); if (r) ring->ready = false; } - ring = &adev->gfx.kiq.ring; - ring->ready = true; - r = amdgpu_ring_test_ring(ring); - if (r) - ring->ready = false; - - return 0; +done: + return r; } static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) @@ -5185,7 +5209,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ ring->wptr = 0; - mqd->cp_hqd_pq_wptr = ring->wptr; + mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); @@ -5245,7 +5269,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) gfx_v8_0_enable_gui_idle_interrupt(adev, false); if (!adev->pp_enabled) { - if (!adev->firmware.smu_load) { + if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { /* legacy firmware loading */ r = gfx_v8_0_cp_gfx_load_microcode(adev); if (r) @@ -5329,7 +5353,6 @@ static int gfx_v8_0_hw_fini(void *handle) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); if (amdgpu_sriov_vf(adev)) { - gfx_v8_0_kiq_free_queue(adev); pr_debug("For SRIOV client, shouldn't do anything.\n"); return 0; } @@ -5839,7 +5862,10 @@ static int gfx_v8_0_set_powergating_state(void *handle, enum amd_powergating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - bool enable = (state == AMD_PG_STATE_GATE) ? true : false; + bool enable = (state == AMD_PG_STATE_GATE); + + if (amdgpu_sriov_vf(adev)) + return 0; switch (adev->asic_type) { case CHIP_CARRIZO: @@ -5898,6 +5924,9 @@ static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int data; + if (amdgpu_sriov_vf(adev)) + *flags = 0; + /* AMD_CG_SUPPORT_GFX_MGCG */ data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK)) @@ -6411,18 +6440,22 @@ static int gfx_v8_0_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (amdgpu_sriov_vf(adev)) + return 0; + switch (adev->asic_type) { case CHIP_FIJI: case CHIP_CARRIZO: case CHIP_STONEY: gfx_v8_0_update_gfx_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; case CHIP_TONGA: gfx_v8_0_tonga_update_gfx_clock_gating(adev, state); break; case CHIP_POLARIS10: case CHIP_POLARIS11: + case CHIP_POLARIS12: gfx_v8_0_polaris_update_gfx_clock_gating(adev, state); break; default: @@ -6431,12 +6464,12 @@ static int gfx_v8_0_set_clockgating_state(void *handle, return 0; } -static u32 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring) +static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->rptr_offs]; } -static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) +static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -6453,10 +6486,10 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) if (ring->use_doorbell) { /* XXX check if swapping is necessary on BE */ - adev->wb.wb[ring->wptr_offs] = ring->wptr; - WDOORBELL32(ring->doorbell_index, ring->wptr); + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); } else { - WREG32(mmCP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); (void)RREG32(mmCP_RB0_WPTR); } } @@ -6531,6 +6564,9 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, control |= ib->length_dw | (vm_id << 24); + if (amdgpu_sriov_vf(ring->adev) && ib->flags & AMDGPU_IB_FLAG_PREEMPT) + control |= INDIRECT_BUFFER_PRE_ENB(1); + amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, #ifdef __BIG_ENDIAN @@ -6639,12 +6675,10 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, /* sync PFP to ME, otherwise we might get invalid PFP reads */ amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); amdgpu_ring_write(ring, 0x0); - /* GFX8 emits 128 dw nop to prevent CE access VM before vm_flush finish */ - amdgpu_ring_insert_nop(ring, 128); } } -static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) +static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->wptr_offs]; } @@ -6654,8 +6688,8 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; /* XXX check if swapping is necessary on BE */ - adev->wb.wb[ring->wptr_offs] = ring->wptr; - WDOORBELL32(ring->doorbell_index, ring->wptr); + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); } static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, @@ -6748,6 +6782,34 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) (flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr); } +static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) +{ + unsigned ret; + + amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); + amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); + amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ + ret = ring->wptr & ring->buf_mask; + amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ + return ret; +} + +static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) +{ + unsigned cur; + + BUG_ON(offset > ring->buf_mask); + BUG_ON(ring->ring[offset] != 0x55aa55aa); + + cur = (ring->wptr & ring->buf_mask) - 1; + if (likely(cur > offset)) + ring->ring[offset] = cur - offset; + else + ring->ring[offset] = (ring->ring_size >> 2) - offset + cur; +} + + static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) { struct amdgpu_device *adev = ring->adev; @@ -6925,9 +6987,9 @@ static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev, enum amdgpu_interrupt_state state) { uint32_t tmp, target; - struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data; + struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); - BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)); + BUG_ON(ring->funcs->type != AMDGPU_RING_TYPE_KIQ); if (ring->me == 1) target = mmCP_ME1_PIPE0_INT_CNTL; @@ -6971,9 +7033,9 @@ static int gfx_v8_0_kiq_irq(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { u8 me_id, pipe_id, queue_id; - struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data; + struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); - BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)); + BUG_ON(ring->funcs->type != AMDGPU_RING_TYPE_KIQ); me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -7010,18 +7072,28 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .type = AMDGPU_RING_TYPE_GFX, .align_mask = 0xff, .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = false, .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_gfx, .set_wptr = gfx_v8_0_ring_set_wptr_gfx, - .emit_frame_size = - 20 + /* gfx_v8_0_ring_emit_gds_switch */ - 7 + /* gfx_v8_0_ring_emit_hdp_flush */ - 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ - 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */ - 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ - 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ - 2 + /* gfx_v8_ring_emit_sb */ - 3 + 4 + 29, /* gfx_v8_ring_emit_cntxcntl including vgt flush/meta-data */ + .emit_frame_size = /* maximum 215dw if count 16 IBs in */ + 5 + /* COND_EXEC */ + 7 + /* PIPELINE_SYNC */ + 19 + /* VM_FLUSH */ + 8 + /* FENCE for VM_FLUSH */ + 20 + /* GDS switch */ + 4 + /* double SWITCH_BUFFER, + the first COND_EXEC jump to the place just + prior to this double SWITCH_BUFFER */ + 5 + /* COND_EXEC */ + 7 + /* HDP_flush */ + 4 + /* VGT_flush */ + 14 + /* CE_META */ + 31 + /* DE_META */ + 3 + /* CNTX_CTRL */ + 5 + /* HDP_INVL */ + 8 + 8 + /* FENCE x2 */ + 2, /* SWITCH_BUFFER */ .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ .emit_ib = gfx_v8_0_ring_emit_ib_gfx, .emit_fence = gfx_v8_0_ring_emit_fence_gfx, @@ -7036,12 +7108,15 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_switch_buffer = gfx_v8_ring_emit_sb, .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl, + .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec, + .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec, }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .type = AMDGPU_RING_TYPE_COMPUTE, .align_mask = 0xff, .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = false, .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, @@ -7070,6 +7145,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { .type = AMDGPU_RING_TYPE_KIQ, .align_mask = 0xff, .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = false, .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, @@ -7266,15 +7342,15 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c uint64_t ce_payload_addr; int cnt_ce; static union { - struct amdgpu_ce_ib_state regular; - struct amdgpu_ce_ib_state_chained_ib chained; + struct vi_ce_ib_state regular; + struct vi_ce_ib_state_chained_ib chained; } ce_payload = {}; if (ring->adev->virt.chained_ib_support) { - ce_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data_chained_ib, ce_payload); + ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload); cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2; } else { - ce_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data, ce_payload); + ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, ce_payload); cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2; } @@ -7293,20 +7369,20 @@ static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t c uint64_t de_payload_addr, gds_addr; int cnt_de; static union { - struct amdgpu_de_ib_state regular; - struct amdgpu_de_ib_state_chained_ib chained; + struct vi_de_ib_state regular; + struct vi_de_ib_state_chained_ib chained; } de_payload = {}; gds_addr = csa_addr + 4096; if (ring->adev->virt.chained_ib_support) { de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr); de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr); - de_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data_chained_ib, de_payload); + de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload); cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2; } else { de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr); de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr); - de_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data, de_payload); + de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload); cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2; } @@ -7319,3 +7395,68 @@ static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t c amdgpu_ring_write(ring, upper_32_bits(de_payload_addr)); amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2); } + +/* create MQD for each compute queue */ +static int gfx_v8_0_compute_mqd_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = NULL; + int r, i; + + /* create MQD for KIQ */ + ring = &adev->gfx.kiq.ring; + if (!ring->mqd_obj) { + r = amdgpu_bo_create_kernel(adev, sizeof(struct vi_mqd), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, &ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); + return r; + } + + /* prepare MQD backup */ + adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct vi_mqd), GFP_KERNEL); + if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) + dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); + } + + /* create MQD for each KCQ */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + if (!ring->mqd_obj) { + r = amdgpu_bo_create_kernel(adev, sizeof(struct vi_mqd), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, &ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); + return r; + } + + /* prepare MQD backup */ + adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct vi_mqd), GFP_KERNEL); + if (!adev->gfx.mec.mqd_backup[i]) + dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); + } + } + + return 0; +} + +static void gfx_v8_0_compute_mqd_sw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = NULL; + int i; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + kfree(adev->gfx.mec.mqd_backup[i]); + amdgpu_bo_free_kernel(&ring->mqd_obj, + &ring->mqd_gpu_addr, + &ring->mqd_ptr); + } + + ring = &adev->gfx.kiq.ring; + kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); + amdgpu_bo_free_kernel(&ring->mqd_obj, + &ring->mqd_gpu_addr, + &ring->mqd_ptr); +} diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c new file mode 100644 index 000000000000..669bb98fc45d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -0,0 +1,4140 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include <linux/firmware.h> +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_gfx.h" +#include "soc15.h" +#include "soc15d.h" + +#include "vega10/soc15ip.h" +#include "vega10/GC/gc_9_0_offset.h" +#include "vega10/GC/gc_9_0_sh_mask.h" +#include "vega10/vega10_enum.h" +#include "vega10/HDP/hdp_4_0_offset.h" + +#include "soc15_common.h" +#include "clearstate_gfx9.h" +#include "v9_structs.h" + +#define GFX9_NUM_GFX_RINGS 1 +#define GFX9_NUM_COMPUTE_RINGS 8 +#define GFX9_NUM_SE 4 +#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000 + +MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega10_me.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); + +static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = +{ + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)}, + {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), + SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)} +}; + +static const u32 golden_settings_gc_9_0[] = +{ + SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, + SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, + SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, + SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff +}; + +static const u32 golden_settings_gc_9_0_vg10[] = +{ + SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107, + SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, + SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042, + SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, + SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, + SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, + SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800, + SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007 +}; + +#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 + +static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); +static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); +static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); +static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); +static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, + struct amdgpu_cu_info *cu_info); +static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); +static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); + +static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_VEGA10: + amdgpu_program_register_sequence(adev, + golden_settings_gc_9_0, + (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); + amdgpu_program_register_sequence(adev, + golden_settings_gc_9_0_vg10, + (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); + break; + default: + break; + } +} + +static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) +{ + adev->gfx.scratch.num_reg = 7; + adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); + adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; +} + +static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, + bool wc, uint32_t reg, uint32_t val) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | + WRITE_DATA_DST_SEL(0) | + (wc ? WR_CONFIRM : 0)); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, + int mem_space, int opt, uint32_t addr0, + uint32_t addr1, uint32_t ref, uint32_t mask, + uint32_t inv) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, + /* memory (1) or register (0) */ + (WAIT_REG_MEM_MEM_SPACE(mem_space) | + WAIT_REG_MEM_OPERATION(opt) | /* wait */ + WAIT_REG_MEM_FUNCTION(3) | /* equal */ + WAIT_REG_MEM_ENGINE(eng_sel))); + + if (mem_space) + BUG_ON(addr0 & 0x3); /* Dword align */ + amdgpu_ring_write(ring, addr0); + amdgpu_ring_write(ring, addr1); + amdgpu_ring_write(ring, ref); + amdgpu_ring_write(ring, mask); + amdgpu_ring_write(ring, inv); /* poll interval */ +} + +static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = amdgpu_ring_alloc(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", + ring->idx, scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + return r; +} + +static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + struct dma_fence *f = NULL; + uint32_t scratch; + uint32_t tmp = 0; + long r; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + memset(&ib, 0, sizeof(ib)); + r = amdgpu_ib_get(adev, NULL, 256, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + goto err1; + } + ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); + ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); + ib.ptr[2] = 0xDEADBEEF; + ib.length_dw = 3; + + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + if (r) + goto err2; + + r = dma_fence_wait_timeout(f, false, timeout); + if (r == 0) { + DRM_ERROR("amdgpu: IB test timed out.\n"); + r = -ETIMEDOUT; + goto err2; + } else if (r < 0) { + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + goto err2; + } + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) { + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + r = 0; + } else { + DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } +err2: + amdgpu_ib_free(adev, &ib, NULL); + dma_fence_put(f); +err1: + amdgpu_gfx_scratch_free(adev, scratch); + return r; +} + +static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + struct amdgpu_firmware_info *info = NULL; + const struct common_firmware_header *header = NULL; + const struct gfx_firmware_header_v1_0 *cp_hdr; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_VEGA10: + chip_name = "vega10"; + break; + default: + BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); + err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; + adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); + err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.me_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; + adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); + err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.ce_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; + adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); + err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); + err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.mec_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); + + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (!err) { + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw_version = + le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.mec2_feature_version = + le32_to_cpu(cp_hdr->ucode_feature_version); + } else { + err = 0; + adev->gfx.mec2_fw = NULL; + } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; + info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; + info->fw = adev->gfx.pfp_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; + info->ucode_id = AMDGPU_UCODE_ID_CP_ME; + info->fw = adev->gfx.me_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; + info->ucode_id = AMDGPU_UCODE_ID_CP_CE; + info->fw = adev->gfx.ce_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; + info->ucode_id = AMDGPU_UCODE_ID_RLC_G; + info->fw = adev->gfx.rlc_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; + info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; + info->fw = adev->gfx.mec_fw; + header = (const struct common_firmware_header *)info->fw->data; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; + info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; + info->fw = adev->gfx.mec_fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); + + if (adev->gfx.mec2_fw) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; + info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; + info->fw = adev->gfx.mec2_fw; + header = (const struct common_firmware_header *)info->fw->data; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; + info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; + info->fw = adev->gfx.mec2_fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); + } + + } + +out: + if (err) { + dev_err(adev->dev, + "gfx9: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->gfx.pfp_fw); + adev->gfx.pfp_fw = NULL; + release_firmware(adev->gfx.me_fw); + adev->gfx.me_fw = NULL; + release_firmware(adev->gfx.ce_fw); + adev->gfx.ce_fw = NULL; + release_firmware(adev->gfx.rlc_fw); + adev->gfx.rlc_fw = NULL; + release_firmware(adev->gfx.mec_fw); + adev->gfx.mec_fw = NULL; + release_firmware(adev->gfx.mec2_fw); + adev->gfx.mec2_fw = NULL; + } + return err; +} + +static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) +{ + int r; + + if (adev->gfx.mec.hpd_eop_obj) { + r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + + amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); + adev->gfx.mec.hpd_eop_obj = NULL; + } + if (adev->gfx.mec.mec_fw_obj) { + r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj); + amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); + + amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj); + adev->gfx.mec.mec_fw_obj = NULL; + } +} + +#define MEC_HPD_SIZE 2048 + +static int gfx_v9_0_mec_init(struct amdgpu_device *adev) +{ + int r; + u32 *hpd; + const __le32 *fw_data; + unsigned fw_size; + u32 *fw; + + const struct gfx_firmware_header_v1_0 *mec_hdr; + + /* + * we assign only 1 pipe because all other pipes will + * be handled by KFD + */ + adev->gfx.mec.num_mec = 1; + adev->gfx.mec.num_pipe = 1; + adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; + + if (adev->gfx.mec.hpd_eop_obj == NULL) { + r = amdgpu_bo_create(adev, + adev->gfx.mec.num_queue * MEC_HPD_SIZE, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, + &adev->gfx.mec.hpd_eop_obj); + if (r) { + dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); + if (unlikely(r != 0)) { + gfx_v9_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); + gfx_v9_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); + if (r) { + dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); + gfx_v9_0_mec_fini(adev); + return r; + } + + memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); + + amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + + mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + + fw_data = (const __le32 *) + (adev->gfx.mec_fw->data + + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; + + if (adev->gfx.mec.mec_fw_obj == NULL) { + r = amdgpu_bo_create(adev, + mec_hdr->header.ucode_size_bytes, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, + &adev->gfx.mec.mec_fw_obj); + if (r) { + dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false); + if (unlikely(r != 0)) { + gfx_v9_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.mec_fw_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r); + gfx_v9_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw); + if (r) { + dev_warn(adev->dev, "(%d) map firmware bo failed\n", r); + gfx_v9_0_mec_fini(adev); + return r; + } + memcpy(fw, fw_data, fw_size); + + amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); + amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); + + + return 0; +} + +static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + + amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); +} + +static int gfx_v9_0_kiq_init(struct amdgpu_device *adev) +{ + int r; + u32 *hpd; + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + + r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, + &kiq->eop_gpu_addr, (void **)&hpd); + if (r) { + dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); + return r; + } + + memset(hpd, 0, MEC_HPD_SIZE); + + r = amdgpu_bo_reserve(kiq->eop_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); + amdgpu_bo_kunmap(kiq->eop_obj); + amdgpu_bo_unreserve(kiq->eop_obj); + + return 0; +} + +static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + int r = 0; + + r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); + if (r) + return r; + + ring->adev = NULL; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_KIQ; + if (adev->gfx.mec2_fw) { + ring->me = 2; + ring->pipe = 0; + } else { + ring->me = 1; + ring->pipe = 1; + } + + irq->data = ring; + ring->queue = 0; + ring->eop_gpu_addr = kiq->eop_gpu_addr; + sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); + r = amdgpu_ring_init(adev, ring, 1024, + irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); + if (r) + dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); + + return r; +} +static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq) +{ + amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); + amdgpu_ring_fini(ring); + irq->data = NULL; +} + +/* create MQD for each compute queue */ +static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = NULL; + int r, i; + + /* create MQD for KIQ */ + ring = &adev->gfx.kiq.ring; + if (!ring->mqd_obj) { + r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); + return r; + } + + /*TODO: prepare MQD backup */ + } + + /* create MQD for each KCQ */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + if (!ring->mqd_obj) { + r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); + return r; + } + + /* TODO: prepare MQD backup */ + } + } + + return 0; +} + +static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = NULL; + int i; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); + } + + ring = &adev->gfx.kiq.ring; + amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); +} + +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) +{ + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX), + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); + return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA)); +} + +static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t thread, + uint32_t regno, uint32_t num, uint32_t *out) +{ + WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX), + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (regno << SQ_IND_INDEX__INDEX__SHIFT) | + (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK) | + (SQ_IND_INDEX__AUTO_INCR_MASK)); + while (num--) + *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA)); +} + +static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) +{ + /* type 1 wave data */ + dst[(*no_fields)++] = 1; + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); +} + +static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t start, + uint32_t size, uint32_t *dst) +{ + wave_read_regs( + adev, simd, wave, 0, + start + SQIND_WAVE_SGPRS_OFFSET, size, dst); +} + + +static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { + .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, + .select_se_sh = &gfx_v9_0_select_se_sh, + .read_wave_data = &gfx_v9_0_read_wave_data, + .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, +}; + +static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) +{ + u32 gb_addr_config; + + adev->gfx.funcs = &gfx_v9_0_gfx_funcs; + + switch (adev->asic_type) { + case CHIP_VEGA10: + adev->gfx.config.max_shader_engines = 4; + adev->gfx.config.max_tile_pipes = 8; //?? + adev->gfx.config.max_cu_per_sh = 16; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 4; + adev->gfx.config.max_texture_channel_caches = 16; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; + break; + default: + BUG(); + break; + } + + adev->gfx.config.gb_addr_config = gb_addr_config; + + adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << + REG_GET_FIELD( + adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG, + NUM_PIPES); + adev->gfx.config.gb_addr_config_fields.num_banks = 1 << + REG_GET_FIELD( + adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG, + NUM_BANKS); + adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << + REG_GET_FIELD( + adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG, + MAX_COMPRESSED_FRAGS); + adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << + REG_GET_FIELD( + adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG, + NUM_RB_PER_SE); + adev->gfx.config.gb_addr_config_fields.num_se = 1 << + REG_GET_FIELD( + adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG, + NUM_SHADER_ENGINES); + adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + + REG_GET_FIELD( + adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG, + PIPE_INTERLEAVE_SIZE)); +} + +static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, + struct amdgpu_ngg_buf *ngg_buf, + int size_se, + int default_size_se) +{ + int r; + + if (size_se < 0) { + dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); + return -EINVAL; + } + size_se = size_se ? size_se : default_size_se; + + ngg_buf->size = size_se * GFX9_NUM_SE; + r = amdgpu_bo_create_kernel(adev, ngg_buf->size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, + &ngg_buf->bo, + &ngg_buf->gpu_addr, + NULL); + if (r) { + dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); + return r; + } + ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); + + return r; +} + +static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < NGG_BUF_MAX; i++) + amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, + &adev->gfx.ngg.buf[i].gpu_addr, + NULL); + + memset(&adev->gfx.ngg.buf[0], 0, + sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); + + adev->gfx.ngg.init = false; + + return 0; +} + +static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) +{ + int r; + + if (!amdgpu_ngg || adev->gfx.ngg.init == true) + return 0; + + /* GDS reserve memory: 64 bytes alignment */ + adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); + adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; + adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; + adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base; + adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; + + /* Primitive Buffer */ + r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM], + amdgpu_prim_buf_per_se, + 64 * 1024); + if (r) { + dev_err(adev->dev, "Failed to create Primitive Buffer\n"); + goto err; + } + + /* Position Buffer */ + r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS], + amdgpu_pos_buf_per_se, + 256 * 1024); + if (r) { + dev_err(adev->dev, "Failed to create Position Buffer\n"); + goto err; + } + + /* Control Sideband */ + r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL], + amdgpu_cntl_sb_buf_per_se, + 256); + if (r) { + dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); + goto err; + } + + /* Parameter Cache, not created by default */ + if (amdgpu_param_buf_per_se <= 0) + goto out; + + r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM], + amdgpu_param_buf_per_se, + 512 * 1024); + if (r) { + dev_err(adev->dev, "Failed to create Parameter Cache\n"); + goto err; + } + +out: + adev->gfx.ngg.init = true; + return 0; +err: + gfx_v9_0_ngg_fini(adev); + return r; +} + +static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; + int r; + u32 data; + u32 size; + u32 base; + + if (!amdgpu_ngg) + return 0; + + /* Program buffer size */ + data = 0; + size = adev->gfx.ngg.buf[PRIM].size / 256; + data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size); + + size = adev->gfx.ngg.buf[POS].size / 256; + data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data); + + data = 0; + size = adev->gfx.ngg.buf[CNTL].size / 256; + data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size); + + size = adev->gfx.ngg.buf[PARAM].size / 1024; + data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data); + + /* Program buffer base address */ + base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr); + data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data); + + base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr); + data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data); + + base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr); + data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data); + + base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr); + data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data); + + base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr); + data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data); + + base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr); + data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); + WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data); + + /* Clear GDS reserved memory */ + r = amdgpu_ring_alloc(ring, 17); + if (r) { + DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + + gfx_v9_0_write_data_to_reg(ring, 0, false, + amdgpu_gds_reg_offset[0].mem_size, + (adev->gds.mem.total_size + + adev->gfx.ngg.gds_reserve_size) >> + AMDGPU_GDS_SHIFT); + + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | + PACKET3_DMA_DATA_SRC_SEL(2))); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); + + + gfx_v9_0_write_data_to_reg(ring, 0, false, + amdgpu_gds_reg_offset[0].mem_size, 0); + + amdgpu_ring_commit(ring); + + return 0; +} + +static int gfx_v9_0_sw_init(void *handle) +{ + int i, r; + struct amdgpu_ring *ring; + struct amdgpu_kiq *kiq; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* KIQ event */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); + if (r) + return r; + + /* EOP Event */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq); + if (r) + return r; + + /* Privileged reg */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184, + &adev->gfx.priv_reg_irq); + if (r) + return r; + + /* Privileged inst */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185, + &adev->gfx.priv_inst_irq); + if (r) + return r; + + adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; + + gfx_v9_0_scratch_init(adev); + + r = gfx_v9_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load gfx firmware!\n"); + return r; + } + + r = gfx_v9_0_mec_init(adev); + if (r) { + DRM_ERROR("Failed to init MEC BOs!\n"); + return r; + } + + /* set up the gfx ring */ + for (i = 0; i < adev->gfx.num_gfx_rings; i++) { + ring = &adev->gfx.gfx_ring[i]; + ring->ring_obj = NULL; + sprintf(ring->name, "gfx"); + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; + r = amdgpu_ring_init(adev, ring, 1024, + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); + if (r) + return r; + } + + /* set up the compute queues */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + unsigned irq_type; + + /* max 32 queues per MEC */ + if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { + DRM_ERROR("Too many (%d) compute rings!\n", i); + break; + } + ring = &adev->gfx.compute_ring[i]; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1; + ring->me = 1; /* first MEC */ + ring->pipe = i / 8; + ring->queue = i % 8; + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); + sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024, + &adev->gfx.eop_irq, irq_type); + if (r) + return r; + } + + if (amdgpu_sriov_vf(adev)) { + r = gfx_v9_0_kiq_init(adev); + if (r) { + DRM_ERROR("Failed to init KIQ BOs!\n"); + return r; + } + + kiq = &adev->gfx.kiq; + r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); + if (r) + return r; + + /* create MQD for all compute queues as wel as KIQ for SRIOV case */ + r = gfx_v9_0_compute_mqd_sw_init(adev); + if (r) + return r; + } + + /* reserve GDS, GWS and OA resource for gfx */ + r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, + &adev->gds.gds_gfx_bo, NULL, NULL); + if (r) + return r; + + r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, + &adev->gds.gws_gfx_bo, NULL, NULL); + if (r) + return r; + + r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, + &adev->gds.oa_gfx_bo, NULL, NULL); + if (r) + return r; + + adev->gfx.ce_ram_size = 0x8000; + + gfx_v9_0_gpu_early_init(adev); + + r = gfx_v9_0_ngg_init(adev); + if (r) + return r; + + return 0; +} + + +static int gfx_v9_0_sw_fini(void *handle) +{ + int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + amdgpu_ring_fini(&adev->gfx.compute_ring[i]); + + if (amdgpu_sriov_vf(adev)) { + gfx_v9_0_compute_mqd_sw_fini(adev); + gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); + gfx_v9_0_kiq_fini(adev); + } + + gfx_v9_0_mec_fini(adev); + gfx_v9_0_ngg_fini(adev); + + return 0; +} + + +static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) +{ + /* TODO */ +} + +static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) +{ + u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); + + if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + } else if (se_num == 0xffffffff) { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + } else if (sh_num == 0xffffffff) { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); + } else { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); + } + WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); +} + +static u32 gfx_v9_0_create_bitmask(u32 bit_width) +{ + return (u32)((1ULL << bit_width) - 1); +} + +static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) +{ + u32 data, mask; + + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE)); + data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE)); + + data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; + data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; + + mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se); + + return (~data) & mask; +} + +static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) +{ + int i, j; + u32 data; + u32 active_rbs = 0; + u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); + data = gfx_v9_0_get_rb_active_bitmap(adev); + active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * + rb_bitmap_width_per_sh); + } + } + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + adev->gfx.config.backend_enable_mask = active_rbs; + adev->gfx.config.num_rbs = hweight32(active_rbs); +} + +#define DEFAULT_SH_MEM_BASES (0x6000) +#define FIRST_COMPUTE_VMID (8) +#define LAST_COMPUTE_VMID (16) +static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) +{ + int i; + uint32_t sh_mem_config; + uint32_t sh_mem_bases; + + /* + * Configure apertures: + * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) + * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) + * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) + */ + sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); + + sh_mem_config = SH_MEM_ADDRESS_MODE_64 | + SH_MEM_ALIGNMENT_MODE_UNALIGNED << + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; + + mutex_lock(&adev->srbm_mutex); + for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { + soc15_grbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); + } + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + +static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) +{ + u32 tmp; + int i; + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL)); + tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); + WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp); + + gfx_v9_0_tiling_mode_table_init(adev); + + gfx_v9_0_setup_rb(adev); + gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); + + /* XXX SH_MEM regs */ + /* where to put LDS, scratch, GPUVM in FSA64 space */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < 16; i++) { + soc15_grbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + tmp = 0; + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0); + } + soc15_grbm_select(adev, 0, 0, 0, 0); + + mutex_unlock(&adev->srbm_mutex); + + gfx_v9_0_init_compute_vmid(adev); + + mutex_lock(&adev->grbm_idx_mutex); + /* + * making sure that the following register writes will be broadcasted + * to all the shaders + */ + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE), + (adev->gfx.config.sc_prim_fifo_size_frontend << + PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_prim_fifo_size_backend << + PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_hiz_tile_fifo_size << + PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_earlyz_tile_fifo_size << + PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); + mutex_unlock(&adev->grbm_idx_mutex); + +} + +static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) +{ + u32 i, j, k; + u32 mask; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); + for (k = 0; k < adev->usec_timeout; k++) { + if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0) + break; + udelay(1); + } + } + } + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; + for (k = 0; k < adev->usec_timeout; k++) { + if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0) + break; + udelay(1); + } +} + +static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + + if (enable) + return; + + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp); +} + +void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); + + tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp); + + gfx_v9_0_enable_gui_idle_interrupt(adev, false); + + gfx_v9_0_wait_for_rlc_serdes(adev); +} + +static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); + + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); + udelay(50); + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); + udelay(50); +} + +static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) +{ +#ifdef AMDGPU_RLC_DEBUG_RETRY + u32 rlc_ucode_ver; +#endif + u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); + + tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp); + + /* carrizo do enable cp interrupt after cp inited */ + if (!(adev->flags & AMD_IS_APU)) + gfx_v9_0_enable_gui_idle_interrupt(adev, true); + + udelay(50); + +#ifdef AMDGPU_RLC_DEBUG_RETRY + /* RLC_GPM_GENERAL_6 : RLC Ucode version */ + rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6)); + if(rlc_ucode_ver == 0x108) { + DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", + rlc_ucode_ver, adev->gfx.rlc_fw_version); + /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, + * default is 0x9C4 to create a 100us interval */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4); + /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr + * to disable the page fault retry interrupts, default is + * 0x100 (256) */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100); + } +#endif +} + +static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) +{ + const struct rlc_firmware_header_v2_0 *hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.rlc_fw) + return -EINVAL; + + hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + amdgpu_ucode_print_rlc_hdr(&hdr->header); + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), + RLCG_UCODE_LOADING_START_ADDRESS); + for (i = 0; i < fw_size; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version); + + return 0; +} + +static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) +{ + int r; + + if (amdgpu_sriov_vf(adev)) + return 0; + + gfx_v9_0_rlc_stop(adev); + + /* disable CG */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0); + + /* disable PG */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0); + + gfx_v9_0_rlc_reset(adev); + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + /* legacy rlc firmware loading */ + r = gfx_v9_0_rlc_load_microcode(adev); + if (r) + return r; + } + + gfx_v9_0_rlc_start(adev); + + return 0; +} + +static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) +{ + int i; + u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)); + + if (enable) { + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); + } else { + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].ready = false; + } + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp); + udelay(50); +} + +static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v1_0 *pfp_hdr; + const struct gfx_firmware_header_v1_0 *ce_hdr; + const struct gfx_firmware_header_v1_0 *me_hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) + return -EINVAL; + + pfp_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.pfp_fw->data; + ce_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.ce_fw->data; + me_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.me_fw->data; + + amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); + amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); + amdgpu_ucode_print_gfx_hdr(&me_hdr->header); + + gfx_v9_0_cp_gfx_enable(adev, false); + + /* PFP */ + fw_data = (const __le32 *) + (adev->gfx.pfp_fw->data + + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0); + for (i = 0; i < fw_size; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version); + + /* CE */ + fw_data = (const __le32 *) + (adev->gfx.ce_fw->data + + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0); + for (i = 0; i < fw_size; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version); + + /* ME */ + fw_data = (const __le32 *) + (adev->gfx.me_fw->data + + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0); + for (i = 0; i < fw_size; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version); + + return 0; +} + +static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) +{ + u32 count = 0; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + /* begin clear state */ + count += 2; + /* context control state */ + count += 3; + + for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) + count += 2 + ext->reg_count; + else + return 0; + } + } + /* pa_sc_raster_config/pa_sc_raster_config1 */ + count += 4; + /* end clear state */ + count += 2; + /* clear state */ + count += 2; + + return count; +} + +static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + int r, i; + + /* init the CP */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1); + + gfx_v9_0_cp_gfx_enable(adev, true); + + r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + return r; + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + amdgpu_ring_write(ring, 0x80000000); + amdgpu_ring_write(ring, 0x80000000); + + for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) { + amdgpu_ring_write(ring, + PACKET3(PACKET3_SET_CONTEXT_REG, + ext->reg_count)); + amdgpu_ring_write(ring, + ext->reg_index - PACKET3_SET_CONTEXT_REG_START); + for (i = 0; i < ext->reg_count; i++) + amdgpu_ring_write(ring, ext->extent[i]); + } + } + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); + + amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); + amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); + amdgpu_ring_write(ring, 0x8000); + amdgpu_ring_write(ring, 0x8000); + + amdgpu_ring_commit(ring); + + return 0; +} + +static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 tmp; + u32 rb_bufsz; + u64 rb_addr, rptr_addr, wptr_gpu_addr; + + /* Set the write pointer delay */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0); + + /* set the RB to use vmid 0 */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0); + + /* Set ring buffer size */ + ring = &adev->gfx.gfx_ring[0]; + rb_bufsz = order_base_2(ring->ring_size / 8); + tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); +#ifdef __BIG_ENDIAN + tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); +#endif + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp); + + /* Initialize the ring buffer's write pointers */ + ring->wptr = 0; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr)); + + /* set the wb address wether it's enabled or not */ + rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); + + wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr)); + + mdelay(1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp); + + rb_addr = ring->gpu_addr >> 8; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr)); + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL)); + if (ring->use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_EN, 1); + } else { + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); + } + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp); + + tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, + DOORBELL_RANGE_LOWER, ring->doorbell_index); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER), + CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); + + + /* start the ring */ + gfx_v9_0_cp_gfx_start(adev); + ring->ready = true; + + return 0; +} + +static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) +{ + int i; + + if (enable) { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0); + } else { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), + (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].ready = false; + adev->gfx.kiq.ring.ready = false; + } + udelay(50); +} + +static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev) +{ + gfx_v9_0_cp_compute_enable(adev, true); + + return 0; +} + +static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v1_0 *mec_hdr; + const __le32 *fw_data; + unsigned i; + u32 tmp; + + if (!adev->gfx.mec_fw) + return -EINVAL; + + gfx_v9_0_cp_compute_enable(adev, false); + + mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); + + fw_data = (const __le32 *) + (adev->gfx.mec_fw->data + + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); + tmp = 0; + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO), + adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI), + upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); + + /* MEC1 */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR), + mec_hdr->jt_offset); + for (i = 0; i < mec_hdr->jt_size; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA), + le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR), + adev->gfx.mec_fw_version); + /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ + + return 0; +} + +static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + + if (ring->mqd_obj) { + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); + + amdgpu_bo_unpin(ring->mqd_obj); + amdgpu_bo_unreserve(ring->mqd_obj); + + amdgpu_bo_unref(&ring->mqd_obj); + ring->mqd_obj = NULL; + } + } +} + +static int gfx_v9_0_init_queue(struct amdgpu_ring *ring); + +static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev) +{ + int i, r; + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + if (gfx_v9_0_init_queue(ring)) + dev_warn(adev->dev, "compute queue %d init failed!\n", i); + } + + r = gfx_v9_0_cp_compute_start(adev); + if (r) + return r; + + return 0; +} + +/* KIQ functions */ +static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) +{ + uint32_t tmp; + struct amdgpu_device *adev = ring->adev; + + /* tell RLC which is KIQ queue */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); + tmp &= 0xffffff00; + tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp); + tmp |= 0x80; + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp); +} + +static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) +{ + amdgpu_ring_alloc(ring, 8); + /* set resources */ + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); + amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ + amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */ + amdgpu_ring_write(ring, 0); /* queue mask hi */ + amdgpu_ring_write(ring, 0); /* gws mask lo */ + amdgpu_ring_write(ring, 0); /* gws mask hi */ + amdgpu_ring_write(ring, 0); /* oac mask */ + amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */ + amdgpu_ring_commit(ring); + udelay(50); +} + +static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, + struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = kiq_ring->adev; + uint64_t mqd_addr, wptr_addr; + + mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); + wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + amdgpu_ring_alloc(kiq_ring, 8); + + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); + /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + (0 << 4) | /* Queue_Sel */ + (0 << 8) | /* VMID */ + (ring->queue << 13 ) | + (ring->pipe << 16) | + ((ring->me == 1 ? 0 : 1) << 18) | + (0 << 21) | /*queue_type: normal compute queue */ + (1 << 24) | /* alloc format: all_on_one_pipe */ + (0 << 26) | /* engine_sel: compute */ + (1 << 29)); /* num_queues: must be 1 */ + amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2)); + amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); + amdgpu_ring_commit(kiq_ring); + udelay(50); +} + +static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct v9_mqd *mqd = ring->mqd_ptr; + uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; + uint32_t tmp; + + mqd->header = 0xC0310800; + mqd->compute_pipelinestat_enable = 0x00000001; + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; + mqd->compute_misc_reserved = 0x00000003; + + eop_base_addr = ring->eop_gpu_addr >> 8; + mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; + mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, + (order_base_2(MEC_HPD_SIZE / 4) - 1)); + + mqd->cp_hqd_eop_control = tmp; + + /* enable doorbell? */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); + + if (ring->use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_HIT, 0); + } + else + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 0); + + mqd->cp_hqd_pq_doorbell_control = tmp; + + /* disable the queue if it's active */ + ring->wptr = 0; + mqd->cp_hqd_dequeue_request = 0; + mqd->cp_hqd_pq_rptr = 0; + mqd->cp_hqd_pq_wptr_lo = 0; + mqd->cp_hqd_pq_wptr_hi = 0; + + /* set the pointer to the MQD */ + mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); + + /* set MQD vmid to 0 */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); + mqd->cp_mqd_control = tmp; + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = ring->gpu_addr >> 8; + mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, + (order_base_2(ring->ring_size / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, + ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); +#ifdef __BIG_ENDIAN + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); +#endif + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + mqd->cp_hqd_pq_control = tmp; + + /* set the wb address whether it's enabled or not */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + + tmp = 0; + /* enable the doorbell if requested */ + if (ring->use_doorbell) { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_HIT, 0); + } + + mqd->cp_hqd_pq_doorbell_control = tmp; + + /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + ring->wptr = 0; + mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); + + /* set the vmid for the queue */ + mqd->cp_hqd_vmid = 0; + + tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); + tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); + mqd->cp_hqd_persistent_state = tmp; + + /* activate the queue */ + mqd->cp_hqd_active = 1; + + return 0; +} + +static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct v9_mqd *mqd = ring->mqd_ptr; + uint32_t tmp; + int j; + + /* disable wptr polling */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL)); + tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), + mqd->cp_hqd_eop_base_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), + mqd->cp_hqd_eop_base_addr_hi); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), + mqd->cp_hqd_eop_control); + + /* enable doorbell? */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), + mqd->cp_hqd_pq_doorbell_control); + + /* disable the queue if it's active */ + if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1); + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1)) + break; + udelay(1); + } + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), + mqd->cp_hqd_dequeue_request); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), + mqd->cp_hqd_pq_rptr); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), + mqd->cp_hqd_pq_wptr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), + mqd->cp_hqd_pq_wptr_hi); + } + + /* set the pointer to the MQD */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), + mqd->cp_mqd_base_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), + mqd->cp_mqd_base_addr_hi); + + /* set MQD vmid to 0 */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), + mqd->cp_mqd_control); + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), + mqd->cp_hqd_pq_base_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), + mqd->cp_hqd_pq_base_hi); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), + mqd->cp_hqd_pq_control); + + /* set the wb address whether it's enabled or not */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR), + mqd->cp_hqd_pq_rptr_report_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI), + mqd->cp_hqd_pq_rptr_report_addr_hi); + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), + mqd->cp_hqd_pq_wptr_poll_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), + mqd->cp_hqd_pq_wptr_poll_addr_hi); + + /* enable the doorbell if requested */ + if (ring->use_doorbell) { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER), + (AMDGPU_DOORBELL64_KIQ *2) << 2); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER), + (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2); + } + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), + mqd->cp_hqd_pq_doorbell_control); + + /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), + mqd->cp_hqd_pq_wptr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), + mqd->cp_hqd_pq_wptr_hi); + + /* set the vmid for the queue */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), + mqd->cp_hqd_persistent_state); + + /* activate the queue */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), + mqd->cp_hqd_active); + + if (ring->use_doorbell) { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS)); + tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp); + } + + return 0; +} + +static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + struct v9_mqd *mqd = ring->mqd_ptr; + bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); + int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; + + if (is_kiq) { + gfx_v9_0_kiq_setting(&kiq->ring); + } else { + mqd_idx = ring - &adev->gfx.compute_ring[0]; + } + + if (!adev->gfx.in_reset) { + memset((void *)mqd, 0, sizeof(*mqd)); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v9_0_mqd_init(ring); + if (is_kiq) + gfx_v9_0_kiq_init_register(ring); + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + } else { /* for GPU_RESET case */ + /* reset MQD to a clean status */ + + /* reset ring buffer */ + ring->wptr = 0; + + if (is_kiq) { + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + gfx_v9_0_kiq_init_register(ring); + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } + } + + if (is_kiq) + gfx_v9_0_kiq_enable(ring); + else + gfx_v9_0_map_queue_enable(&kiq->ring, ring); + + return 0; +} + +static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = NULL; + int r = 0, i; + + gfx_v9_0_cp_compute_enable(adev, true); + + ring = &adev->gfx.kiq.ring; + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + goto done; + + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v9_0_kiq_init_queue(ring); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) + goto done; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + goto done; + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v9_0_kiq_init_queue(ring); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) + goto done; + } + +done: + return r; +} + +static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) +{ + int r,i; + struct amdgpu_ring *ring; + + if (!(adev->flags & AMD_IS_APU)) + gfx_v9_0_enable_gui_idle_interrupt(adev, false); + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + /* legacy firmware loading */ + r = gfx_v9_0_cp_gfx_load_microcode(adev); + if (r) + return r; + + r = gfx_v9_0_cp_compute_load_microcode(adev); + if (r) + return r; + } + + r = gfx_v9_0_cp_gfx_resume(adev); + if (r) + return r; + + if (amdgpu_sriov_vf(adev)) + r = gfx_v9_0_kiq_resume(adev); + else + r = gfx_v9_0_cp_compute_resume(adev); + if (r) + return r; + + ring = &adev->gfx.gfx_ring[0]; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) + ring->ready = false; + } + + if (amdgpu_sriov_vf(adev)) { + ring = &adev->gfx.kiq.ring; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) + ring->ready = false; + } + + gfx_v9_0_enable_gui_idle_interrupt(adev, true); + + return 0; +} + +static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) +{ + gfx_v9_0_cp_gfx_enable(adev, enable); + gfx_v9_0_cp_compute_enable(adev, enable); +} + +static int gfx_v9_0_hw_init(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + gfx_v9_0_init_golden_registers(adev); + + gfx_v9_0_gpu_init(adev); + + r = gfx_v9_0_rlc_resume(adev); + if (r) + return r; + + r = gfx_v9_0_cp_resume(adev); + if (r) + return r; + + r = gfx_v9_0_ngg_en(adev); + if (r) + return r; + + return r; +} + +static int gfx_v9_0_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + if (amdgpu_sriov_vf(adev)) { + pr_debug("For SRIOV client, shouldn't do anything.\n"); + return 0; + } + gfx_v9_0_cp_enable(adev, false); + gfx_v9_0_rlc_stop(adev); + gfx_v9_0_cp_compute_fini(adev); + + return 0; +} + +static int gfx_v9_0_suspend(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return gfx_v9_0_hw_fini(adev); +} + +static int gfx_v9_0_resume(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return gfx_v9_0_hw_init(adev); +} + +static bool gfx_v9_0_is_idle(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)), + GRBM_STATUS, GUI_ACTIVE)) + return false; + else + return true; +} + +static int gfx_v9_0_wait_for_idle(void *handle) +{ + unsigned i; + u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) & + GRBM_STATUS__GUI_ACTIVE_MASK; + + if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void gfx_v9_0_print_status(void *handle) +{ + int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + dev_info(adev->dev, "GFX 9.x registers\n"); + dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS))); + dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2))); + dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0))); + dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1))); + dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2))); + dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3))); + dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STAT))); + dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1))); + dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2))); + dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3))); + dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT))); + dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1))); + dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS))); + dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT))); + dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1))); + dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS))); + + for (i = 0; i < 32; i++) { + dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", + i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + i*4)); + } + for (i = 0; i < 16; i++) { + dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", + i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_MACROTILE_MODE0) + i*4)); + } + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + dev_info(adev->dev, " se: %d\n", i); + gfx_v9_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff); + dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG))); + dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG_1))); + } + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + + dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))); + + dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS))); + dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1))); + dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX))); + dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL))); + dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG))); + dev_info(adev->dev, " DB_DEBUG=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG))); + dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))); + dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3))); + dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL))); + dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1))); + dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE))); + dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_NUM_INSTANCES))); + dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL))); + dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FORCE_EOV_MAX_CNTS))); + dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION))); + dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_GS_VERTEX_REUSE))); + dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE))); + dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_CL_ENHANCE))); + dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE))); + + dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL))); + dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT))); + dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID))); + + dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_SEM_WAIT_TIMER))); + + dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY))); + dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID))); + dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL))); + dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR))); + dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR))); + dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI))); + dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL))); + dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE))); + dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI))); + dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL))); + + dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_ADDR))); + dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_UMSK))); + + dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0))); + dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL))); + dev_info(adev->dev, " RLC_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL))); + dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL))); + dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_INIT))); + dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_MAX))); + dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_INIT_CU_MASK))); + dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_PARAMS))); + dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL))); + dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_UCODE_CNTL))); + + dev_info(adev->dev, " RLC_GPM_GENERAL_6=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6))); + dev_info(adev->dev, " RLC_GPM_GENERAL_12=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12))); + dev_info(adev->dev, " RLC_GPM_TIMER_INT_3=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3))); + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < 16; i++) { + soc15_grbm_select(adev, 0, 0, 0, i); + dev_info(adev->dev, " VM %d:\n", i); + dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))); + dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", + RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES))); + } + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + +static int gfx_v9_0_soft_reset(void *handle) +{ + u32 grbm_soft_reset = 0; + u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* GRBM_STATUS */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)); + if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | + GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | + GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | + GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | + GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | + GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_CP, 1); + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); + } + + if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_CP, 1); + } + + /* GRBM_STATUS2 */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)); + if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); + + + if (grbm_soft_reset ) { + gfx_v9_0_print_status((void *)adev); + /* stop the rlc */ + gfx_v9_0_rlc_stop(adev); + + /* Disable GFX parsing/prefetching */ + gfx_v9_0_cp_gfx_enable(adev, false); + + /* Disable MEC parsing/prefetching */ + gfx_v9_0_cp_compute_enable(adev, false); + + if (grbm_soft_reset) { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); + } + + /* Wait a little for things to settle down */ + udelay(50); + gfx_v9_0_print_status((void *)adev); + } + return 0; +} + +static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) +{ + uint64_t clock; + + mutex_lock(&adev->gfx.gpu_clock_mutex); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1); + clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) | + ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL); + mutex_unlock(&adev->gfx.gpu_clock_mutex); + return clock; +} + +static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, + uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size) +{ + gds_base = gds_base >> AMDGPU_GDS_SHIFT; + gds_size = gds_size >> AMDGPU_GDS_SHIFT; + + gws_base = gws_base >> AMDGPU_GWS_SHIFT; + gws_size = gws_size >> AMDGPU_GWS_SHIFT; + + oa_base = oa_base >> AMDGPU_OA_SHIFT; + oa_size = oa_size >> AMDGPU_OA_SHIFT; + + /* GDS Base */ + gfx_v9_0_write_data_to_reg(ring, 0, false, + amdgpu_gds_reg_offset[vmid].mem_base, + gds_base); + + /* GDS Size */ + gfx_v9_0_write_data_to_reg(ring, 0, false, + amdgpu_gds_reg_offset[vmid].mem_size, + gds_size); + + /* GWS */ + gfx_v9_0_write_data_to_reg(ring, 0, false, + amdgpu_gds_reg_offset[vmid].gws, + gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); + + /* OA */ + gfx_v9_0_write_data_to_reg(ring, 0, false, + amdgpu_gds_reg_offset[vmid].oa, + (1 << (oa_size + oa_base)) - (1 << oa_base)); +} + +static int gfx_v9_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; + adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS; + gfx_v9_0_set_ring_funcs(adev); + gfx_v9_0_set_irq_funcs(adev); + gfx_v9_0_set_gds_init(adev); + gfx_v9_0_set_rlc_funcs(adev); + + return 0; +} + +static int gfx_v9_0_late_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; + + r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); + if (r) + return r; + + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); + if (r) + return r; + + return 0; +} + +static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) +{ + uint32_t rlc_setting, data; + unsigned i; + + if (adev->gfx.rlc.in_safe_mode) + return; + + /* if RLC is not enabled, do nothing */ + rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); + if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) + return; + + if (adev->cg_flags & + (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_3D_CGCG)) { + data = RLC_SAFE_MODE__CMD_MASK; + data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data); + + /* wait for RLC_SAFE_MODE */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) + break; + udelay(1); + } + adev->gfx.rlc.in_safe_mode = true; + } +} + +static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) +{ + uint32_t rlc_setting, data; + + if (!adev->gfx.rlc.in_safe_mode) + return; + + /* if RLC is not enabled, do nothing */ + rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); + if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) + return; + + if (adev->cg_flags & + (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { + /* + * Try to exit safe mode only if it is already in safe + * mode. + */ + data = RLC_SAFE_MODE__CMD_MASK; + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data); + adev->gfx.rlc.in_safe_mode = false; + } +} + +static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, def; + + /* It is disabled by HW by default */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { + /* 1 - RLC_CGTT_MGCG_OVERRIDE */ + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); + data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); + + /* only for Vega10 & Raven1 */ + data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; + + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); + + /* MGLS is a global flag to control all MGLS in GFX */ + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { + /* 2 - RLC memory Light sleep */ + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); + data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data); + } + /* 3 - CP memory Light sleep */ + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); + data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data); + } + } + } else { + /* 1 - MGCG_OVERRIDE */ + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); + data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); + + /* 2 - disable MGLS in RLC */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); + if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { + data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data); + } + + /* 3 - disable MGLS in CP */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); + if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { + data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data); + } + } +} + +static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, def; + + adev->gfx.rlc.funcs->enter_safe_mode(adev); + + /* Enable 3D CGCG/CGLS */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { + /* write cmd to clear cgcg/cgls ov */ + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); + /* unset CGCG override */ + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; + /* update CGCG and CGLS override bits */ + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); + /* enable 3Dcgcg FSM(0x0020003f) */ + def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); + data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | + RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) + data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | + RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data); + + /* set IDLE_POLL_COUNT(0x00900100) */ + def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); + data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | + (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); + } else { + /* Disable CGCG/CGLS */ + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); + /* disable cgcg, cgls should be disabled */ + data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | + RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); + /* disable cgcg and cgls in FSM */ + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data); + } + + adev->gfx.rlc.funcs->exit_safe_mode(adev); +} + +static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + adev->gfx.rlc.funcs->enter_safe_mode(adev); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); + /* unset CGCG override */ + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; + else + data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; + /* update CGCG and CGLS override bits */ + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); + + /* enable cgcg FSM(0x0020003F) */ + def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); + data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | + RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) + data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | + RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data); + + /* set IDLE_POLL_COUNT(0x00900100) */ + def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); + data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | + (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); + } else { + def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); + /* reset CGCG/CGLS bits */ + data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); + /* disable cgcg and cgls in FSM */ + if (def != data) + WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data); + } + + adev->gfx.rlc.funcs->exit_safe_mode(adev); +} + +static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + if (enable) { + /* CGCG/CGLS should be enabled after MGCG/MGLS + * === MGCG + MGLS === + */ + gfx_v9_0_update_medium_grain_clock_gating(adev, enable); + /* === CGCG /CGLS for GFX 3D Only === */ + gfx_v9_0_update_3d_clock_gating(adev, enable); + /* === CGCG + CGLS === */ + gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); + } else { + /* CGCG/CGLS should be disabled before MGCG/MGLS + * === CGCG + CGLS === + */ + gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); + /* === CGCG /CGLS for GFX 3D Only === */ + gfx_v9_0_update_3d_clock_gating(adev, enable); + /* === MGCG + MGLS === */ + gfx_v9_0_update_medium_grain_clock_gating(adev, enable); + } + return 0; +} + +static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { + .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, + .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode +}; + +static int gfx_v9_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +static int gfx_v9_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + switch (adev->asic_type) { + case CHIP_VEGA10: + gfx_v9_0_update_gfx_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + break; + default: + break; + } + return 0; +} + +static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int data; + + if (amdgpu_sriov_vf(adev)) + *flags = 0; + + /* AMD_CG_SUPPORT_GFX_MGCG */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); + if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) + *flags |= AMD_CG_SUPPORT_GFX_MGCG; + + /* AMD_CG_SUPPORT_GFX_CGCG */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); + if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_CGCG; + + /* AMD_CG_SUPPORT_GFX_CGLS */ + if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_CGLS; + + /* AMD_CG_SUPPORT_GFX_RLC_LS */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); + if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; + + /* AMD_CG_SUPPORT_GFX_CP_LS */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); + if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; + + /* AMD_CG_SUPPORT_GFX_3D_CGCG */ + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); + if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; + + /* AMD_CG_SUPPORT_GFX_3D_CGLS */ + if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; +} + +static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) +{ + return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ +} + +static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u64 wptr; + + /* XXX check if swapping is necessary on BE */ + if (ring->use_doorbell) { + wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); + } else { + wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR)); + wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32; + } + + return wptr; +} + +static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); + WDOORBELL64(ring->doorbell_index, ring->wptr); + } else { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr)); + } +} + +static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +{ + u32 ref_and_mask, reg_mem_engine; + struct nbio_hdp_flush_reg *nbio_hf_reg; + + if (ring->adev->asic_type == CHIP_VEGA10) + nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; + + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { + switch (ring->me) { + case 1: + ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; + break; + case 2: + ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; + break; + default: + return; + } + reg_mem_engine = 0; + } else { + ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; + reg_mem_engine = 1; /* pfp */ + } + + gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, + nbio_hf_reg->hdp_flush_req_offset, + nbio_hf_reg->hdp_flush_done_offset, + ref_and_mask, ref_and_mask, 0x20); +} + +static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +{ + gfx_v9_0_write_data_to_reg(ring, 0, true, + SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1); +} + +static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) +{ + u32 header, control = 0; + + if (ib->flags & AMDGPU_IB_FLAG_CE) + header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); + else + header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); + + control |= ib->length_dw | (vm_id << 24); + + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) + control |= INDIRECT_BUFFER_PRE_ENB(1); + + amdgpu_ring_write(ring, header); + BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ + amdgpu_ring_write(ring, +#ifdef __BIG_ENDIAN + (2 << 0) | +#endif + lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, control); +} + +#define INDIRECT_BUFFER_VALID (1 << 23) + +static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) +{ + u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); + + amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ + amdgpu_ring_write(ring, +#ifdef __BIG_ENDIAN + (2 << 0) | +#endif + lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, control); +} + +static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) +{ + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + + /* RELEASE_MEM - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); + amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | + EOP_TC_WB_ACTION_EN | + EOP_TC_MD_ACTION_EN | + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + EVENT_INDEX(5))); + amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); + + /* + * the address should be Qword aligned if 64bit write, Dword + * aligned if only send 32bit data low (discard data high) + */ + if (write64bit) + BUG_ON(addr & 0x7); + else + BUG_ON(addr & 0x3); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + amdgpu_ring_write(ring, 0); +} + +static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +{ + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; + + gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, + lower_32_bits(addr), upper_32_bits(addr), + seq, 0xffffffff, 4); +} + +static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); + unsigned eng = ring->idx; + unsigned i; + + pd_addr = pd_addr | 0x1; /* valid bit */ + /* now only use physical base address of PDE and valid */ + BUG_ON(pd_addr & 0xFFFF00000000003EULL); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; + uint32_t req = hub->get_invalidate_req(vm_id); + + gfx_v9_0_write_data_to_reg(ring, usepfp, true, + hub->ctx0_ptb_addr_lo32 + + (2 * vm_id), + lower_32_bits(pd_addr)); + + gfx_v9_0_write_data_to_reg(ring, usepfp, true, + hub->ctx0_ptb_addr_hi32 + + (2 * vm_id), + upper_32_bits(pd_addr)); + + gfx_v9_0_write_data_to_reg(ring, usepfp, true, + hub->vm_inv_eng0_req + eng, req); + + /* wait for the invalidate to complete */ + gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + + eng, 0, 1 << vm_id, 1 << vm_id, 0x20); + } + + /* compute doesn't have PFP */ + if (usepfp) { + /* sync PFP to ME, otherwise we might get invalid PFP reads */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); + amdgpu_ring_write(ring, 0x0); + } +} + +static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) +{ + return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ +} + +static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) +{ + u64 wptr; + + /* XXX check if swapping is necessary on BE */ + if (ring->use_doorbell) + wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); + else + BUG(); + return wptr; +} + +static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + /* XXX check if swapping is necessary on BE */ + if (ring->use_doorbell) { + atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); + WDOORBELL64(ring->doorbell_index, ring->wptr); + } else{ + BUG(); /* only DOORBELL method supported on gfx9 now */ + } +} + +static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned int flags) +{ + /* we only allocate 32bit for each seq wb address */ + BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + /* write fence seq to the "addr" */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + if (flags & AMDGPU_FENCE_FLAG_INT) { + /* set register to trigger INT */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ + } +} + +static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); + amdgpu_ring_write(ring, 0); +} + +static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) +{ + static struct v9_ce_ib_state ce_payload = {0}; + uint64_t csa_addr; + int cnt; + + cnt = (sizeof(ce_payload) >> 2) + 4 - 2; + csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; + + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | + WRITE_DATA_DST_SEL(8) | + WR_CONFIRM) | + WRITE_DATA_CACHE_POLICY(0)); + amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); + amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); + amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); +} + +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) +{ + static struct v9_de_ib_state de_payload = {0}; + uint64_t csa_addr, gds_addr; + int cnt; + + csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; + gds_addr = csa_addr + 4096; + de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); + de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); + + cnt = (sizeof(de_payload) >> 2) + 4 - 2; + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | + WRITE_DATA_DST_SEL(8) | + WR_CONFIRM) | + WRITE_DATA_CACHE_POLICY(0)); + amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); + amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); + amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); +} + +static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) +{ + uint32_t dw2 = 0; + + if (amdgpu_sriov_vf(ring->adev)) + gfx_v9_0_ring_emit_ce_meta(ring); + + dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ + if (flags & AMDGPU_HAVE_CTX_SWITCH) { + /* set load_global_config & load_global_uconfig */ + dw2 |= 0x8001; + /* set load_cs_sh_regs */ + dw2 |= 0x01000000; + /* set load_per_context_state & load_gfx_sh_regs for GFX */ + dw2 |= 0x10002; + + /* set load_ce_ram if preamble presented */ + if (AMDGPU_PREAMBLE_IB_PRESENT & flags) + dw2 |= 0x10000000; + } else { + /* still load_ce_ram if this is the first time preamble presented + * although there is no context switch happens. + */ + if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) + dw2 |= 0x10000000; + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + amdgpu_ring_write(ring, dw2); + amdgpu_ring_write(ring, 0); + + if (amdgpu_sriov_vf(ring->adev)) + gfx_v9_0_ring_emit_de_meta(ring); +} + +static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) +{ + unsigned ret; + amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); + amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); + amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ + ret = ring->wptr & ring->buf_mask; + amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ + return ret; +} + +static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) +{ + unsigned cur; + BUG_ON(offset > ring->buf_mask); + BUG_ON(ring->ring[offset] != 0x55aa55aa); + + cur = (ring->wptr & ring->buf_mask) - 1; + if (likely(cur > offset)) + ring->ring[offset] = cur - offset; + else + ring->ring[offset] = (ring->ring_size>>2) - offset + cur; +} + +static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) +{ + struct amdgpu_device *adev = ring->adev; + + amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); + amdgpu_ring_write(ring, 0 | /* src: register*/ + (5 << 8) | /* dst: memory */ + (1 << 20)); /* write confirm */ + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + + adev->virt.reg_val_offs * 4)); + amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + + adev->virt.reg_val_offs * 4)); +} + +static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */ + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + TIME_STAMP_INT_ENABLE, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + cp_int_cntl = + REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + TIME_STAMP_INT_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); + break; + default: + break; + } +} + +static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, + int me, int pipe, + enum amdgpu_interrupt_state state) +{ + u32 mec_int_cntl, mec_int_cntl_reg; + + /* + * amdgpu controls only pipe 0 of MEC1. That's why this function only + * handles the setting of interrupts for this specific pipe. All other + * pipes' interrupts are set by amdkfd. + */ + + if (me == 1) { + switch (pipe) { + case 0: + mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); + break; + default: + DRM_DEBUG("invalid pipe %d\n", pipe); + return; + } + } else { + DRM_DEBUG("invalid me %d\n", me); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + TIME_STAMP_INT_ENABLE, 0); + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + TIME_STAMP_INT_ENABLE, 1); + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + default: + break; + } +} + +static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_REG_INT_ENABLE, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_REG_INT_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_INSTR_INT_ENABLE, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_INSTR_INT_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + switch (type) { + case AMDGPU_CP_IRQ_GFX_EOP: + gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: + gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); + break; + default: + break; + } + return 0; +} + +static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int i; + u8 me_id, pipe_id, queue_id; + struct amdgpu_ring *ring; + + DRM_DEBUG("IH: CP EOP\n"); + me_id = (entry->ring_id & 0x0c) >> 2; + pipe_id = (entry->ring_id & 0x03) >> 0; + queue_id = (entry->ring_id & 0x70) >> 4; + + switch (me_id) { + case 0: + amdgpu_fence_process(&adev->gfx.gfx_ring[0]); + break; + case 1: + case 2: + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + /* Per-queue interrupt is supported for MEC starting from VI. + * The interrupt can only be enabled/disabled per pipe instead of per queue. + */ + if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) + amdgpu_fence_process(ring); + } + break; + } + return 0; +} + +static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal register access in command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + uint32_t tmp, target; + struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data; + + BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)); + + if (ring->me == 1) + target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); + else + target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); + target += ring->pipe; + + switch (type) { + case AMDGPU_CP_KIQ_IRQ_DRIVER0: + if (state == AMDGPU_IRQ_STATE_DISABLE) { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL)); + tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, + GENERIC2_INT_ENABLE, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp); + + tmp = RREG32(target); + tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, + GENERIC2_INT_ENABLE, 0); + WREG32(target, tmp); + } else { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL)); + tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, + GENERIC2_INT_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp); + + tmp = RREG32(target); + tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, + GENERIC2_INT_ENABLE, 1); + WREG32(target, tmp); + } + break; + default: + BUG(); /* kiq only support GENERIC2_INT now */ + break; + } + return 0; +} + +static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u8 me_id, pipe_id, queue_id; + struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data; + + BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)); + + me_id = (entry->ring_id & 0x0c) >> 2; + pipe_id = (entry->ring_id & 0x03) >> 0; + queue_id = (entry->ring_id & 0x70) >> 4; + DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", + me_id, pipe_id, queue_id); + + amdgpu_fence_process(ring); + return 0; +} + +const struct amd_ip_funcs gfx_v9_0_ip_funcs = { + .name = "gfx_v9_0", + .early_init = gfx_v9_0_early_init, + .late_init = gfx_v9_0_late_init, + .sw_init = gfx_v9_0_sw_init, + .sw_fini = gfx_v9_0_sw_fini, + .hw_init = gfx_v9_0_hw_init, + .hw_fini = gfx_v9_0_hw_fini, + .suspend = gfx_v9_0_suspend, + .resume = gfx_v9_0_resume, + .is_idle = gfx_v9_0_is_idle, + .wait_for_idle = gfx_v9_0_wait_for_idle, + .soft_reset = gfx_v9_0_soft_reset, + .set_clockgating_state = gfx_v9_0_set_clockgating_state, + .set_powergating_state = gfx_v9_0_set_powergating_state, + .get_clockgating_state = gfx_v9_0_get_clockgating_state, +}; + +static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, + .get_rptr = gfx_v9_0_ring_get_rptr_gfx, + .get_wptr = gfx_v9_0_ring_get_wptr_gfx, + .set_wptr = gfx_v9_0_ring_set_wptr_gfx, + .emit_frame_size = /* totally 242 maximum if 16 IBs */ + 5 + /* COND_EXEC */ + 7 + /* PIPELINE_SYNC */ + 46 + /* VM_FLUSH */ + 8 + /* FENCE for VM_FLUSH */ + 20 + /* GDS switch */ + 4 + /* double SWITCH_BUFFER, + the first COND_EXEC jump to the place just + prior to this double SWITCH_BUFFER */ + 5 + /* COND_EXEC */ + 7 + /* HDP_flush */ + 4 + /* VGT_flush */ + 14 + /* CE_META */ + 31 + /* DE_META */ + 3 + /* CNTX_CTRL */ + 5 + /* HDP_INVL */ + 8 + 8 + /* FENCE x2 */ + 2, /* SWITCH_BUFFER */ + .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ + .emit_ib = gfx_v9_0_ring_emit_ib_gfx, + .emit_fence = gfx_v9_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, + .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, + .emit_switch_buffer = gfx_v9_ring_emit_sb, + .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, + .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, + .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, +}; + +static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, + .get_rptr = gfx_v9_0_ring_get_rptr_compute, + .get_wptr = gfx_v9_0_ring_get_wptr_compute, + .set_wptr = gfx_v9_0_ring_set_wptr_compute, + .emit_frame_size = + 20 + /* gfx_v9_0_ring_emit_gds_switch */ + 7 + /* gfx_v9_0_ring_emit_hdp_flush */ + 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + 64 + /* gfx_v9_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ + .emit_ib = gfx_v9_0_ring_emit_ib_compute, + .emit_fence = gfx_v9_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, + .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, +}; + +static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { + .type = AMDGPU_RING_TYPE_KIQ, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, + .get_rptr = gfx_v9_0_ring_get_rptr_compute, + .get_wptr = gfx_v9_0_ring_get_wptr_compute, + .set_wptr = gfx_v9_0_ring_set_wptr_compute, + .emit_frame_size = + 20 + /* gfx_v9_0_ring_emit_gds_switch */ + 7 + /* gfx_v9_0_ring_emit_hdp_flush */ + 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + 64 + /* gfx_v9_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ + .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ + .emit_ib = gfx_v9_0_ring_emit_ib_compute, + .emit_fence = gfx_v9_0_ring_emit_fence_kiq, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, + .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, + .emit_rreg = gfx_v9_0_ring_emit_rreg, + .emit_wreg = gfx_v9_0_ring_emit_wreg, +}; + +static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; +} + +static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = { + .set = gfx_v9_0_kiq_set_interrupt_state, + .process = gfx_v9_0_kiq_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { + .set = gfx_v9_0_set_eop_interrupt_state, + .process = gfx_v9_0_eop_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { + .set = gfx_v9_0_set_priv_reg_fault_state, + .process = gfx_v9_0_priv_reg_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { + .set = gfx_v9_0_set_priv_inst_fault_state, + .process = gfx_v9_0_priv_inst_irq, +}; + +static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; + adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; + + adev->gfx.priv_reg_irq.num_types = 1; + adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; + + adev->gfx.priv_inst_irq.num_types = 1; + adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; + + adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; + adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; +} + +static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_VEGA10: + adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; + break; + default: + break; + } +} + +static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) +{ + /* init asci gds info */ + adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE)); + adev->gds.gws.total_size = 64; + adev->gds.oa.total_size = 16; + + if (adev->gds.mem.total_size == 64 * 1024) { + adev->gds.mem.gfx_partition_size = 4096; + adev->gds.mem.cs_partition_size = 4096; + + adev->gds.gws.gfx_partition_size = 4; + adev->gds.gws.cs_partition_size = 4; + + adev->gds.oa.gfx_partition_size = 4; + adev->gds.oa.cs_partition_size = 1; + } else { + adev->gds.mem.gfx_partition_size = 1024; + adev->gds.mem.cs_partition_size = 1024; + + adev->gds.gws.gfx_partition_size = 16; + adev->gds.gws.cs_partition_size = 16; + + adev->gds.oa.gfx_partition_size = 4; + adev->gds.oa.cs_partition_size = 4; + } +} + +static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) +{ + u32 data, mask; + + data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG)); + data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG)); + + data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; + data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; + + mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh); + + return (~data) & mask; +} + +static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, + struct amdgpu_cu_info *cu_info) +{ + int i, j, k, counter, active_cu_number = 0; + u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; + + if (!adev || !cu_info) + return -EINVAL; + + memset(cu_info, 0, sizeof(*cu_info)); + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + mask = 1; + ao_bitmap = 0; + counter = 0; + gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); + bitmap = gfx_v9_0_get_cu_active_bitmap(adev); + cu_info->bitmap[i][j] = bitmap; + + for (k = 0; k < 16; k ++) { + if (bitmap & mask) { + if (counter < 2) + ao_bitmap |= mask; + counter ++; + } + mask <<= 1; + } + active_cu_number += counter; + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + } + } + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + cu_info->number = active_cu_number; + cu_info->ao_cu_mask = ao_cu_mask; + + return 0; +} + +static int gfx_v9_0_init_queue(struct amdgpu_ring *ring) +{ + int r, j; + u32 tmp; + bool use_doorbell = true; + u64 hqd_gpu_addr; + u64 mqd_gpu_addr; + u64 eop_gpu_addr; + u64 wb_gpu_addr; + u32 *buf; + struct v9_mqd *mqd; + struct amdgpu_device *adev; + + adev = ring->adev; + if (ring->mqd_obj == NULL) { + r = amdgpu_bo_create(adev, + sizeof(struct v9_mqd), + PAGE_SIZE,true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, + NULL, &ring->mqd_obj); + if (r) { + dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + gfx_v9_0_cp_compute_fini(adev); + return r; + } + + r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, + &mqd_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); + gfx_v9_0_cp_compute_fini(adev); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); + if (r) { + dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); + gfx_v9_0_cp_compute_fini(adev); + return r; + } + + /* init the mqd struct */ + memset(buf, 0, sizeof(struct v9_mqd)); + + mqd = (struct v9_mqd *)buf; + mqd->header = 0xC0310800; + mqd->compute_pipelinestat_enable = 0x00000001; + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; + mqd->compute_misc_reserved = 0x00000003; + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, + ring->pipe, + ring->queue, 0); + /* disable wptr polling */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL)); + tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp); + + /* write the EOP addr */ + BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */ + eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE); + eop_gpu_addr >>= 8; + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr)); + mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr); + mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, + (order_base_2(MEC_HPD_SIZE / 4) - 1)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp); + + /* enable doorbell? */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); + if (use_doorbell) + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + else + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp); + mqd->cp_hqd_pq_doorbell_control = tmp; + + /* disable the queue if it's active */ + ring->wptr = 0; + mqd->cp_hqd_dequeue_request = 0; + mqd->cp_hqd_pq_rptr = 0; + mqd->cp_hqd_pq_wptr_lo = 0; + mqd->cp_hqd_pq_wptr_hi = 0; + if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1); + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1)) + break; + udelay(1); + } + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi); + } + + /* set the pointer to the MQD */ + mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi); + + /* set MQD vmid to 0 */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp); + mqd->cp_mqd_control = tmp; + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = ring->gpu_addr >> 8; + mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, + (order_base_2(ring->ring_size / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, + ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); +#ifdef __BIG_ENDIAN + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); +#endif + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp); + mqd->cp_hqd_pq_control = tmp; + + /* set the wb address wether it's enabled or not */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR), + mqd->cp_hqd_pq_rptr_report_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI), + mqd->cp_hqd_pq_rptr_report_addr_hi); + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), + mqd->cp_hqd_pq_wptr_poll_addr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), + mqd->cp_hqd_pq_wptr_poll_addr_hi); + + /* enable the doorbell if requested */ + if (use_doorbell) { + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER), + (AMDGPU_DOORBELL64_KIQ * 2) << 2); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER), + (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2); + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); + mqd->cp_hqd_pq_doorbell_control = tmp; + + } else { + mqd->cp_hqd_pq_doorbell_control = 0; + } + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), + mqd->cp_hqd_pq_doorbell_control); + + /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi); + + /* set the vmid for the queue */ + mqd->cp_hqd_vmid = 0; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid); + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp); + mqd->cp_hqd_persistent_state = tmp; + + /* activate the queue */ + mqd->cp_hqd_active = 1; + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active); + + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + amdgpu_bo_kunmap(ring->mqd_obj); + amdgpu_bo_unreserve(ring->mqd_obj); + + if (use_doorbell) { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS)); + tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp); + } + + return 0; +} + +const struct amdgpu_ip_block_version gfx_v9_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 9, + .minor = 0, + .rev = 0, + .funcs = &gfx_v9_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h new file mode 100644 index 000000000000..56ef652a575d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFX_V9_0_H__ +#define __GFX_V9_0_H__ + +extern const struct amd_ip_funcs gfx_v9_0_ip_funcs; +extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block; + +void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); + +uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); +int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c new file mode 100644 index 000000000000..30ef3126c8a9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -0,0 +1,458 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "gfxhub_v1_0.h" + +#include "vega10/soc15ip.h" +#include "vega10/GC/gc_9_0_offset.h" +#include "vega10/GC/gc_9_0_sh_mask.h" +#include "vega10/GC/gc_9_0_default.h" +#include "vega10/vega10_enum.h" + +#include "soc15_common.h" + +int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) +{ + u32 tmp; + u64 value; + u32 i; + + /* Program MC. */ + /* Update configuration */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), + adev->mc.vram_start >> 18); + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR), + adev->mc.vram_end >> 18); + + value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32(SOC15_REG_OFFSET(GC, 0, + mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB), + (u32)(value >> 12)); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB), + (u32)(value >> 44)); + + if (amdgpu_sriov_vf(adev)) { + /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so + vbios post doesn't program them, for SRIOV driver need to program them */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE), + adev->mc.vram_start >> 24); + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP), + adev->mc.vram_end >> 24); + } + + /* Disable AGP. */ + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF); + + /* GART Enable. */ + + /* Setup TLB control */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + SYSTEM_ACCESS_MODE, + 3); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, + 1); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, + 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ECO_BITS, + 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + MTYPE, + MTYPE_UC);/* XXX for emulation. */ + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ATC_EN, + 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + + /* Setup L2 cache */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + ENABLE_L2_FRAGMENT_PROCESSING, + 0); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + L2_PDE0_CACHE_TAG_GENERATION_MODE, + 0);/* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + CONTEXT1_IDENTITY_ACCESS_MODE, + 1); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + IDENTITY_MODE_FRAGMENT_SIZE, + 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2)); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp); + + tmp = mmVM_L2_CNTL3_DEFAULT; + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4)); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, + 0); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, + 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp); + + /* setup context0 */ + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32), + (u32)(adev->mc.gtt_start >> 12)); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32), + (u32)(adev->mc.gtt_start >> 44)); + + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32), + (u32)(adev->mc.gtt_end >> 12)); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32), + (u32)(adev->mc.gtt_end >> 44)); + + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); + value = adev->gart.table_addr - adev->mc.vram_start + + adev->vm_manager.vram_base_offset; + value &= 0x0000FFFFFFFFF000ULL; + value |= 0x1; /*valid bit*/ + + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32), + (u32)value); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32), + (u32)(value >> 32)); + + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), + (u32)(adev->dummy_page.addr >> 12)); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32), + (u32)((u64)adev->dummy_page.addr >> 44)); + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2)); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, + 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp); + + /* Disable identity aperture.*/ + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); + + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); + + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); + + for (i = 0; i <= 14; i++) { + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, + adev->vm_manager.num_level); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PAGE_TABLE_BLOCK_SIZE, + amdgpu_vm_block_size - 9); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2, + lower_32_bits(adev->vm_manager.max_pfn - 1)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, + upper_32_bits(adev->vm_manager.max_pfn - 1)); + } + + + return 0; +} + +void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) +{ + u32 tmp; + u32 i; + + /* Disable all tables */ + for (i = 0; i < 16; i++) + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0); + + /* Setup TLB control */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, + 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + + /* Setup L2 cache */ + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0); +} + +/** + * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value) +{ + u32 tmp; + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + VM_L2_PROTECTION_FAULT_CNTL, + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, + value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp); +} + +static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id) +{ + u32 req = 0; + + /* invalidate using legacy mode on vm_id*/ + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vm_id); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static uint32_t gfxhub_v1_0_get_vm_protection_bits(void) +{ + return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); +} + +static int gfxhub_v1_0_early_init(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_late_init(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_sw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); + hub->ctx0_ptb_addr_hi32 = + SOC15_REG_OFFSET(GC, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); + hub->vm_inv_eng0_req = + SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); + hub->vm_inv_eng0_ack = + SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); + hub->vm_context0_cntl = + SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); + hub->vm_l2_pro_fault_status = + SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); + hub->vm_l2_pro_fault_cntl = + SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); + + hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req; + hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits; + + return 0; +} + +static int gfxhub_v1_0_sw_fini(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_hw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + unsigned i; + + for (i = 0 ; i < 18; ++i) { + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) + + 2 * i, 0xffffffff); + WREG32(SOC15_REG_OFFSET(GC, 0, + mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) + + 2 * i, 0x1f); + } + + return 0; +} + +static int gfxhub_v1_0_hw_fini(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_suspend(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_resume(void *handle) +{ + return 0; +} + +static bool gfxhub_v1_0_is_idle(void *handle) +{ + return true; +} + +static int gfxhub_v1_0_wait_for_idle(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_soft_reset(void *handle) +{ + return 0; +} + +static int gfxhub_v1_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + return 0; +} + +static int gfxhub_v1_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = { + .name = "gfxhub_v1_0", + .early_init = gfxhub_v1_0_early_init, + .late_init = gfxhub_v1_0_late_init, + .sw_init = gfxhub_v1_0_sw_init, + .sw_fini = gfxhub_v1_0_sw_fini, + .hw_init = gfxhub_v1_0_hw_init, + .hw_fini = gfxhub_v1_0_hw_fini, + .suspend = gfxhub_v1_0_suspend, + .resume = gfxhub_v1_0_resume, + .is_idle = gfxhub_v1_0_is_idle, + .wait_for_idle = gfxhub_v1_0_wait_for_idle, + .soft_reset = gfxhub_v1_0_soft_reset, + .set_clockgating_state = gfxhub_v1_0_set_clockgating_state, + .set_powergating_state = gfxhub_v1_0_set_powergating_state, +}; + +const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFXHUB, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &gfxhub_v1_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h new file mode 100644 index 000000000000..5129a8ff0932 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFXHUB_V1_0_H__ +#define __GFXHUB_V1_0_H__ + +int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev); +void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev); +void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value); + +extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs; +extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 0635829b18cf..d9586601a437 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -367,7 +367,7 @@ static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, uint32_t gpu_page_idx, uint64_t addr, - uint32_t flags) + uint64_t flags) { void __iomem *ptr = (void *)cpu_pt_addr; uint64_t value; @@ -379,6 +379,21 @@ static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, return 0; } +static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, + uint32_t flags) +{ + uint64_t pte_flag = 0; + + if (flags & AMDGPU_VM_PAGE_READABLE) + pte_flag |= AMDGPU_PTE_READABLE; + if (flags & AMDGPU_VM_PAGE_WRITEABLE) + pte_flag |= AMDGPU_PTE_WRITEABLE; + if (flags & AMDGPU_VM_PAGE_PRT) + pte_flag |= AMDGPU_PTE_PRT; + + return pte_flag; +} + static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) { @@ -400,6 +415,60 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, WREG32(mmVM_CONTEXT1_CNTL, tmp); } + /** + + * gmc_v8_0_set_prt - set PRT VM fault + + * + + * @adev: amdgpu_device pointer + + * @enable: enable/disable VM fault handling for PRT + +*/ +static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) +{ + u32 tmp; + + if (enable && !adev->mc.prt_warning) { + dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); + adev->mc.prt_warning = true; + } + + tmp = RREG32(mmVM_PRT_CNTL); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, + enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, + enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + L2_CACHE_STORE_INVALID_ENTRIES, + enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + L1_TLB_STORE_INVALID_ENTRIES, + enable); + WREG32(mmVM_PRT_CNTL, tmp); + + if (enable) { + uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; + uint32_t high = adev->vm_manager.max_pfn; + + WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); + } else { + WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); + } +} + static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) { int r, i; @@ -500,6 +569,7 @@ static int gmc_v6_0_gart_init(struct amdgpu_device *adev) if (r) return r; adev->gart.table_size = adev->gart.num_gpu_pages * 8; + adev->gart.gart_pte_flags = 0; return amdgpu_gart_table_vram_alloc(adev); } @@ -551,6 +621,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ @@ -769,11 +840,11 @@ static int gmc_v6_0_sw_init(void *handle) int dma_bits; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); if (r) return r; - r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); if (r) return r; @@ -1039,7 +1110,7 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, if (printk_ratelimit()) { dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); + entry->src_id, entry->src_data[0]); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", addr); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", @@ -1082,6 +1153,8 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = { .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v6_0_gart_set_pte_pde, + .set_prt = gmc_v6_0_set_prt, + .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags }; static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 8d05e0c4e3d7..0c0a6015cca5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -161,9 +161,7 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - printk(KERN_ERR - "cik_mc: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); release_firmware(adev->mc.fw); adev->mc.fw = NULL; } @@ -441,7 +439,7 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, uint32_t gpu_page_idx, uint64_t addr, - uint32_t flags) + uint64_t flags) { void __iomem *ptr = (void *)cpu_pt_addr; uint64_t value; @@ -453,6 +451,21 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, return 0; } +static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, + uint32_t flags) +{ + uint64_t pte_flag = 0; + + if (flags & AMDGPU_VM_PAGE_READABLE) + pte_flag |= AMDGPU_PTE_READABLE; + if (flags & AMDGPU_VM_PAGE_WRITEABLE) + pte_flag |= AMDGPU_PTE_WRITEABLE; + if (flags & AMDGPU_VM_PAGE_PRT) + pte_flag |= AMDGPU_PTE_PRT; + + return pte_flag; +} + /** * gmc_v8_0_set_fault_enable_default - update VM fault handling * @@ -481,6 +494,62 @@ static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, } /** + * gmc_v7_0_set_prt - set PRT VM fault + * + * @adev: amdgpu_device pointer + * @enable: enable/disable VM fault handling for PRT + */ +static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) +{ + uint32_t tmp; + + if (enable && !adev->mc.prt_warning) { + dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); + adev->mc.prt_warning = true; + } + + tmp = RREG32(mmVM_PRT_CNTL); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + L2_CACHE_STORE_INVALID_ENTRIES, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + L1_TLB_STORE_INVALID_ENTRIES, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + MASK_PDE0_FAULT, enable); + WREG32(mmVM_PRT_CNTL, tmp); + + if (enable) { + uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; + uint32_t high = adev->vm_manager.max_pfn; + + WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); + } else { + WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); + } +} + +/** * gmc_v7_0_gart_enable - gart enable * * @adev: amdgpu_device pointer @@ -604,6 +673,7 @@ static int gmc_v7_0_gart_init(struct amdgpu_device *adev) if (r) return r; adev->gart.table_size = adev->gart.num_gpu_pages * 8; + adev->gart.gart_pte_flags = 0; return amdgpu_gart_table_vram_alloc(adev); } @@ -672,6 +742,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ @@ -880,6 +951,14 @@ static int gmc_v7_0_early_init(void *handle) gmc_v7_0_set_gart_funcs(adev); gmc_v7_0_set_irq_funcs(adev); + adev->mc.shared_aperture_start = 0x2000000000000000ULL; + adev->mc.shared_aperture_end = + adev->mc.shared_aperture_start + (4ULL << 30) - 1; + adev->mc.private_aperture_start = + adev->mc.shared_aperture_end + 1; + adev->mc.private_aperture_end = + adev->mc.private_aperture_start + (4ULL << 30) - 1; + return 0; } @@ -907,11 +986,11 @@ static int gmc_v7_0_sw_init(void *handle) adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); } - r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); if (r) return r; - r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); if (r) return r; @@ -938,12 +1017,12 @@ static int gmc_v7_0_sw_init(void *handle) if (r) { adev->need_dma32 = true; dma_bits = 32; - printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); + pr_warn("amdgpu: No suitable DMA available\n"); } r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); if (r) { pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); - printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); + pr_warn("amdgpu: No coherent DMA available\n"); } r = gmc_v7_0_init_microcode(adev); @@ -1202,7 +1281,7 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (printk_ratelimit()) { dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); + entry->src_id, entry->src_data[0]); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", addr); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", @@ -1259,6 +1338,8 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = { .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v7_0_gart_set_pte_pde, + .set_prt = gmc_v7_0_set_prt, + .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags }; static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 7669b3259f35..d19d1c5e2847 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -245,9 +245,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - printk(KERN_ERR - "mc: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); release_firmware(adev->mc.fw); adev->mc.fw = NULL; } @@ -255,14 +253,14 @@ out: } /** - * gmc_v8_0_mc_load_microcode - load MC ucode into the hw + * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw * * @adev: amdgpu_device pointer * * Load the GDDR MC ucode into the hw (CIK). * Returns 0 on success, error on failure. */ -static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) +static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) { const struct mc_firmware_header_v1_0 *hdr; const __le32 *fw_data = NULL; @@ -270,9 +268,6 @@ static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) u32 running; int i, ucode_size, regs_size; - if (!adev->mc.fw) - return -EINVAL; - /* Skip MC ucode loading on SR-IOV capable boards. * vbios does this for us in asic_init in that case. * Skip MC ucode loading on VF, because hypervisor will do that @@ -281,6 +276,9 @@ static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) if (amdgpu_sriov_bios(adev)) return 0; + if (!adev->mc.fw) + return -EINVAL; + hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; amdgpu_ucode_print_mc_hdr(&hdr->header); @@ -331,6 +329,76 @@ static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) return 0; } +static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) +{ + const struct mc_firmware_header_v1_0 *hdr; + const __le32 *fw_data = NULL; + const __le32 *io_mc_regs = NULL; + u32 data, vbios_version; + int i, ucode_size, regs_size; + + /* Skip MC ucode loading on SR-IOV capable boards. + * vbios does this for us in asic_init in that case. + * Skip MC ucode loading on VF, because hypervisor will do that + * for this adaptor. + */ + if (amdgpu_sriov_bios(adev)) + return 0; + + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); + data = RREG32(mmMC_SEQ_IO_DEBUG_DATA); + vbios_version = data & 0xf; + + if (vbios_version == 0) + return 0; + + if (!adev->mc.fw) + return -EINVAL; + + hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; + amdgpu_ucode_print_mc_hdr(&hdr->header); + + adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + io_mc_regs = (const __le32 *) + (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) + (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + data = RREG32(mmMC_SEQ_MISC0); + data &= ~(0x40); + WREG32(mmMC_SEQ_MISC0, data); + + /* load mc io regs */ + for (i = 0; i < regs_size; i++) { + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); + } + + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); + + /* load the MC ucode */ + for (i = 0; i < ucode_size; i++) + WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); + + /* put the engine back into the active state */ + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); + + /* wait for training to complete */ + for (i = 0; i < adev->usec_timeout; i++) { + data = RREG32(mmMC_SEQ_MISC0); + if (data & 0x80) + break; + udelay(1); + } + + return 0; +} + static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) { @@ -533,7 +601,7 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, uint32_t gpu_page_idx, uint64_t addr, - uint32_t flags) + uint64_t flags) { void __iomem *ptr = (void *)cpu_pt_addr; uint64_t value; @@ -565,6 +633,23 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, return 0; } +static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, + uint32_t flags) +{ + uint64_t pte_flag = 0; + + if (flags & AMDGPU_VM_PAGE_EXECUTABLE) + pte_flag |= AMDGPU_PTE_EXECUTABLE; + if (flags & AMDGPU_VM_PAGE_READABLE) + pte_flag |= AMDGPU_PTE_READABLE; + if (flags & AMDGPU_VM_PAGE_WRITEABLE) + pte_flag |= AMDGPU_PTE_WRITEABLE; + if (flags & AMDGPU_VM_PAGE_PRT) + pte_flag |= AMDGPU_PTE_PRT; + + return pte_flag; +} + /** * gmc_v8_0_set_fault_enable_default - update VM fault handling * @@ -595,6 +680,62 @@ static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, } /** + * gmc_v8_0_set_prt - set PRT VM fault + * + * @adev: amdgpu_device pointer + * @enable: enable/disable VM fault handling for PRT +*/ +static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) +{ + u32 tmp; + + if (enable && !adev->mc.prt_warning) { + dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); + adev->mc.prt_warning = true; + } + + tmp = RREG32(mmVM_PRT_CNTL); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + L2_CACHE_STORE_INVALID_ENTRIES, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + L1_TLB_STORE_INVALID_ENTRIES, enable); + tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, + MASK_PDE0_FAULT, enable); + WREG32(mmVM_PRT_CNTL, tmp); + + if (enable) { + uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; + uint32_t high = adev->vm_manager.max_pfn; + + WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); + WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); + WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); + } else { + WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); + WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); + WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); + } +} + +/** * gmc_v8_0_gart_enable - gart enable * * @adev: amdgpu_device pointer @@ -735,6 +876,7 @@ static int gmc_v8_0_gart_init(struct amdgpu_device *adev) if (r) return r; adev->gart.table_size = adev->gart.num_gpu_pages * 8; + adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; return amdgpu_gart_table_vram_alloc(adev); } @@ -803,6 +945,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ @@ -885,6 +1028,14 @@ static int gmc_v8_0_early_init(void *handle) gmc_v8_0_set_gart_funcs(adev); gmc_v8_0_set_irq_funcs(adev); + adev->mc.shared_aperture_start = 0x2000000000000000ULL; + adev->mc.shared_aperture_end = + adev->mc.shared_aperture_start + (4ULL << 30) - 1; + adev->mc.private_aperture_start = + adev->mc.shared_aperture_end + 1; + adev->mc.private_aperture_end = + adev->mc.private_aperture_start + (4ULL << 30) - 1; + return 0; } @@ -919,11 +1070,11 @@ static int gmc_v8_0_sw_init(void *handle) adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); } - r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); if (r) return r; - r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); if (r) return r; @@ -950,12 +1101,12 @@ static int gmc_v8_0_sw_init(void *handle) if (r) { adev->need_dma32 = true; dma_bits = 32; - printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); + pr_warn("amdgpu: No suitable DMA available\n"); } r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); if (r) { pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); - printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); + pr_warn("amdgpu: No coherent DMA available\n"); } r = gmc_v8_0_init_microcode(adev); @@ -1015,7 +1166,15 @@ static int gmc_v8_0_hw_init(void *handle) gmc_v8_0_mc_program(adev); if (adev->asic_type == CHIP_TONGA) { - r = gmc_v8_0_mc_load_microcode(adev); + r = gmc_v8_0_tonga_mc_load_microcode(adev); + if (r) { + DRM_ERROR("Failed to load MC firmware!\n"); + return r; + } + } else if (adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10 || + adev->asic_type == CHIP_POLARIS12) { + r = gmc_v8_0_polaris_mc_load_microcode(adev); if (r) { DRM_ERROR("Failed to load MC firmware!\n"); return r; @@ -1237,6 +1396,13 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, { u32 addr, status, mc_client; + if (amdgpu_sriov_vf(adev)) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data[0]); + dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); + return 0; + } + addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); @@ -1251,7 +1417,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (printk_ratelimit()) { dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); + entry->src_id, entry->src_data[0]); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", addr); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", @@ -1427,12 +1593,15 @@ static int gmc_v8_0_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (amdgpu_sriov_vf(adev)) + return 0; + switch (adev->asic_type) { case CHIP_FIJI: fiji_update_mc_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); fiji_update_mc_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; default: break; @@ -1451,6 +1620,9 @@ static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int data; + if (amdgpu_sriov_vf(adev)) + *flags = 0; + /* AMD_CG_SUPPORT_MC_MGCG */ data = RREG32(mmMC_HUB_MISC_HUB_CG); if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) @@ -1485,6 +1657,8 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, .set_pte_pde = gmc_v8_0_gart_set_pte_pde, + .set_prt = gmc_v8_0_set_prt, + .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags }; static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c new file mode 100644 index 000000000000..df69aae99df4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -0,0 +1,842 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include <linux/firmware.h> +#include "amdgpu.h" +#include "gmc_v9_0.h" + +#include "vega10/soc15ip.h" +#include "vega10/HDP/hdp_4_0_offset.h" +#include "vega10/HDP/hdp_4_0_sh_mask.h" +#include "vega10/GC/gc_9_0_sh_mask.h" +#include "vega10/vega10_enum.h" + +#include "soc15_common.h" + +#include "nbio_v6_1.h" +#include "gfxhub_v1_0.h" +#include "mmhub_v1_0.h" + +#define mmDF_CS_AON0_DramBaseAddress0 0x0044 +#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 +//DF_CS_AON0_DramBaseAddress0 +#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 +#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 +#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 +#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 +#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc +#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L +#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L +#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L +#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L +#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L + +/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ +#define AMDGPU_NUM_OF_VMIDS 8 + +static const u32 golden_settings_vega10_hdp[] = +{ + 0xf64, 0x0fffffff, 0x00000000, + 0xf65, 0x0fffffff, 0x00000000, + 0xf66, 0x0fffffff, 0x00000000, + 0xf67, 0x0fffffff, 0x00000000, + 0xf68, 0x0fffffff, 0x00000000, + 0xf6a, 0x0fffffff, 0x00000000, + 0xf6b, 0x0fffffff, 0x00000000, + 0xf6c, 0x0fffffff, 0x00000000, + 0xf6d, 0x0fffffff, 0x00000000, + 0xf6e, 0x0fffffff, 0x00000000, +}; + +static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + struct amdgpu_vmhub *hub; + u32 tmp, reg, bits, i; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* MM HUB */ + hub = &adev->vmhub[AMDGPU_MMHUB]; + bits = hub->get_vm_protection_bits(); + for (i = 0; i< 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); + tmp &= ~bits; + WREG32(reg, tmp); + } + + /* GFX HUB */ + hub = &adev->vmhub[AMDGPU_GFXHUB]; + bits = hub->get_vm_protection_bits(); + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); + tmp &= ~bits; + WREG32(reg, tmp); + } + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* MM HUB */ + hub = &adev->vmhub[AMDGPU_MMHUB]; + bits = hub->get_vm_protection_bits(); + for (i = 0; i< 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); + tmp |= bits; + WREG32(reg, tmp); + } + + /* GFX HUB */ + hub = &adev->vmhub[AMDGPU_GFXHUB]; + bits = hub->get_vm_protection_bits(); + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); + tmp |= bits; + WREG32(reg, tmp); + } + break; + default: + break; + } + + return 0; +} + +static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB]; + struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB]; + uint32_t status = 0; + u64 addr; + + addr = (u64)entry->src_data[0] << 12; + addr |= ((u64)entry->src_data[1] & 0xf) << 44; + + if (!amdgpu_sriov_vf(adev)) { + if (entry->vm_id_src) { + status = RREG32(mmhub->vm_l2_pro_fault_status); + WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1); + } else { + status = RREG32(gfxhub->vm_l2_pro_fault_status); + WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1); + } + } + + if (printk_ratelimit()) { + dev_err(adev->dev, + "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n", + entry->vm_id_src ? "mmhub" : "gfxhub", + entry->src_id, entry->ring_id, entry->vm_id, + entry->pas_id); + dev_err(adev->dev, " at page 0x%016llx from %d\n", + addr, entry->client_id); + if (!amdgpu_sriov_vf(adev)) + dev_err(adev->dev, + "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", + status); + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { + .set = gmc_v9_0_vm_fault_interrupt_state, + .process = gmc_v9_0_process_interrupt, +}; + +static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->mc.vm_fault.num_types = 1; + adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; +} + +/* + * GART + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ + +/** + * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * + * Flush the TLB for the requested page table. + */ +static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) +{ + /* Use register 17 for GART */ + const unsigned eng = 17; + unsigned i, j; + + /* flush hdp cache */ + nbio_v6_1_hdp_flush(adev); + + spin_lock(&adev->mc.invalidate_lock); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &adev->vmhub[i]; + u32 tmp = hub->get_invalidate_req(vmid); + + WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); + + /* Busy wait for ACK.*/ + for (j = 0; j < 100; j++) { + tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); + tmp &= 1 << vmid; + if (tmp) + break; + cpu_relax(); + } + if (j < 100) + continue; + + /* Wait for ACK with a delay.*/ + for (j = 0; j < adev->usec_timeout; j++) { + tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); + tmp &= 1 << vmid; + if (tmp) + break; + udelay(1); + } + if (j < adev->usec_timeout) + continue; + + DRM_ERROR("Timeout waiting for VM flush ACK!\n"); + } + + spin_unlock(&adev->mc.invalidate_lock); +} + +/** + * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO + * + * @adev: amdgpu_device pointer + * @cpu_pt_addr: cpu address of the page table + * @gpu_page_idx: entry in the page table to update + * @addr: dst addr to write into pte/pde + * @flags: access flags + * + * Update the page tables using the CPU. + */ +static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev, + void *cpu_pt_addr, + uint32_t gpu_page_idx, + uint64_t addr, + uint64_t flags) +{ + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; + + /* + * PTE format on VEGA 10: + * 63:59 reserved + * 58:57 mtype + * 56 F + * 55 L + * 54 P + * 53 SW + * 52 T + * 50:48 reserved + * 47:12 4k physical page base address + * 11:7 fragment + * 6 write + * 5 read + * 4 exe + * 3 Z + * 2 snooped + * 1 system + * 0 valid + * + * PDE format on VEGA 10: + * 63:59 block fragment size + * 58:55 reserved + * 54 P + * 53:48 reserved + * 47:6 physical base address of PD or PTE + * 5:3 reserved + * 2 C + * 1 system + * 0 valid + */ + + /* + * The following is for PTE only. GART does not have PDEs. + */ + value = addr & 0x0000FFFFFFFFF000ULL; + value |= flags; + writeq(value, ptr + (gpu_page_idx * 8)); + return 0; +} + +static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, + uint32_t flags) + +{ + uint64_t pte_flag = 0; + + if (flags & AMDGPU_VM_PAGE_EXECUTABLE) + pte_flag |= AMDGPU_PTE_EXECUTABLE; + if (flags & AMDGPU_VM_PAGE_READABLE) + pte_flag |= AMDGPU_PTE_READABLE; + if (flags & AMDGPU_VM_PAGE_WRITEABLE) + pte_flag |= AMDGPU_PTE_WRITEABLE; + + switch (flags & AMDGPU_VM_MTYPE_MASK) { + case AMDGPU_VM_MTYPE_DEFAULT: + pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_NC: + pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_WC: + pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); + break; + case AMDGPU_VM_MTYPE_CC: + pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); + break; + case AMDGPU_VM_MTYPE_UC: + pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); + break; + default: + pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); + break; + } + + if (flags & AMDGPU_VM_PAGE_PRT) + pte_flag |= AMDGPU_PTE_PRT; + + return pte_flag; +} + +static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { + .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, + .set_pte_pde = gmc_v9_0_gart_set_pte_pde, + .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags +}; + +static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) +{ + if (adev->gart.gart_funcs == NULL) + adev->gart.gart_funcs = &gmc_v9_0_gart_funcs; +} + +static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) +{ + return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start; +} + +static const struct amdgpu_mc_funcs gmc_v9_0_mc_funcs = { + .adjust_mc_addr = gmc_v9_0_adjust_mc_addr, +}; + +static void gmc_v9_0_set_mc_funcs(struct amdgpu_device *adev) +{ + adev->mc.mc_funcs = &gmc_v9_0_mc_funcs; +} + +static int gmc_v9_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + gmc_v9_0_set_gart_funcs(adev); + gmc_v9_0_set_mc_funcs(adev); + gmc_v9_0_set_irq_funcs(adev); + + return 0; +} + +static int gmc_v9_0_late_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); +} + +static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc) +{ + u64 base = 0; + if (!amdgpu_sriov_vf(adev)) + base = mmhub_v1_0_get_fb_location(adev); + amdgpu_vram_location(adev, &adev->mc, base); + adev->mc.gtt_base_align = 0; + amdgpu_gtt_location(adev, mc); +} + +/** + * gmc_v9_0_mc_init - initialize the memory controller driver params + * + * @adev: amdgpu_device pointer + * + * Look up the amount of vram, vram width, and decide how to place + * vram and gart within the GPU's physical address space. + * Returns 0 for success. + */ +static int gmc_v9_0_mc_init(struct amdgpu_device *adev) +{ + u32 tmp; + int chansize, numchan; + + /* hbm memory channel size */ + chansize = 128; + + tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); + tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; + tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; + switch (tmp) { + case 0: + default: + numchan = 1; + break; + case 1: + numchan = 2; + break; + case 2: + numchan = 0; + break; + case 3: + numchan = 4; + break; + case 4: + numchan = 0; + break; + case 5: + numchan = 8; + break; + case 6: + numchan = 0; + break; + case 7: + numchan = 16; + break; + case 8: + numchan = 2; + break; + } + adev->mc.vram_width = numchan * chansize; + + /* Could aper size report 0 ? */ + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + /* size in MB on si */ + adev->mc.mc_vram_size = + nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL; + adev->mc.real_vram_size = adev->mc.mc_vram_size; + adev->mc.visible_vram_size = adev->mc.aper_size; + + /* In case the PCI BAR is larger than the actual amount of vram */ + if (adev->mc.visible_vram_size > adev->mc.real_vram_size) + adev->mc.visible_vram_size = adev->mc.real_vram_size; + + /* unless the user had overridden it, set the gart + * size equal to the 1024 or vram, whichever is larger. + */ + if (amdgpu_gart_size == -1) + adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); + else + adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; + + gmc_v9_0_vram_gtt_location(adev, &adev->mc); + + return 0; +} + +static int gmc_v9_0_gart_init(struct amdgpu_device *adev) +{ + int r; + + if (adev->gart.robj) { + WARN(1, "VEGA10 PCIE GART already initialized\n"); + return 0; + } + /* Initialize common gart structure */ + r = amdgpu_gart_init(adev); + if (r) + return r; + adev->gart.table_size = adev->gart.num_gpu_pages * 8; + adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | + AMDGPU_PTE_EXECUTABLE; + return amdgpu_gart_table_vram_alloc(adev); +} + +/* + * vm + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ +/** + * gmc_v9_0_vm_init - vm init callback + * + * @adev: amdgpu_device pointer + * + * Inits vega10 specific vm parameters (number of VMs, base of vram for + * VMIDs 1-15) (vega10). + * Returns 0 for success. + */ +static int gmc_v9_0_vm_init(struct amdgpu_device *adev) +{ + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; + adev->vm_manager.num_level = 3; + amdgpu_vm_manager_init(adev); + + /* base offset of vram pages */ + /*XXX This value is not zero for APU*/ + adev->vm_manager.vram_base_offset = 0; + + return 0; +} + +/** + * gmc_v9_0_vm_fini - vm fini callback + * + * @adev: amdgpu_device pointer + * + * Tear down any asic specific VM setup. + */ +static void gmc_v9_0_vm_fini(struct amdgpu_device *adev) +{ + return; +} + +static int gmc_v9_0_sw_init(void *handle) +{ + int r; + int dma_bits; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + spin_lock_init(&adev->mc.invalidate_lock); + + if (adev->flags & AMD_IS_APU) { + adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; + } else { + /* XXX Don't know how to get VRAM type yet. */ + adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; + } + + /* This interrupt is VMC page fault.*/ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, + &adev->mc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, + &adev->mc.vm_fault); + + if (r) + return r; + + /* Because of four level VMPTs, vm size is at least 512GB. + * The maximum size is 256TB (48bit). + */ + if (amdgpu_vm_size < 512) { + DRM_WARN("VM size is at least 512GB!\n"); + amdgpu_vm_size = 512; + } + adev->vm_manager.max_pfn = (uint64_t)amdgpu_vm_size << 18; + + /* Set the internal MC address mask + * This is the max address of the GPU's + * internal address space. + */ + adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ + + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 44-bits. + * IGP - can handle 44-bits + * PCI - dma32 for legacy pci gart, 44 bits on vega10 + */ + adev->need_dma32 = false; + dma_bits = adev->need_dma32 ? 32 : 44; + r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); + if (r) { + adev->need_dma32 = true; + dma_bits = 32; + printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); + } + r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); + if (r) { + pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); + printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); + } + + r = gmc_v9_0_mc_init(adev); + if (r) + return r; + + /* Memory manager */ + r = amdgpu_bo_init(adev); + if (r) + return r; + + r = gmc_v9_0_gart_init(adev); + if (r) + return r; + + if (!adev->vm_manager.enabled) { + r = gmc_v9_0_vm_init(adev); + if (r) { + dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); + return r; + } + adev->vm_manager.enabled = true; + } + return r; +} + +/** + * gmc_v8_0_gart_fini - vm fini callback + * + * @adev: amdgpu_device pointer + * + * Tears down the driver GART/VM setup (CIK). + */ +static void gmc_v9_0_gart_fini(struct amdgpu_device *adev) +{ + amdgpu_gart_table_vram_free(adev); + amdgpu_gart_fini(adev); +} + +static int gmc_v9_0_sw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->vm_manager.enabled) { + amdgpu_vm_manager_fini(adev); + gmc_v9_0_vm_fini(adev); + adev->vm_manager.enabled = false; + } + gmc_v9_0_gart_fini(adev); + amdgpu_gem_force_release(adev); + amdgpu_bo_fini(adev); + + return 0; +} + +static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_VEGA10: + break; + default: + break; + } +} + +/** + * gmc_v9_0_gart_enable - gart enable + * + * @adev: amdgpu_device pointer + */ +static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) +{ + int r; + bool value; + u32 tmp; + + amdgpu_program_register_sequence(adev, + golden_settings_vega10_hdp, + (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); + + if (adev->gart.robj == NULL) { + dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; + } + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; + + /* After HDP is initialized, flush HDP.*/ + nbio_v6_1_hdp_flush(adev); + + r = gfxhub_v1_0_gart_enable(adev); + if (r) + return r; + + r = mmhub_v1_0_gart_enable(adev); + if (r) + return r; + + tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL)); + tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; + WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL)); + WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp); + + + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) + value = false; + else + value = true; + + gfxhub_v1_0_set_fault_enable_default(adev, value); + mmhub_v1_0_set_fault_enable_default(adev, value); + + gmc_v9_0_gart_flush_gpu_tlb(adev, 0); + + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->mc.gtt_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +} + +static int gmc_v9_0_hw_init(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* The sequence of these two function calls matters.*/ + gmc_v9_0_init_golden_registers(adev); + + r = gmc_v9_0_gart_enable(adev); + + return r; +} + +/** + * gmc_v9_0_gart_disable - gart disable + * + * @adev: amdgpu_device pointer + * + * This disables all VM page table. + */ +static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) +{ + gfxhub_v1_0_gart_disable(adev); + mmhub_v1_0_gart_disable(adev); + amdgpu_gart_table_vram_unpin(adev); +} + +static int gmc_v9_0_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); + gmc_v9_0_gart_disable(adev); + + return 0; +} + +static int gmc_v9_0_suspend(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->vm_manager.enabled) { + gmc_v9_0_vm_fini(adev); + adev->vm_manager.enabled = false; + } + gmc_v9_0_hw_fini(adev); + + return 0; +} + +static int gmc_v9_0_resume(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = gmc_v9_0_hw_init(adev); + if (r) + return r; + + if (!adev->vm_manager.enabled) { + r = gmc_v9_0_vm_init(adev); + if (r) { + dev_err(adev->dev, + "vm manager initialization failed (%d).\n", r); + return r; + } + adev->vm_manager.enabled = true; + } + + return r; +} + +static bool gmc_v9_0_is_idle(void *handle) +{ + /* MC is always ready in GMC v9.*/ + return true; +} + +static int gmc_v9_0_wait_for_idle(void *handle) +{ + /* There is no need to wait for MC idle in GMC v9.*/ + return 0; +} + +static int gmc_v9_0_soft_reset(void *handle) +{ + /* XXX for emulation.*/ + return 0; +} + +static int gmc_v9_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + return 0; +} + +static int gmc_v9_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +const struct amd_ip_funcs gmc_v9_0_ip_funcs = { + .name = "gmc_v9_0", + .early_init = gmc_v9_0_early_init, + .late_init = gmc_v9_0_late_init, + .sw_init = gmc_v9_0_sw_init, + .sw_fini = gmc_v9_0_sw_fini, + .hw_init = gmc_v9_0_hw_init, + .hw_fini = gmc_v9_0_hw_fini, + .suspend = gmc_v9_0_suspend, + .resume = gmc_v9_0_resume, + .is_idle = gmc_v9_0_is_idle, + .wait_for_idle = gmc_v9_0_wait_for_idle, + .soft_reset = gmc_v9_0_soft_reset, + .set_clockgating_state = gmc_v9_0_set_clockgating_state, + .set_powergating_state = gmc_v9_0_set_powergating_state, +}; + +const struct amdgpu_ip_block_version gmc_v9_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 9, + .minor = 0, + .rev = 0, + .funcs = &gmc_v9_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h new file mode 100644 index 000000000000..b030ca5ea107 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h @@ -0,0 +1,30 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GMC_V9_0_H__ +#define __GMC_V9_0_H__ + +extern const struct amd_ip_funcs gmc_v9_0_ip_funcs; +extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index ac21bb7bc0f3..cb622add99a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -227,8 +227,9 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev, dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; entry->src_id = dw[0] & 0xff; - entry->src_data = dw[1] & 0xfffffff; + entry->src_data[0] = dw[1] & 0xfffffff; entry->ring_id = dw[2] & 0xff; entry->vm_id = (dw[2] >> 8) & 0xff; entry->pas_id = (dw[2] >> 16) & 0xffff; diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index f5a343cb0010..79a52ad2c80d 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -2981,11 +2981,13 @@ static int kv_dpm_sw_init(void *handle) int ret; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); + ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, + &adev->pm.dpm.thermal.irq); if (ret) return ret; - ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); + ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, + &adev->pm.dpm.thermal.irq); if (ret) return ret; @@ -3260,6 +3262,39 @@ static int kv_check_state_equal(struct amdgpu_device *adev, return 0; } +static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx, + void *value, int *size) +{ + struct kv_power_info *pi = kv_get_pi(adev); + uint32_t sclk; + u32 pl_index = + (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; + + /* size must be at least 4 bytes for all sensors */ + if (*size < 4) + return -EINVAL; + + switch (idx) { + case AMDGPU_PP_SENSOR_GFX_SCLK: + if (pl_index < SMU__NUM_SCLK_DPM_STATE) { + sclk = be32_to_cpu( + pi->graphics_level[pl_index].SclkFrequency); + *((uint32_t *)value) = sclk; + *size = 4; + return 0; + } + return -EINVAL; + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = kv_dpm_get_temp(adev); + *size = 4; + return 0; + default: + return -EINVAL; + } +} + const struct amd_ip_funcs kv_dpm_ip_funcs = { .name = "kv_dpm", .early_init = kv_dpm_early_init, @@ -3292,6 +3327,7 @@ static const struct amdgpu_dpm_funcs kv_dpm_funcs = { .enable_bapm = &kv_dpm_enable_bapm, .get_vce_clock_state = amdgpu_get_vce_clock_state, .check_state_equal = kv_check_state_equal, + .read_sensor = &kv_dpm_read_sensor, }; static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c new file mode 100644 index 000000000000..266a0f47a908 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -0,0 +1,615 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "mmhub_v1_0.h" + +#include "vega10/soc15ip.h" +#include "vega10/MMHUB/mmhub_1_0_offset.h" +#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "vega10/MMHUB/mmhub_1_0_default.h" +#include "vega10/ATHUB/athub_1_0_offset.h" +#include "vega10/ATHUB/athub_1_0_sh_mask.h" +#include "vega10/ATHUB/athub_1_0_default.h" +#include "vega10/vega10_enum.h" + +#include "soc15_common.h" + +u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) +{ + u64 base = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE)); + + base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; + base <<= 24; + + return base; +} + +int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) +{ + u32 tmp; + u64 value; + uint64_t addr; + u32 i; + + /* Program MC. */ + /* Update configuration */ + DRM_INFO("%s -- in\n", __func__); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), + adev->mc.vram_start >> 18); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR), + adev->mc.vram_end >> 18); + value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB), + (u32)(value >> 12)); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB), + (u32)(value >> 44)); + + if (amdgpu_sriov_vf(adev)) { + /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so + vbios post doesn't program them, for SRIOV driver need to program them */ + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE), + adev->mc.vram_start >> 24); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP), + adev->mc.vram_end >> 24); + } + + /* Disable AGP. */ + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BOT), 0x00FFFFFF); + + /* GART Enable. */ + + /* Setup TLB control */ + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + SYSTEM_ACCESS_MODE, + 3); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, + 1); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, + 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ECO_BITS, + 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + MTYPE, + MTYPE_UC);/* XXX for emulation. */ + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ATC_EN, + 1); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + + /* Setup L2 cache */ + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + ENABLE_L2_FRAGMENT_PROCESSING, + 0); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + L2_PDE0_CACHE_TAG_GENERATION_MODE, + 0);/* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + CONTEXT1_IDENTITY_ACCESS_MODE, + 1); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL, + IDENTITY_MODE_FRAGMENT_SIZE, + 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2)); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp); + + tmp = mmVM_L2_CNTL3_DEFAULT; + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4)); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, + 0); + tmp = REG_SET_FIELD(tmp, + VM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, + 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp); + + /* setup context0 */ + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32), + (u32)(adev->mc.gtt_start >> 12)); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32), + (u32)(adev->mc.gtt_start >> 44)); + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32), + (u32)(adev->mc.gtt_end >> 12)); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32), + (u32)(adev->mc.gtt_end >> 44)); + + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); + value = adev->gart.table_addr - adev->mc.vram_start + + adev->vm_manager.vram_base_offset; + value &= 0x0000FFFFFFFFF000ULL; + value |= 0x1; /* valid bit */ + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32), + (u32)value); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32), + (u32)(value >> 32)); + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), + (u32)(adev->dummy_page.addr >> 12)); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32), + (u32)((u64)adev->dummy_page.addr >> 44)); + + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2)); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, + 1); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); + + addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); + tmp = RREG32(addr); + + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp); + + tmp = RREG32(addr); + + /* Disable identity aperture.*/ + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); + + for (i = 0; i <= 14; i++) { + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) + + i); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PAGE_TABLE_DEPTH, adev->vm_manager.num_level); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PAGE_TABLE_BLOCK_SIZE, + amdgpu_vm_block_size - 9); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) + i, tmp); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2, + lower_32_bits(adev->vm_manager.max_pfn - 1)); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, + upper_32_bits(adev->vm_manager.max_pfn - 1)); + } + + return 0; +} + +void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) +{ + u32 tmp; + u32 i; + + /* Disable all tables */ + for (i = 0; i < 16; i++) + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL) + i, 0); + + /* Setup TLB control */ + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL)); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, + MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, + 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); + + /* Setup L2 cache */ + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), 0); +} + +/** + * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) +{ + u32 tmp; + tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL)); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + VM_L2_PROTECTION_FAULT_CNTL, + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, + value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp); +} + +static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vm_id) +{ + u32 req = 0; + + /* invalidate using legacy mode on vm_id*/ + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vm_id); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static uint32_t mmhub_v1_0_get_vm_protection_bits(void) +{ + return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); +} + +static int mmhub_v1_0_early_init(void *handle) +{ + return 0; +} + +static int mmhub_v1_0_late_init(void *handle) +{ + return 0; +} + +static int mmhub_v1_0_sw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); + hub->ctx0_ptb_addr_hi32 = + SOC15_REG_OFFSET(MMHUB, 0, + mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); + hub->vm_inv_eng0_req = + SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); + hub->vm_inv_eng0_ack = + SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); + hub->vm_context0_cntl = + SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); + hub->vm_l2_pro_fault_status = + SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); + hub->vm_l2_pro_fault_cntl = + SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); + + hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req; + hub->get_vm_protection_bits = mmhub_v1_0_get_vm_protection_bits; + + return 0; +} + +static int mmhub_v1_0_sw_fini(void *handle) +{ + return 0; +} + +static int mmhub_v1_0_hw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + unsigned i; + + for (i = 0; i < 18; ++i) { + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) + + 2 * i, 0xffffffff); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) + + 2 * i, 0x1f); + } + + return 0; +} + +static int mmhub_v1_0_hw_fini(void *handle) +{ + return 0; +} + +static int mmhub_v1_0_suspend(void *handle) +{ + return 0; +} + +static int mmhub_v1_0_resume(void *handle) +{ + return 0; +} + +static bool mmhub_v1_0_is_idle(void *handle) +{ + return true; +} + +static int mmhub_v1_0_wait_for_idle(void *handle) +{ + return 0; +} + +static int mmhub_v1_0_soft_reset(void *handle) +{ + return 0; +} + +static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data, def1, data1, def2, data2; + + def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG)); + def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2)); + def2 = data2 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { + data |= ATC_L2_MISC_CG__ENABLE_MASK; + + data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + + data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + } else { + data &= ~ATC_L2_MISC_CG__ENABLE_MASK; + + data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + + data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | + DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); + } + + if (def != data) + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data); + + if (def1 != data1) + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2), data1); + + if (def2 != data2) + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2), data2); +} + +static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) + data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; + else + data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; + + if (def != data) + WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data); +} + +static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) + data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; + else + data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; + + if (def != data) + WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data); +} + +static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && + (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) + data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; + else + data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; + + if(def != data) + WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data); +} + +static int mmhub_v1_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + switch (adev->asic_type) { + case CHIP_VEGA10: + mmhub_v1_0_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + athub_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + mmhub_v1_0_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + athub_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + break; + default: + break; + } + + return 0; +} + +static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int data; + + if (amdgpu_sriov_vf(adev)) + *flags = 0; + + /* AMD_CG_SUPPORT_MC_MGCG */ + data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL)); + if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_MC_MGCG; + + /* AMD_CG_SUPPORT_MC_LS */ + data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG)); + if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_MC_LS; +} + +static int mmhub_v1_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +const struct amd_ip_funcs mmhub_v1_0_ip_funcs = { + .name = "mmhub_v1_0", + .early_init = mmhub_v1_0_early_init, + .late_init = mmhub_v1_0_late_init, + .sw_init = mmhub_v1_0_sw_init, + .sw_fini = mmhub_v1_0_sw_fini, + .hw_init = mmhub_v1_0_hw_init, + .hw_fini = mmhub_v1_0_hw_fini, + .suspend = mmhub_v1_0_suspend, + .resume = mmhub_v1_0_resume, + .is_idle = mmhub_v1_0_is_idle, + .wait_for_idle = mmhub_v1_0_wait_for_idle, + .soft_reset = mmhub_v1_0_soft_reset, + .set_clockgating_state = mmhub_v1_0_set_clockgating_state, + .set_powergating_state = mmhub_v1_0_set_powergating_state, + .get_clockgating_state = mmhub_v1_0_get_clockgating_state, +}; + +const struct amdgpu_ip_block_version mmhub_v1_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_MMHUB, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &mmhub_v1_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h new file mode 100644 index 000000000000..aadedf99c028 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __MMHUB_V1_0_H__ +#define __MMHUB_V1_0_H__ + +u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev); +int mmhub_v1_0_gart_enable(struct amdgpu_device *adev); +void mmhub_v1_0_gart_disable(struct amdgpu_device *adev); +void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value); + +extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs; +extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h new file mode 100644 index 000000000000..5f0fc8bf16a9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h @@ -0,0 +1,87 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __MMSCH_V1_0_H__ +#define __MMSCH_V1_0_H__ + +#define MMSCH_VERSION_MAJOR 1 +#define MMSCH_VERSION_MINOR 0 +#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR) + +enum mmsch_v1_0_command_type { + MMSCH_COMMAND__DIRECT_REG_WRITE = 0, + MMSCH_COMMAND__DIRECT_REG_POLLING = 2, + MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3, + MMSCH_COMMAND__INDIRECT_REG_WRITE = 8, + MMSCH_COMMAND__END = 0xf +}; + +struct mmsch_v1_0_init_header { + uint32_t version; + uint32_t header_size; + uint32_t vce_init_status; + uint32_t uvd_init_status; + uint32_t vce_table_offset; + uint32_t vce_table_size; + uint32_t uvd_table_offset; + uint32_t uvd_table_size; +}; + +struct mmsch_v1_0_cmd_direct_reg_header { + uint32_t reg_offset : 28; + uint32_t command_type : 4; +}; + +struct mmsch_v1_0_cmd_indirect_reg_header { + uint32_t reg_offset : 20; + uint32_t reg_idx_space : 8; + uint32_t command_type : 4; +}; + +struct mmsch_v1_0_cmd_direct_write { + struct mmsch_v1_0_cmd_direct_reg_header cmd_header; + uint32_t reg_value; +}; + +struct mmsch_v1_0_cmd_direct_read_modify_write { + struct mmsch_v1_0_cmd_direct_reg_header cmd_header; + uint32_t write_data; + uint32_t mask_value; +}; + +struct mmsch_v1_0_cmd_direct_polling { + struct mmsch_v1_0_cmd_direct_reg_header cmd_header; + uint32_t mask_value; + uint32_t wait_value; +}; + +struct mmsch_v1_0_cmd_end { + struct mmsch_v1_0_cmd_direct_reg_header cmd_header; +}; + +struct mmsch_v1_0_cmd_indirect_write { + struct mmsch_v1_0_cmd_indirect_reg_header cmd_header; + uint32_t reg_value; +}; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c new file mode 100644 index 000000000000..cfd5e54777bb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -0,0 +1,207 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu.h" +#include "vega10/soc15ip.h" +#include "vega10/NBIO/nbio_6_1_offset.h" +#include "vega10/NBIO/nbio_6_1_sh_mask.h" +#include "vega10/GC/gc_9_0_offset.h" +#include "vega10/GC/gc_9_0_sh_mask.h" +#include "soc15.h" +#include "soc15_common.h" +#include "mxgpu_ai.h" + +static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) +{ + u32 reg; + int timeout = AI_MAILBOX_TIMEDOUT; + u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_VALID); + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_ACK, 1); + WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL), reg); + + /*Wait for RCV_MSG_VALID to be 0*/ + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + while (reg & mask) { + if (timeout <= 0) { + pr_err("RCV_MSG_VALID is not cleared\n"); + break; + } + mdelay(1); + timeout -=1; + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + } +} + +static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) +{ + u32 reg; + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL, + TRN_MSG_VALID, val ? 1 : 0); + WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL), + reg); +} + +static void xgpu_ai_mailbox_trans_msg(struct amdgpu_device *adev, + enum idh_request req) +{ + u32 reg; + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0)); + reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0, + MSGBUF_DATA, req); + WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), + reg); + + xgpu_ai_mailbox_set_valid(adev, true); +} + +static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev, + enum idh_event event) +{ + u32 reg; + u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_VALID); + + if (event != IDH_FLR_NOTIFICATION_CMPL) { + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + if (!(reg & mask)) + return -ENOENT; + } + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0)); + if (reg != event) + return -ENOENT; + + xgpu_ai_mailbox_send_ack(adev); + + return 0; +} + +static int xgpu_ai_poll_ack(struct amdgpu_device *adev) +{ + int r = 0, timeout = AI_MAILBOX_TIMEDOUT; + u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, TRN_MSG_ACK); + u32 reg; + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + while (!(reg & mask)) { + if (timeout <= 0) { + pr_err("Doesn't get ack from pf.\n"); + r = -ETIME; + break; + } + msleep(1); + timeout -= 1; + + reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_PF0_MAILBOX_CONTROL)); + } + + return r; +} + +static int xgpu_vi_poll_msg(struct amdgpu_device *adev, enum idh_event event) +{ + int r = 0, timeout = AI_MAILBOX_TIMEDOUT; + + r = xgpu_ai_mailbox_rcv_msg(adev, event); + while (r) { + if (timeout <= 0) { + pr_err("Doesn't get ack from pf.\n"); + r = -ETIME; + break; + } + msleep(1); + timeout -= 1; + + r = xgpu_ai_mailbox_rcv_msg(adev, event); + } + + return r; +} + + +static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, + enum idh_request req) +{ + int r; + + xgpu_ai_mailbox_trans_msg(adev, req); + + /* start to poll ack */ + r = xgpu_ai_poll_ack(adev); + if (r) + return r; + + xgpu_ai_mailbox_set_valid(adev, false); + + /* start to check msg if request is idh_req_gpu_init_access */ + if (req == IDH_REQ_GPU_INIT_ACCESS || + req == IDH_REQ_GPU_FINI_ACCESS || + req == IDH_REQ_GPU_RESET_ACCESS) { + r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); + if (r) + return r; + } + + return 0; +} + +static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev, + bool init) +{ + enum idh_request req; + + req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS; + return xgpu_ai_send_access_requests(adev, req); +} + +static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev, + bool init) +{ + enum idh_request req; + int r = 0; + + req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS; + r = xgpu_ai_send_access_requests(adev, req); + + return r; +} + +const struct amdgpu_virt_ops xgpu_ai_virt_ops = { + .req_full_gpu = xgpu_ai_request_full_gpu_access, + .rel_full_gpu = xgpu_ai_release_full_gpu_access, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h new file mode 100644 index 000000000000..bf8ab8fd4367 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __MXGPU_AI_H__ +#define __MXGPU_AI_H__ + +#define AI_MAILBOX_TIMEDOUT 150000 + +enum idh_request { + IDH_REQ_GPU_INIT_ACCESS = 1, + IDH_REL_GPU_INIT_ACCESS, + IDH_REQ_GPU_FINI_ACCESS, + IDH_REL_GPU_FINI_ACCESS, + IDH_REQ_GPU_RESET_ACCESS +}; + +enum idh_event { + IDH_CLR_MSG_BUF = 0, + IDH_READY_TO_ACCESS_GPU, + IDH_FLR_NOTIFICATION, + IDH_FLR_NOTIFICATION_CMPL, + IDH_EVENT_MAX +}; + +extern const struct amdgpu_virt_ops xgpu_ai_virt_ops; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index d2622b6f49fa..70a3dd13cb02 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -318,31 +318,46 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev) { u32 reg; + int timeout = VI_MAILBOX_TIMEDOUT; + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); - reg = RREG32(mmMAILBOX_CONTROL); + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1); - WREG32(mmMAILBOX_CONTROL, reg); + WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); + + /*Wait for RCV_MSG_VALID to be 0*/ + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); + while (reg & mask) { + if (timeout <= 0) { + pr_err("RCV_MSG_VALID is not cleared\n"); + break; + } + mdelay(1); + timeout -=1; + + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); + } } static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val) { u32 reg; - reg = RREG32(mmMAILBOX_CONTROL); + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, TRN_MSG_VALID, val ? 1 : 0); - WREG32(mmMAILBOX_CONTROL, reg); + WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); } static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev, - enum idh_event event) + enum idh_request req) { u32 reg; - reg = RREG32(mmMAILBOX_MSGBUF_TRN_DW0); + reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0, - MSGBUF_DATA, event); - WREG32(mmMAILBOX_MSGBUF_TRN_DW0, reg); + MSGBUF_DATA, req); + WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); xgpu_vi_mailbox_set_valid(adev, true); } @@ -351,8 +366,13 @@ static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev, enum idh_event event) { u32 reg; + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); - reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0); + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); + if (!(reg & mask)) + return -ENOENT; + + reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); if (reg != event) return -ENOENT; @@ -368,7 +388,7 @@ static int xgpu_vi_poll_ack(struct amdgpu_device *adev) u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); u32 reg; - reg = RREG32(mmMAILBOX_CONTROL); + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); while (!(reg & mask)) { if (timeout <= 0) { pr_err("Doesn't get ack from pf.\n"); @@ -378,7 +398,7 @@ static int xgpu_vi_poll_ack(struct amdgpu_device *adev) msleep(1); timeout -= 1; - reg = RREG32(mmMAILBOX_CONTROL); + reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); } return r; @@ -419,7 +439,9 @@ static int xgpu_vi_send_access_requests(struct amdgpu_device *adev, xgpu_vi_mailbox_set_valid(adev, false); /* start to check msg if request is idh_req_gpu_init_access */ - if (request == IDH_REQ_GPU_INIT_ACCESS) { + if (request == IDH_REQ_GPU_INIT_ACCESS || + request == IDH_REQ_GPU_FINI_ACCESS || + request == IDH_REQ_GPU_RESET_ACCESS) { r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); if (r) return r; @@ -436,20 +458,20 @@ static int xgpu_vi_request_reset(struct amdgpu_device *adev) static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev, bool init) { - enum idh_event event; + enum idh_request req; - event = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS; - return xgpu_vi_send_access_requests(adev, event); + req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS; + return xgpu_vi_send_access_requests(adev, req); } static int xgpu_vi_release_full_gpu_access(struct amdgpu_device *adev, bool init) { - enum idh_event event; + enum idh_request req; int r = 0; - event = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS; - r = xgpu_vi_send_access_requests(adev, event); + req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS; + r = xgpu_vi_send_access_requests(adev, req); return r; } @@ -468,28 +490,28 @@ static int xgpu_vi_set_mailbox_ack_irq(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 tmp = RREG32(mmMAILBOX_INT_CNTL); + u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN, (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); - WREG32(mmMAILBOX_INT_CNTL, tmp); + WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); return 0; } static void xgpu_vi_mailbox_flr_work(struct work_struct *work) { - struct amdgpu_virt *virt = container_of(work, - struct amdgpu_virt, flr_work.work); - struct amdgpu_device *adev = container_of(virt, - struct amdgpu_device, virt); - int r = 0; + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); + struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); - r = xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL); - if (r) - DRM_ERROR("failed to get flr cmpl msg from hypervior.\n"); + /* wait until RCV_MSG become 3 */ + if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) { + pr_err("failed to recieve FLR_CMPL\n"); + return; + } - /* TODO: need to restore gfx states */ + /* Trigger recovery due to world switch failure */ + amdgpu_sriov_gpu_reset(adev, false); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ -497,11 +519,11 @@ static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 tmp = RREG32(mmMAILBOX_INT_CNTL); + u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN, (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); - WREG32(mmMAILBOX_INT_CNTL, tmp); + WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); return 0; } @@ -512,15 +534,12 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev, { int r; - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; + /* see what event we get */ r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); - /* do nothing for other msg */ - if (r) - return 0; - /* TODO: need to save gfx states */ - schedule_delayed_work(&adev->virt.flr_work, - msecs_to_jiffies(VI_MAILBOX_RESET_TIME)); + /* only handle FLR_NOTIFY now */ + if (!r) + schedule_work(&adev->virt.flr_work); return 0; } @@ -547,11 +566,11 @@ int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev) { int r; - r = amdgpu_irq_add_id(adev, 135, &adev->virt.rcv_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq); if (r) return r; - r = amdgpu_irq_add_id(adev, 138, &adev->virt.ack_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq); if (r) { amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); return r; @@ -573,14 +592,13 @@ int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev) return r; } - INIT_DELAYED_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work); + INIT_WORK(&adev->virt.flr_work, xgpu_vi_mailbox_flr_work); return 0; } void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev) { - cancel_delayed_work_sync(&adev->virt.flr_work); amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h index fd6216efd2b0..2db741131bc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h @@ -23,7 +23,7 @@ #ifndef __MXGPU_VI_H__ #define __MXGPU_VI_H__ -#define VI_MAILBOX_TIMEDOUT 150 +#define VI_MAILBOX_TIMEDOUT 5000 #define VI_MAILBOX_RESET_TIME 12 /* VI mailbox messages request */ diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c new file mode 100644 index 000000000000..97057f4a10de --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -0,0 +1,266 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "nbio_v6_1.h" + +#include "vega10/soc15ip.h" +#include "vega10/NBIO/nbio_6_1_default.h" +#include "vega10/NBIO/nbio_6_1_offset.h" +#include "vega10/NBIO/nbio_6_1_sh_mask.h" +#include "vega10/vega10_enum.h" + +#define smnCPM_CONTROL 0x11180460 +#define smnPCIE_CNTL2 0x11180070 + +u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0)); + + tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; + tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; + + return tmp; +} + +u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx) +{ + return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx); +} + +void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx, uint32_t val) +{ + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val); +} + +void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) +{ + if (enable) + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), + BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); + else + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0); +} + +void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) +{ + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); +} + +u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) +{ + return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE)); +} + +static const u32 nbio_sdma_doorbell_range_reg[] = +{ + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE), + SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) +}; + +void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, + bool use_doorbell, int doorbell_index) +{ + u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]); + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); + } else + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); + + WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range); +} + +void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp; + + tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_DOORBELL_APER_EN)); + if (enable) + tmp = REG_SET_FIELD(tmp, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); + else + tmp = REG_SET_FIELD(tmp, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); + + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_DOORBELL_APER_EN), tmp); +} + +void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = 0; + + if (enable) { + tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | + REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); + + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW), + lower_32_bits(adev->doorbell.base)); + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH), + upper_32_bits(adev->doorbell.base)); + } + + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL), tmp); +} + + +void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index) +{ + u32 ih_doorbell_range = RREG32(SOC15_REG_OFFSET(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE)); + + if (use_doorbell) { + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); + } else + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); + + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_IH_DOORBELL_RANGE), ih_doorbell_range); +} + +void nbio_v6_1_ih_control(struct amdgpu_device *adev) +{ + u32 interrupt_cntl; + + /* setup interrupt control */ + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL2), adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL)); + /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); + /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL), interrupt_cntl); +} + +void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32_PCIE(smnCPM_CONTROL); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { + data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | + CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); + } else { + data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | + CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | + CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); + } + + if (def != data) + WREG32_PCIE(smnCPM_CONTROL, data); +} + +void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32_PCIE(smnPCIE_CNTL2); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { + data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); + } else { + data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); + } + + if (def != data) + WREG32_PCIE(smnPCIE_CNTL2, data); +} + +void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) +{ + int data; + + /* AMD_CG_SUPPORT_BIF_MGCG */ + data = RREG32_PCIE(smnCPM_CONTROL); + if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_BIF_MGCG; + + /* AMD_CG_SUPPORT_BIF_LS */ + data = RREG32_PCIE(smnPCIE_CNTL2); + if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) + *flags |= AMD_CG_SUPPORT_BIF_LS; +} + +struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; +struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; + +int nbio_v6_1_init(struct amdgpu_device *adev) +{ + nbio_v6_1_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); + nbio_v6_1_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK; + nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK; + + nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX); + nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); + + return 0; +} + +void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) +{ + uint32_t reg; + + reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, + mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER)); + if (reg & 1) + adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; + + if (reg & 0x80000000) + adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; + + if (!reg) { + if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ + adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h new file mode 100644 index 000000000000..f6f8bc045518 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h @@ -0,0 +1,54 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NBIO_V6_1_H__ +#define __NBIO_V6_1_H__ + +#include "soc15_common.h" + +extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; +extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; +int nbio_v6_1_init(struct amdgpu_device *adev); +u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx); +void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, + uint32_t idx, uint32_t val); +void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable); +void nbio_v6_1_hdp_flush(struct amdgpu_device *adev); +u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev); +void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, + bool use_doorbell, int doorbell_index); +void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable); +void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, + bool enable); +void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, + bool use_doorbell, int doorbell_index); +void nbio_v6_1_ih_control(struct amdgpu_device *adev); +u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev); +void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable); +void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable); +void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); +void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h new file mode 100644 index 000000000000..8da6da90b1c9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -0,0 +1,269 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _PSP_TEE_GFX_IF_H_ +#define _PSP_TEE_GFX_IF_H_ + +#define PSP_GFX_CMD_BUF_VERSION 0x00000001 + +#define GFX_CMD_STATUS_MASK 0x0000FFFF +#define GFX_CMD_ID_MASK 0x000F0000 +#define GFX_CMD_RESERVED_MASK 0x7FF00000 +#define GFX_CMD_RESPONSE_MASK 0x80000000 + +/* TEE Gfx Command IDs for the register interface. +* Command ID must be between 0x00010000 and 0x000F0000. +*/ +enum psp_gfx_crtl_cmd_id +{ + GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ + GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ + GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ + GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ + + GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ +}; + + +/* Control registers of the TEE Gfx interface. These are located in +* SRBM-to-PSP mailbox registers (total 8 registers). +*/ +struct psp_gfx_ctrl +{ + volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ + volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ + volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ + volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ + volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ + volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of physical address of ring buffer */ + volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of physical address of ring buffer */ + volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ + +}; + + +/* Response flag is set in the command when command is completed by PSP. +* Used in the GFX_CTRL.CmdResp. +* When PSP GFX I/F is initialized, the flag is set. +*/ +#define GFX_FLAG_RESPONSE 0x80000000 + + +/* TEE Gfx Command IDs for the ring buffer interface. */ +enum psp_gfx_cmd_id +{ + GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ + GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ + GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ + GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ + GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ + GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ + +}; + + +/* Command to load Trusted Application binary into PSP OS. */ +struct psp_gfx_cmd_load_ta +{ + uint32_t app_phy_addr_lo; /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */ + uint32_t app_phy_addr_hi; /* bits [63:32] of the physical address of the TA binary */ + uint32_t app_len; /* length of the TA binary in bytes */ + uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */ + uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the physical address of CMD buffer */ + uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ + + /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided + * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead + * of using global persistent buffer. + */ +}; + + +/* Command to Unload Trusted Application binary from PSP OS. */ +struct psp_gfx_cmd_unload_ta +{ + uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ + +}; + + +/* Shared buffers for InvokeCommand. +*/ +struct psp_gfx_buf_desc +{ + uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */ + uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of the buffer */ + uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ + +}; + +/* Max number of descriptors for one shared buffer (in how many different +* physical locations one shared buffer can be stored). If buffer is too much +* fragmented, error will be returned. +*/ +#define GFX_BUF_MAX_DESC 64 + +struct psp_gfx_buf_list +{ + uint32_t num_desc; /* number of buffer descriptors in the list */ + uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ + struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ + + /* total 776 bytes */ +}; + +/* Command to execute InvokeCommand entry point of the TA. */ +struct psp_gfx_cmd_invoke_cmd +{ + uint32_t session_id; /* Session ID of the TA to be executed */ + uint32_t ta_cmd_id; /* Command ID to be sent to TA */ + struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ + +}; + + +/* Command to setup TMR region. */ +struct psp_gfx_cmd_setup_tmr +{ + uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */ + uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of TMR buffer */ + uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ + +}; + + +/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ +enum psp_gfx_fw_type +{ + GFX_FW_TYPE_NONE = 0, + GFX_FW_TYPE_CP_ME = 1, + GFX_FW_TYPE_CP_PFP = 2, + GFX_FW_TYPE_CP_CE = 3, + GFX_FW_TYPE_CP_MEC = 4, + GFX_FW_TYPE_CP_MEC_ME1 = 5, + GFX_FW_TYPE_CP_MEC_ME2 = 6, + GFX_FW_TYPE_RLC_V = 7, + GFX_FW_TYPE_RLC_G = 8, + GFX_FW_TYPE_SDMA0 = 9, + GFX_FW_TYPE_SDMA1 = 10, + GFX_FW_TYPE_DMCU_ERAM = 11, + GFX_FW_TYPE_DMCU_ISR = 12, + GFX_FW_TYPE_VCN = 13, + GFX_FW_TYPE_UVD = 14, + GFX_FW_TYPE_VCE = 15, + GFX_FW_TYPE_ISP = 16, + GFX_FW_TYPE_ACP = 17, + GFX_FW_TYPE_SMU = 18, +}; + +/* Command to load HW IP FW. */ +struct psp_gfx_cmd_load_ip_fw +{ + uint32_t fw_phy_addr_lo; /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */ + uint32_t fw_phy_addr_hi; /* bits [63:32] of physical address of FW location */ + uint32_t fw_size; /* FW buffer size in bytes */ + enum psp_gfx_fw_type fw_type; /* FW type */ + +}; + + +/* All GFX ring buffer commands. */ +union psp_gfx_commands +{ + struct psp_gfx_cmd_load_ta cmd_load_ta; + struct psp_gfx_cmd_unload_ta cmd_unload_ta; + struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; + struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; + struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; + +}; + + +/* Structure of GFX Response buffer. +* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI +* it is separate buffer. +*/ +struct psp_gfx_resp +{ + uint32_t status; /* +0 status of command execution */ + uint32_t session_id; /* +4 session ID in response to LoadTa command */ + uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ + uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ + + uint32_t reserved[4]; + + /* total 32 bytes */ +}; + +/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi +* and psp_gfx_rb_frame.cmd_buf_addr_lo. +*/ +struct psp_gfx_cmd_resp +{ + uint32_t buf_size; /* +0 total size of the buffer in bytes */ + uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ + uint32_t cmd_id; /* +8 command ID */ + + /* These fields are used for RBI only. They are all 0 in GPCOM commands + */ + uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */ + uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of physical address of response buffer */ + uint32_t resp_offset; /* +20 offset within response buffer */ + uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ + + union psp_gfx_commands cmd; /* +28 command specific structures */ + + uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; + + /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response + * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. + */ + struct psp_gfx_resp resp; /* +864 response */ + + uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; + + /* total size 1024 bytes */ +}; + + +#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ + +/* Structure of the Ring Buffer Frame */ +struct psp_gfx_rb_frame +{ + uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of physical address of command buffer (must be 4 KB aligned) */ + uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of physical address of command buffer */ + uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ + uint32_t fence_addr_lo; /* +12 bits [31:0] of physical address of Fence for this frame */ + uint32_t fence_addr_hi; /* +16 bits [63:32] of physical address of Fence for this frame */ + uint32_t fence_value; /* +20 Fence value */ + uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ + uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ + uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */ + uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ + uint8_t reserved1[2]; /* +34 reserved, must be 0 */ + uint32_t reserved2[7]; /* +40 reserved, must be 0 */ + /* total 64 bytes */ +}; + +#endif /* _PSP_TEE_GFX_IF_H_ */ diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c new file mode 100644 index 000000000000..5191c45ffdf3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -0,0 +1,521 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ + +#include <linux/firmware.h> +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_psp.h" +#include "amdgpu_ucode.h" +#include "soc15_common.h" +#include "psp_v3_1.h" + +#include "vega10/soc15ip.h" +#include "vega10/MP/mp_9_0_offset.h" +#include "vega10/MP/mp_9_0_sh_mask.h" +#include "vega10/GC/gc_9_0_offset.h" +#include "vega10/SDMA0/sdma0_4_0_offset.h" +#include "vega10/NBIO/nbio_6_1_offset.h" + +MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); +MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); + +#define smnMP1_FIRMWARE_FLAGS 0x3010028 + +static int +psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) +{ + switch(ucode->ucode_id) { + case AMDGPU_UCODE_ID_SDMA0: + *type = GFX_FW_TYPE_SDMA0; + break; + case AMDGPU_UCODE_ID_SDMA1: + *type = GFX_FW_TYPE_SDMA1; + break; + case AMDGPU_UCODE_ID_CP_CE: + *type = GFX_FW_TYPE_CP_CE; + break; + case AMDGPU_UCODE_ID_CP_PFP: + *type = GFX_FW_TYPE_CP_PFP; + break; + case AMDGPU_UCODE_ID_CP_ME: + *type = GFX_FW_TYPE_CP_ME; + break; + case AMDGPU_UCODE_ID_CP_MEC1: + *type = GFX_FW_TYPE_CP_MEC; + break; + case AMDGPU_UCODE_ID_CP_MEC1_JT: + *type = GFX_FW_TYPE_CP_MEC_ME1; + break; + case AMDGPU_UCODE_ID_CP_MEC2: + *type = GFX_FW_TYPE_CP_MEC; + break; + case AMDGPU_UCODE_ID_CP_MEC2_JT: + *type = GFX_FW_TYPE_CP_MEC_ME2; + break; + case AMDGPU_UCODE_ID_RLC_G: + *type = GFX_FW_TYPE_RLC_G; + break; + case AMDGPU_UCODE_ID_SMC: + *type = GFX_FW_TYPE_SMU; + break; + case AMDGPU_UCODE_ID_UVD: + *type = GFX_FW_TYPE_UVD; + break; + case AMDGPU_UCODE_ID_VCE: + *type = GFX_FW_TYPE_VCE; + break; + case AMDGPU_UCODE_ID_MAXIMUM: + default: + return -EINVAL; + } + + return 0; +} + +int psp_v3_1_init_microcode(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + const char *chip_name; + char fw_name[30]; + int err = 0; + const struct psp_firmware_header_v1_0 *hdr; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_VEGA10: + chip_name = "vega10"; + break; + default: BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); + err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); + if (err) + goto out; + + err = amdgpu_ucode_validate(adev->psp.sos_fw); + if (err) + goto out; + + hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; + adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); + adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); + adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); + adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - + le32_to_cpu(hdr->sos_size_bytes); + adev->psp.sys_start_addr = (uint8_t *)hdr + + le32_to_cpu(hdr->header.ucode_array_offset_bytes); + adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + + le32_to_cpu(hdr->sos_offset_bytes); + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); + err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); + if (err) + goto out; + + err = amdgpu_ucode_validate(adev->psp.asd_fw); + if (err) + goto out; + + hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; + adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); + adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); + adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); + adev->psp.asd_start_addr = (uint8_t *)hdr + + le32_to_cpu(hdr->header.ucode_array_offset_bytes); + + return 0; +out: + if (err) { + dev_err(adev->dev, + "psp v3.1: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->psp.sos_fw); + adev->psp.sos_fw = NULL; + release_firmware(adev->psp.asd_fw); + adev->psp.asd_fw = NULL; + } + + return err; +} + +int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) +{ + int ret; + uint32_t psp_gfxdrv_command_reg = 0; + struct amdgpu_bo *psp_sysdrv; + void *psp_sysdrv_virt = NULL; + uint64_t psp_sysdrv_mem; + struct amdgpu_device *adev = psp->adev; + uint32_t size, sol_reg; + + /* Check sOS sign of life register to confirm sys driver and sOS + * are already been loaded. + */ + sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); + if (sol_reg) + return 0; + + /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + 0x80000000, 0x80000000, false); + if (ret) + return ret; + + /* + * Create a 1 meg GART memory to store the psp sys driver + * binary with a 1 meg aligned address + */ + size = (psp->sys_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) & + (~(PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)); + + ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT, + AMDGPU_GEM_DOMAIN_GTT, + &psp_sysdrv, + &psp_sysdrv_mem, + &psp_sysdrv_virt); + if (ret) + return ret; + + /* Copy PSP System Driver binary to memory */ + memcpy(psp_sysdrv_virt, psp->sys_start_addr, psp->sys_bin_size); + + /* Provide the sys driver to bootrom */ + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), + (uint32_t)(psp_sysdrv_mem >> 20)); + psp_gfxdrv_command_reg = 1 << 16; + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + psp_gfxdrv_command_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + 0x80000000, 0x80000000, false); + + amdgpu_bo_free_kernel(&psp_sysdrv, &psp_sysdrv_mem, &psp_sysdrv_virt); + + return ret; +} + +int psp_v3_1_bootloader_load_sos(struct psp_context *psp) +{ + int ret; + unsigned int psp_gfxdrv_command_reg = 0; + struct amdgpu_bo *psp_sos; + void *psp_sos_virt = NULL; + uint64_t psp_sos_mem; + struct amdgpu_device *adev = psp->adev; + uint32_t size, sol_reg; + + /* Check sOS sign of life register to confirm sys driver and sOS + * are already been loaded. + */ + sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); + if (sol_reg) + return 0; + + /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + 0x80000000, 0x80000000, false); + if (ret) + return ret; + + size = (psp->sos_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) & + (~((uint64_t)PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)); + + ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT, + AMDGPU_GEM_DOMAIN_GTT, + &psp_sos, + &psp_sos_mem, + &psp_sos_virt); + if (ret) + return ret; + + /* Copy Secure OS binary to PSP memory */ + memcpy(psp_sos_virt, psp->sos_start_addr, psp->sos_bin_size); + + /* Provide the PSP secure OS to bootrom */ + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), + (uint32_t)(psp_sos_mem >> 20)); + psp_gfxdrv_command_reg = 2 << 16; + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), + psp_gfxdrv_command_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); +#if 0 + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), + RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)), + 0, true); +#endif + + amdgpu_bo_free_kernel(&psp_sos, &psp_sos_mem, &psp_sos_virt); + + return ret; +} + +int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd) +{ + int ret; + uint64_t fw_mem_mc_addr = ucode->mc_addr; + + memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); + + cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr; + cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32); + cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; + + ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); + if (ret) + DRM_ERROR("Unknown firmware type\n"); + + return ret; +} + +int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) +{ + int ret = 0; + unsigned int psp_ring_reg = 0; + struct psp_ring *ring; + struct amdgpu_device *adev = psp->adev; + + ring = &psp->km_ring; + + ring->ring_type = ring_type; + + /* allocate 4k Page of Local Frame Buffer memory for ring */ + ring->ring_size = 0x1000; + ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->firmware.rbuf, + &ring->ring_mem_mc_addr, + (void **)&ring->ring_mem); + if (ret) { + ring->ring_size = 0; + return ret; + } + + /* Write low address of the ring to C2PMSG_69 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg); + /* Write high address of the ring to C2PMSG_70 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg); + /* Write size of ring to C2PMSG_71 */ + psp_ring_reg = ring->ring_size; + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg); + /* Write the ring initialization command to C2PMSG_64 */ + psp_ring_reg = ring_type; + psp_ring_reg = psp_ring_reg << 16; + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_64 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), + 0x80000000, 0x8000FFFF, false); + + return ret; +} + +int psp_v3_1_cmd_submit(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, + int index) +{ + unsigned int psp_write_ptr_reg = 0; + struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + uint32_t ring_size_dw = ring->ring_size / 4; + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; + + /* KM (GPCOM) prepare write pointer */ + psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67)); + + /* Update KM RB frame pointer to new frame */ + /* write_frame ptr increments by size of rb_frame in bytes */ + /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ + if ((psp_write_ptr_reg % ring_size_dw) == 0) + write_frame = ring->ring_mem; + else + write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw); + + /* Initialize KM RB frame */ + memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); + + /* Update KM RB frame */ + write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32); + write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr); + write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32); + write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr); + write_frame->fence_value = index; + + /* Update the write Pointer in DWORDs */ + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg); + + return 0; +} + +static int +psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, + unsigned int *sram_data_reg_offset, + enum AMDGPU_UCODE_ID ucode_id) +{ + int ret = 0; + + switch(ucode_id) { +/* TODO: needs to confirm */ +#if 0 + case AMDGPU_UCODE_ID_SMC: + *sram_offset = 0; + *sram_addr_reg_offset = 0; + *sram_data_reg_offset = 0; + break; +#endif + + case AMDGPU_UCODE_ID_CP_CE: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_PFP: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_ME: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_MEC1: + *sram_offset = 0x10000; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_CP_MEC2: + *sram_offset = 0x10000; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_RLC_G: + *sram_offset = 0x2000; + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); + break; + + case AMDGPU_UCODE_ID_SDMA0: + *sram_offset = 0x0; + *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); + break; + +/* TODO: needs to confirm */ +#if 0 + case AMDGPU_UCODE_ID_SDMA1: + *sram_offset = ; + *sram_addr_reg_offset = ; + break; + + case AMDGPU_UCODE_ID_UVD: + *sram_offset = ; + *sram_addr_reg_offset = ; + break; + + case AMDGPU_UCODE_ID_VCE: + *sram_offset = ; + *sram_addr_reg_offset = ; + break; +#endif + + case AMDGPU_UCODE_ID_MAXIMUM: + default: + ret = -EINVAL; + break; + } + + return ret; +} + +bool psp_v3_1_compare_sram_data(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + enum AMDGPU_UCODE_ID ucode_type) +{ + int err = 0; + unsigned int fw_sram_reg_val = 0; + unsigned int fw_sram_addr_reg_offset = 0; + unsigned int fw_sram_data_reg_offset = 0; + unsigned int ucode_size; + uint32_t *ucode_mem = NULL; + struct amdgpu_device *adev = psp->adev; + + err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, + &fw_sram_data_reg_offset, ucode_type); + if (err) + return false; + + WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); + + ucode_size = ucode->ucode_size; + ucode_mem = (uint32_t *)ucode->kaddr; + while (!ucode_size) { + fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); + + if (*ucode_mem != fw_sram_reg_val) + return false; + + ucode_mem++; + /* 4 bytes */ + ucode_size -= 4; + } + + return true; +} + +bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + uint32_t reg, reg_val; + + reg_val = (smnMP1_FIRMWARE_FLAGS & 0xffffffff) | 0x03b00000; + WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg_val); + reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)); + if ((reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return true; + + return false; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h new file mode 100644 index 000000000000..e82eff741a08 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h @@ -0,0 +1,50 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Huang Rui + * + */ +#ifndef __PSP_V3_1_H__ +#define __PSP_V3_1_H__ + +#include "amdgpu_psp.h" + +enum { PSP_DIRECTORY_TABLE_ENTRIES = 4 }; +enum { PSP_BINARY_ALIGNMENT = 64 }; +enum { PSP_BOOTLOADER_1_MEG_ALIGNMENT = 0x100000 }; +enum { PSP_BOOTLOADER_8_MEM_ALIGNMENT = 0x800000 }; + +extern int psp_v3_1_init_microcode(struct psp_context *psp); +extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp); +extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp); +extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, + struct psp_gfx_cmd_resp *cmd); +extern int psp_v3_1_ring_init(struct psp_context *psp, + enum psp_ring_type ring_type); +extern int psp_v3_1_cmd_submit(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, + int index); +extern bool psp_v3_1_compare_sram_data(struct psp_context *psp, + struct amdgpu_firmware_info *ucode, + enum AMDGPU_UCODE_ID ucode_type); +extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp); +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 896be64b7013..f2d0710258cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -158,7 +158,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) if (adev->sdma.instance[i].feature_version >= 20) adev->sdma.instance[i].burst_nop = true; - if (adev->firmware.smu_load) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; info->fw = adev->sdma.instance[i].fw; @@ -170,9 +170,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) out: if (err) { - printk(KERN_ERR - "sdma_v2_4: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); for (i = 0; i < adev->sdma.num_instances; i++) { release_firmware(adev->sdma.instance[i].fw); adev->sdma.instance[i].fw = NULL; @@ -188,7 +186,7 @@ out: * * Get the current rptr from the hardware (VI+). */ -static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) { /* XXX check if swapping is necessary on BE */ return ring->adev->wb.wb[ring->rptr_offs] >> 2; @@ -201,7 +199,7 @@ static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) * * Get the current wptr from the hardware (VI+). */ -static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; @@ -222,7 +220,7 @@ static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); } static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) @@ -253,7 +251,7 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, u32 vmid = vm_id & 0xf; /* IB packet must end on a 8 DW boundary */ - sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); + sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); @@ -468,7 +466,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); ring->wptr = 0; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); /* enable DMA RB */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); @@ -564,7 +562,7 @@ static int sdma_v2_4_start(struct amdgpu_device *adev) int r; if (!adev->pp_enabled) { - if (!adev->firmware.smu_load) { + if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { r = sdma_v2_4_load_microcode(adev); if (r) return r; @@ -800,14 +798,14 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, */ static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, - uint32_t incr, uint32_t flags) + uint32_t incr, uint64_t flags) { /* for physically contiguous pages (vram) */ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ @@ -923,17 +921,20 @@ static int sdma_v2_4_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* SDMA trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, + &adev->sdma.trap_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, + &adev->sdma.illegal_inst_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, + &adev->sdma.illegal_inst_irq); if (r) return r; @@ -1208,6 +1209,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, .align_mask = 0xf, .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = false, .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, .set_wptr = sdma_v2_4_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 011800f621c6..a69e5d4e1d2a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -310,7 +310,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) if (adev->sdma.instance[i].feature_version >= 20) adev->sdma.instance[i].burst_nop = true; - if (adev->firmware.smu_load) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; info->fw = adev->sdma.instance[i].fw; @@ -321,9 +321,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) } out: if (err) { - printk(KERN_ERR - "sdma_v3_0: Failed to load firmware \"%s\"\n", - fw_name); + pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); for (i = 0; i < adev->sdma.num_instances; i++) { release_firmware(adev->sdma.instance[i].fw); adev->sdma.instance[i].fw = NULL; @@ -339,7 +337,7 @@ out: * * Get the current rptr from the hardware (VI+). */ -static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) { /* XXX check if swapping is necessary on BE */ return ring->adev->wb.wb[ring->rptr_offs] >> 2; @@ -352,7 +350,7 @@ static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) * * Get the current wptr from the hardware (VI+). */ -static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 wptr; @@ -382,12 +380,12 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) if (ring->use_doorbell) { /* XXX check if swapping is necessary on BE */ - adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; - WDOORBELL32(ring->doorbell_index, ring->wptr << 2); + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2; + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); } else { int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); } } @@ -419,7 +417,7 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, u32 vmid = vm_id & 0xf; /* IB packet must end on a 8 DW boundary */ - sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); + sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); @@ -615,6 +613,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) for (i = 0; i < adev->sdma.num_instances; i++) { ring = &adev->sdma.instance[i].ring; + amdgpu_ring_clear_ring(ring); wb_offset = (ring->rptr_offs * 4); mutex_lock(&adev->srbm_mutex); @@ -661,7 +660,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); ring->wptr = 0; - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); @@ -772,7 +771,7 @@ static int sdma_v3_0_start(struct amdgpu_device *adev) int r, i; if (!adev->pp_enabled) { - if (!adev->firmware.smu_load) { + if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { r = sdma_v3_0_load_microcode(adev); if (r) return r; @@ -1008,14 +1007,14 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, */ static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, - uint32_t incr, uint32_t flags) + uint32_t incr, uint64_t flags) { /* for physically contiguous pages (vram) */ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(addr); ib->ptr[ib->length_dw++] = incr; /* increment size */ @@ -1138,17 +1137,20 @@ static int sdma_v3_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* SDMA trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, + &adev->sdma.trap_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, + &adev->sdma.illegal_inst_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, + &adev->sdma.illegal_inst_irq); if (r) return r; @@ -1512,14 +1514,17 @@ static int sdma_v3_0_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (amdgpu_sriov_vf(adev)) + return 0; + switch (adev->asic_type) { case CHIP_FIJI: case CHIP_CARRIZO: case CHIP_STONEY: sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; default: break; @@ -1538,6 +1543,9 @@ static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int data; + if (amdgpu_sriov_vf(adev)) + *flags = 0; + /* AMD_CG_SUPPORT_SDMA_MGCG */ data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) @@ -1574,6 +1582,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, .align_mask = 0xf, .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = false, .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, .set_wptr = sdma_v3_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c new file mode 100644 index 000000000000..2dd2b20d727e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -0,0 +1,1616 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/firmware.h> +#include <drm/drmP.h> +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_trace.h" + +#include "vega10/soc15ip.h" +#include "vega10/SDMA0/sdma0_4_0_offset.h" +#include "vega10/SDMA0/sdma0_4_0_sh_mask.h" +#include "vega10/SDMA1/sdma1_4_0_offset.h" +#include "vega10/SDMA1/sdma1_4_0_sh_mask.h" +#include "vega10/MMHUB/mmhub_1_0_offset.h" +#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "vega10/HDP/hdp_4_0_offset.h" + +#include "soc15_common.h" +#include "soc15.h" +#include "vega10_sdma_pkt_open.h" + +MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); + +static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); +static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); +static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); +static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); + +static const u32 golden_settings_sdma_4[] = +{ + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0 +}; + +static const u32 golden_settings_sdma_vg10[] = +{ + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, + SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, + SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002 +}; + +static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset) +{ + u32 base = 0; + switch (instance) { + case 0: + base = SDMA0_BASE.instance[0].segment[0]; + break; + case 1: + base = SDMA1_BASE.instance[0].segment[0]; + break; + default: + BUG(); + break; + } + + return base + internal_offset; +} + +static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_VEGA10: + amdgpu_program_register_sequence(adev, + golden_settings_sdma_4, + (const u32)ARRAY_SIZE(golden_settings_sdma_4)); + amdgpu_program_register_sequence(adev, + golden_settings_sdma_vg10, + (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); + break; + default: + break; + } +} + +static void sdma_v4_0_print_ucode_regs(void *handle) +{ + int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + dev_info(adev->dev, "VEGA10 SDMA ucode registers\n"); + for (i = 0; i < adev->sdma.num_instances; i++) { + dev_info(adev->dev, " SDMA%d_UCODE_ADDR=0x%08X\n", + i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR))); + dev_info(adev->dev, " SDMA%d_UCODE_CHECKSUM=0x%08X\n", + i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM))); + } +} + +/** + * sdma_v4_0_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ + +// emulation only, won't work on real chip +// vega10 real chip need to use PSP to load firmware +static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err = 0, i; + struct amdgpu_firmware_info *info = NULL; + const struct common_firmware_header *header = NULL; + const struct sdma_firmware_header_v1_0 *hdr; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_VEGA10: + chip_name = "vega10"; + break; + default: BUG(); + } + + for (i = 0; i < adev->sdma.num_instances; i++) { + if (i == 0) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); + err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); + if (err) + goto out; + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; + adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); + if (adev->sdma.instance[i].feature_version >= 20) + adev->sdma.instance[i].burst_nop = true; + DRM_DEBUG("psp_load == '%s'\n", + adev->firmware.load_type == AMDGPU_FW_LOAD_PSP? "true": "false"); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; + info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; + info->fw = adev->sdma.instance[i].fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + } +out: + if (err) { + printk(KERN_ERR + "sdma_v4_0: Failed to load firmware \"%s\"\n", + fw_name); + for (i = 0; i < adev->sdma.num_instances; i++) { + release_firmware(adev->sdma.instance[i].fw); + adev->sdma.instance[i].fw = NULL; + } + } + return err; +} + +/** + * sdma_v4_0_ring_get_rptr - get the current read pointer + * + * @ring: amdgpu ring pointer + * + * Get the current rptr from the hardware (VEGA10+). + */ +static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + u64* rptr; + + /* XXX check if swapping is necessary on BE */ + rptr =((u64*)&ring->adev->wb.wb[ring->rptr_offs]); + + DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); + return ((*rptr) >> 2); +} + +/** + * sdma_v4_0_ring_get_wptr - get the current write pointer + * + * @ring: amdgpu ring pointer + * + * Get the current wptr from the hardware (VEGA10+). + */ +static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u64* wptr = NULL; + uint64_t local_wptr=0; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + wptr = ((u64*)&adev->wb.wb[ring->wptr_offs]); + DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); + *wptr = (*wptr) >> 2; + DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); + } else { + u32 lowbit, highbit; + int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; + wptr=&local_wptr; + lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2; + highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; + + DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", + me, highbit, lowbit); + *wptr = highbit; + *wptr = (*wptr) << 32; + *wptr |= lowbit; + } + + return *wptr; +} + +/** + * sdma_v4_0_ring_set_wptr - commit the write pointer + * + * @ring: amdgpu ring pointer + * + * Write the wptr back to the hardware (VEGA10+). + */ +static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + DRM_DEBUG("Setting write pointer\n"); + if (ring->use_doorbell) { + DRM_DEBUG("Using doorbell -- " + "wptr_offs == 0x%08x " + "lower_32_bits(ring->wptr) << 2 == 0x%08x " + "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", + ring->wptr_offs, + lower_32_bits(ring->wptr << 2), + upper_32_bits(ring->wptr << 2)); + /* XXX check if swapping is necessary on BE */ + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); + adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); + DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", + ring->doorbell_index, ring->wptr << 2); + WDOORBELL64(ring->doorbell_index, ring->wptr << 2); + } else { + int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; + DRM_DEBUG("Not using doorbell -- " + "mmSDMA%i_GFX_RB_WPTR == 0x%08x " + "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x \n", + me, + me, + lower_32_bits(ring->wptr << 2), + upper_32_bits(ring->wptr << 2)); + WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } +} + +static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) +{ + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); + int i; + + for (i = 0; i < count; i++) + if (sdma && sdma->burst_nop && (i == 0)) + amdgpu_ring_write(ring, ring->funcs->nop | + SDMA_PKT_NOP_HEADER_COUNT(count - 1)); + else + amdgpu_ring_write(ring, ring->funcs->nop); +} + +/** + * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine + * + * @ring: amdgpu ring pointer + * @ib: IB object to schedule + * + * Schedule an IB in the DMA ring (VEGA10). + */ +static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) +{ + u32 vmid = vm_id & 0xf; + + /* IB packet must end on a 8 DW boundary */ + sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | + SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); + /* base must be 32 byte aligned */ + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); + +} + +/** + * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring + * + * @ring: amdgpu ring pointer + * + * Emit an hdp flush packet on the requested DMA ring. + */ +static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +{ + u32 ref_and_mask = 0; + struct nbio_hdp_flush_reg *nbio_hf_reg; + + if (ring->adev->asic_type == CHIP_VEGA10) + nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; + + if (ring == &ring->adev->sdma.instance[0].ring) + ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; + else + ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ + amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2); + amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2); + amdgpu_ring_write(ring, ref_and_mask); /* reference */ + amdgpu_ring_write(ring, ref_and_mask); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ +} + +static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0)); + amdgpu_ring_write(ring, 1); +} + +/** + * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring + * + * @ring: amdgpu ring pointer + * @fence: amdgpu fence object + * + * Add a DMA fence packet to the ring to write + * the fence seq number and DMA trap packet to generate + * an interrupt if needed (VEGA10). + */ +static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + unsigned flags) +{ + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + /* write the fence */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); + /* zero in first two bits */ + BUG_ON(addr & 0x3); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + /* optionally write high bits as well */ + if (write64bit) { + addr += 4; + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); + /* zero in first two bits */ + BUG_ON(addr & 0x3); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } + + /* generate an interrupt */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); + amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); +} + + +/** + * sdma_v4_0_gfx_stop - stop the gfx async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the gfx async dma ring buffers (VEGA10). + */ +static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; + u32 rb_cntl, ib_cntl; + int i; + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); + + for (i = 0; i < adev->sdma.num_instances; i++) { + rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + } + + sdma0->ready = false; + sdma1->ready = false; +} + +/** + * sdma_v4_0_rlc_stop - stop the compute async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the compute async dma queues (VEGA10). + */ +static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) +{ + /* XXX todo */ +} + +/** + * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs context switch. + * + * Halt or unhalt the async dma engines context switch (VEGA10). + */ +static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) +{ + u32 f32_cntl; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) { + f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, + AUTO_CTXSW_ENABLE, enable ? 1 : 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl); + } + +} + +/** + * sdma_v4_0_enable - stop the async dma engines + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs. + * + * Halt or unhalt the async dma engines (VEGA10). + */ +static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) +{ + u32 f32_cntl; + int i; + + if (enable == false) { + sdma_v4_0_gfx_stop(adev); + sdma_v4_0_rlc_stop(adev); + } + + for (i = 0; i < adev->sdma.num_instances; i++) { + f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl); + } +} + +/** + * sdma_v4_0_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them (VEGA10). + * Returns 0 for success, error for failure. + */ +static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 rb_cntl, ib_cntl; + u32 rb_bufsz; + u32 wb_offset; + u32 doorbell; + u32 doorbell_offset; + u32 temp; + int i,r; + + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + wb_offset = (ring->rptr_offs * 4); + + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); +#ifdef __BIG_ENDIAN + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); +#endif + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0); + + /* set the wb address whether it's enabled or not */ + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); + + ring->wptr = 0; + + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + } + + doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET)); + + if (ring->use_doorbell){ + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); + } + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); + nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); + + if (amdgpu_sriov_vf(adev)) + sdma_v4_0_ring_set_wptr(ring); + + /* set minor_ptr_update to 0 after wptr programed */ + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + + /* set utc l1 enable flag always to 1 */ + temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp); + + if (!amdgpu_sriov_vf(adev)) { + /* unhalt engine */ + temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp); + } + + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); +#ifdef __BIG_ENDIAN + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); +#endif + /* enable DMA IBs */ + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + + ring->ready = true; + + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v4_0_ctx_switch_enable(adev, true); + sdma_v4_0_enable(adev, true); + } + + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + if (adev->mman.buffer_funcs_ring == ring) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); + } + + return 0; +} + +/** + * sdma_v4_0_rlc_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the compute DMA queues and enable them (VEGA10). + * Returns 0 for success, error for failure. + */ +static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +/** + * sdma_v4_0_load_microcode - load the sDMA ME ucode + * + * @adev: amdgpu_device pointer + * + * Loads the sDMA0/1 ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) +{ + const struct sdma_firmware_header_v1_0 *hdr; + const __le32 *fw_data; + u32 fw_size; + u32 digest_size = 0; + int i, j; + + /* halt the MEs */ + sdma_v4_0_enable(adev, false); + + for (i = 0; i < adev->sdma.num_instances; i++) { + uint16_t version_major; + uint16_t version_minor; + if (!adev->sdma.instance[i].fw) + return -EINVAL; + + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; + amdgpu_ucode_print_sdma_hdr(&hdr->header); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + + version_major = le16_to_cpu(hdr->header.header_version_major); + version_minor = le16_to_cpu(hdr->header.header_version_minor); + + if (version_major == 1 && version_minor >= 1) { + const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = (const struct sdma_firmware_header_v1_1 *) hdr; + digest_size = le32_to_cpu(sdma_v1_1_hdr->digest_size); + } + + fw_size -= digest_size; + + fw_data = (const __le32 *) + (adev->sdma.instance[i].fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0); + + + for (j = 0; j < fw_size; j++) + { + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); + } + + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); + } + + sdma_v4_0_print_ucode_regs(adev); + + return 0; +} + +/** + * sdma_v4_0_start - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the DMA engines and enable them (VEGA10). + * Returns 0 for success, error for failure. + */ +static int sdma_v4_0_start(struct amdgpu_device *adev) +{ + int r = 0; + + if (amdgpu_sriov_vf(adev)) { + sdma_v4_0_ctx_switch_enable(adev, false); + sdma_v4_0_enable(adev, false); + + /* set RB registers */ + r = sdma_v4_0_gfx_resume(adev); + return r; + } + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + DRM_INFO("Loading via direct write\n"); + r = sdma_v4_0_load_microcode(adev); + if (r) + return r; + } + + /* unhalt the MEs */ + sdma_v4_0_enable(adev, true); + /* enable sdma ring preemption */ + sdma_v4_0_ctx_switch_enable(adev, true); + + /* start the gfx rings and rlc compute queues */ + r = sdma_v4_0_gfx_resume(adev); + if (r) + return r; + r = sdma_v4_0_rlc_resume(adev); + if (r) + return r; + + return 0; +} + +/** + * sdma_v4_0_ring_test_ring - simple async dma engine test + * + * @ring: amdgpu_ring structure holding ring information + * + * Test the DMA engine by writing using it to write an + * value to memory. (VEGA10). + * Returns 0 for success, error for failure. + */ +static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + unsigned i; + unsigned index; + int r; + u32 tmp; + u64 gpu_addr; + + DRM_INFO("In Ring test func\n"); + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ring_alloc(ring, 5); + if (r) { + DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + amdgpu_wb_free(adev, index); + return r; + } + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); + amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); + amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) { + break; + } + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + amdgpu_wb_free(adev, index); + + return r; +} + +/** + * sdma_v4_0_ring_test_ib - test an IB on the DMA engine + * + * @ring: amdgpu_ring structure holding ring information + * + * Test a simple IB in the DMA ring (VEGA10). + * Returns 0 on success, error on failure. + */ +static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + struct dma_fence *f = NULL; + unsigned index; + long r; + u32 tmp = 0; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + memset(&ib, 0, sizeof(ib)); + r = amdgpu_ib_get(adev, NULL, 256, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + goto err0; + } + + ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + ib.ptr[1] = lower_32_bits(gpu_addr); + ib.ptr[2] = upper_32_bits(gpu_addr); + ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); + ib.ptr[4] = 0xDEADBEEF; + ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.length_dw = 8; + + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + if (r) + goto err1; + + r = dma_fence_wait_timeout(f, false, timeout); + if (r == 0) { + DRM_ERROR("amdgpu: IB test timed out\n"); + r = -ETIMEDOUT; + goto err1; + } else if (r < 0) { + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + goto err1; + } + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) { + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + r = 0; + } else { + DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); + r = -EINVAL; + } +err1: + amdgpu_ib_free(adev, &ib, NULL); + dma_fence_put(f); +err0: + amdgpu_wb_free(adev, index); + return r; +} + + +/** + * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @src: src addr to copy from + * @count: number of page entries to update + * + * Update PTEs by copying them from the GART using sDMA (VEGA10). + */ +static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, + uint64_t pe, uint64_t src, + unsigned count) +{ + unsigned bytes = count * 8; + + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + ib->ptr[ib->length_dw++] = bytes - 1; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(src); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + +} + +/** + * sdma_v4_0_vm_write_pte - update PTEs by writing them manually + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update PTEs by writing them manually using sDMA (VEGA10). + */ +static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, + uint64_t value, unsigned count, + uint32_t incr) +{ + unsigned ndw = count * 2; + + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = ndw - 1; + for (; ndw > 0; ndw -= 2) { + ib->ptr[ib->length_dw++] = lower_32_bits(value); + ib->ptr[ib->length_dw++] = upper_32_bits(value); + value += incr; + } +} + +/** + * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update the page tables using sDMA (VEGA10). + */ +static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint64_t flags) +{ + /* for physically contiguous pages (vram) */ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); + ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ +} + +/** + * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw + * + * @ib: indirect buffer to fill with padding + * + */ +static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) +{ + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); + u32 pad_count; + int i; + + pad_count = (8 - (ib->length_dw & 0x7)) % 8; + for (i = 0; i < pad_count; i++) + if (sdma && sdma->burst_nop && (i == 0)) + ib->ptr[ib->length_dw++] = + SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | + SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); + else + ib->ptr[ib->length_dw++] = + SDMA_PKT_HEADER_OP(SDMA_OP_NOP); +} + + +/** + * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline + * + * @ring: amdgpu_ring pointer + * + * Make sure all previous operations are completed (CIK). + */ +static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +{ + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; + + /* wait for idle */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ + SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + amdgpu_ring_write(ring, seq); /* reference */ + amdgpu_ring_write(ring, 0xfffffff); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ +} + + +/** + * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA + * + * @ring: amdgpu_ring pointer + * @vm: amdgpu_vm pointer + * + * Update the page table base and flush the VM TLB + * using sDMA (VEGA10). + */ +static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + unsigned eng = ring->idx; + unsigned i; + + pd_addr = pd_addr | 0x1; /* valid bit */ + /* now only use physical base address of PDE and valid */ + BUG_ON(pd_addr & 0xFFFF00000000003EULL); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; + uint32_t req = hub->get_invalidate_req(vm_id); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2); + amdgpu_ring_write(ring, upper_32_bits(pd_addr)); + + /* flush TLB */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng); + amdgpu_ring_write(ring, req); + + /* wait for flush */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ + amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 1 << vm_id); /* reference */ + amdgpu_ring_write(ring, 1 << vm_id); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); + } +} + +static int sdma_v4_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->sdma.num_instances = 2; + + sdma_v4_0_set_ring_funcs(adev); + sdma_v4_0_set_buffer_funcs(adev); + sdma_v4_0_set_vm_pte_funcs(adev); + sdma_v4_0_set_irq_funcs(adev); + + return 0; +} + + +static int sdma_v4_0_sw_init(void *handle) +{ + struct amdgpu_ring *ring; + int r, i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* SDMA trap event */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224, + &adev->sdma.trap_irq); + if (r) + return r; + + /* SDMA trap event */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224, + &adev->sdma.trap_irq); + if (r) + return r; + + r = sdma_v4_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load sdma firmware!\n"); + return r; + } + + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + ring->ring_obj = NULL; + ring->use_doorbell = true; + + DRM_INFO("use_doorbell being set to: [%s]\n", + ring->use_doorbell?"true":"false"); + + ring->doorbell_index = (i == 0) ? + (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset + : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset + + sprintf(ring->name, "sdma%d", i); + r = amdgpu_ring_init(adev, ring, 1024, + &adev->sdma.trap_irq, + (i == 0) ? + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); + if (r) + return r; + } + + return r; +} + +static int sdma_v4_0_sw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ring_fini(&adev->sdma.instance[i].ring); + + return 0; +} + +static int sdma_v4_0_hw_init(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + sdma_v4_0_init_golden_registers(adev); + + r = sdma_v4_0_start(adev); + if (r) + return r; + + return r; +} + +static int sdma_v4_0_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_sriov_vf(adev)) + return 0; + + sdma_v4_0_ctx_switch_enable(adev, false); + sdma_v4_0_enable(adev, false); + + return 0; +} + +static int sdma_v4_0_suspend(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return sdma_v4_0_hw_fini(adev); +} + +static int sdma_v4_0_resume(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return sdma_v4_0_hw_init(adev); +} + +static bool sdma_v4_0_is_idle(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 i; + for (i = 0; i < adev->sdma.num_instances; i++) { + u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG)); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + return false; + } + + return true; +} + +static int sdma_v4_0_wait_for_idle(void *handle) +{ + unsigned i; + u32 sdma0,sdma1; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + for (i = 0; i < adev->usec_timeout; i++) { + sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG)); + sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG)); + + if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static int sdma_v4_0_soft_reset(void *handle) +{ + /* todo */ + + return 0; +} + +static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 sdma_cntl; + + u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? + sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) : + sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL); + + sdma_cntl = RREG32(reg_offset); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); + WREG32(reg_offset, sdma_cntl); + + return 0; +} + +static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: SDMA trap\n"); + switch (entry->client_id) { + case AMDGPU_IH_CLIENTID_SDMA0: + switch (entry->ring_id) { + case 0: + amdgpu_fence_process(&adev->sdma.instance[0].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + case 3: + /* XXX page queue*/ + break; + } + break; + case AMDGPU_IH_CLIENTID_SDMA1: + switch (entry->ring_id) { + case 0: + amdgpu_fence_process(&adev->sdma.instance[1].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + case 3: + /* XXX page queue*/ + break; + } + break; + } + return 0; +} + +static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in SDMA command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + + +static void sdma_v4_0_update_medium_grain_clock_gating( + struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, def; + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { + /* enable sdma0 clock gating */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); + data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); + + if (adev->asic_type == CHIP_VEGA10) { + def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); + data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); + if(def != data) + WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); + } + } else { + /* disable sdma0 clock gating */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); + data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); + + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); + + if (adev->asic_type == CHIP_VEGA10) { + def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); + data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | + SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); + } + } +} + + +static void sdma_v4_0_update_medium_grain_light_sleep( + struct amdgpu_device *adev, + bool enable) +{ + uint32_t data, def; + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { + /* 1-not override: enable sdma0 mem light sleep */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); + data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); + + /* 1-not override: enable sdma1 mem light sleep */ + if (adev->asic_type == CHIP_VEGA10) { + def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); + data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); + } + } else { + /* 0-override:disable sdma0 mem light sleep */ + def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); + data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); + + /* 0-override:disable sdma1 mem light sleep */ + if (adev->asic_type == CHIP_VEGA10) { + def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); + data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (def != data) + WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); + } + } +} + +static int sdma_v4_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_sriov_vf(adev)) + return 0; + + switch (adev->asic_type) { + case CHIP_VEGA10: + sdma_v4_0_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + sdma_v4_0_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + break; + default: + break; + } + return 0; +} + +static int sdma_v4_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int data; + + if (amdgpu_sriov_vf(adev)) + *flags = 0; + + /* AMD_CG_SUPPORT_SDMA_MGCG */ + data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); + if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) + *flags |= AMD_CG_SUPPORT_SDMA_MGCG; + + /* AMD_CG_SUPPORT_SDMA_LS */ + data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); + if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) + *flags |= AMD_CG_SUPPORT_SDMA_LS; +} + +const struct amd_ip_funcs sdma_v4_0_ip_funcs = { + .name = "sdma_v4_0", + .early_init = sdma_v4_0_early_init, + .late_init = NULL, + .sw_init = sdma_v4_0_sw_init, + .sw_fini = sdma_v4_0_sw_fini, + .hw_init = sdma_v4_0_hw_init, + .hw_fini = sdma_v4_0_hw_fini, + .suspend = sdma_v4_0_suspend, + .resume = sdma_v4_0_resume, + .is_idle = sdma_v4_0_is_idle, + .wait_for_idle = sdma_v4_0_wait_for_idle, + .soft_reset = sdma_v4_0_soft_reset, + .set_clockgating_state = sdma_v4_0_set_clockgating_state, + .set_powergating_state = sdma_v4_0_set_powergating_state, + .get_clockgating_state = sdma_v4_0_get_clockgating_state, +}; + +static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, + .get_rptr = sdma_v4_0_ring_get_rptr, + .get_wptr = sdma_v4_0_ring_get_wptr, + .set_wptr = sdma_v4_0_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v4_0_ring_emit_hdp_flush */ + 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */ + 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ + 36 + /* sdma_v4_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ + .emit_ib = sdma_v4_0_ring_emit_ib, + .emit_fence = sdma_v4_0_ring_emit_fence, + .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, + .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate, + .test_ring = sdma_v4_0_ring_test_ring, + .test_ib = sdma_v4_0_ring_test_ib, + .insert_nop = sdma_v4_0_ring_insert_nop, + .pad_ib = sdma_v4_0_ring_pad_ib, +}; + +static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { + .set = sdma_v4_0_set_trap_irq_state, + .process = sdma_v4_0_process_trap_irq, +}; + +static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { + .process = sdma_v4_0_process_illegal_inst_irq, +}; + +static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; + adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; +} + +/** + * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_offset: src GPU address + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Copy GPU buffers using the DMA engine (VEGA10). + * Used by the amdgpu ttm implementation to move pages if + * registered as the asic copy callback. + */ +static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count) +{ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + ib->ptr[ib->length_dw++] = byte_count - 1; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); +} + +/** + * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_data: value to write to buffer + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Fill GPU buffers using the DMA engine (VEGA10). + */ +static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, + uint32_t src_data, + uint64_t dst_offset, + uint32_t byte_count) +{ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = src_data; + ib->ptr[ib->length_dw++] = byte_count - 1; +} + +static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { + .copy_max_bytes = 0x400000, + .copy_num_dw = 7, + .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, + + .fill_max_bytes = 0x400000, + .fill_num_dw = 5, + .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, +}; + +static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) +{ + if (adev->mman.buffer_funcs == NULL) { + adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; + } +} + +static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { + .copy_pte = sdma_v4_0_vm_copy_pte, + .write_pte = sdma_v4_0_vm_write_pte, + .set_pte_pde = sdma_v4_0_vm_set_pte_pde, +}; + +static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) +{ + unsigned i; + + if (adev->vm_manager.vm_pte_funcs == NULL) { + adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; + for (i = 0; i < adev->sdma.num_instances; i++) + adev->vm_manager.vm_pte_rings[i] = + &adev->sdma.instance[i].ring; + + adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; + } +} + +const struct amdgpu_ip_block_version sdma_v4_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 4, + .minor = 0, + .rev = 0, + .funcs = &sdma_v4_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h new file mode 100644 index 000000000000..5c5a7479a062 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h @@ -0,0 +1,30 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SDMA_V4_0_H__ +#define __SDMA_V4_0_H__ + +extern const struct amd_ip_funcs sdma_v4_0_ip_funcs; +extern const struct amdgpu_ip_block_version sdma_v4_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index b71e3faa40db..c0b1aabf282f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -45,6 +45,7 @@ #include "gmc/gmc_6_0_d.h" #include "dce/dce_6_0_d.h" #include "uvd/uvd_4_0_d.h" +#include "bif/bif_3_0_d.h" static const u32 tahiti_golden_registers[] = { @@ -1155,6 +1156,11 @@ static int si_asic_reset(struct amdgpu_device *adev) return 0; } +static u32 si_get_config_memsize(struct amdgpu_device *adev) +{ + return RREG32(mmCONFIG_MEMSIZE); +} + static void si_vga_set_state(struct amdgpu_device *adev, bool state) { uint32_t temp; @@ -1206,6 +1212,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs = .get_xclk = &si_get_xclk, .set_uvd_clocks = &si_set_uvd_clocks, .set_vce_clocks = NULL, + .get_config_memsize = &si_get_config_memsize, }; static uint32_t si_get_rev_id(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 3372a071bb85..112969f3301a 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -37,12 +37,12 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); static void si_dma_set_irq_funcs(struct amdgpu_device *adev); -static uint32_t si_dma_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->rptr_offs>>2]; } -static uint32_t si_dma_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; @@ -55,7 +55,8 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; - WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); + WREG32(DMA_RB_WPTR + sdma_offsets[me], + (lower_32_bits(ring->wptr) << 2) & 0x3fffc); } static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, @@ -65,7 +66,7 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. * Pad as necessary with NOPs. */ - while ((ring->wptr & 7) != 5) + while ((lower_32_bits(ring->wptr) & 7) != 5) amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0)); amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); @@ -184,7 +185,7 @@ static int si_dma_start(struct amdgpu_device *adev) WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); ring->wptr = 0; - WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); ring->ready = true; @@ -397,7 +398,7 @@ static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, - uint32_t incr, uint32_t flags) + uint32_t incr, uint64_t flags) { uint64_t value; unsigned ndw; @@ -416,8 +417,8 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); ib->ptr[ib->length_dw++] = pe; /* dst addr */ ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; - ib->ptr[ib->length_dw++] = flags; /* mask */ - ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); ib->ptr[ib->length_dw++] = value; /* value */ ib->ptr[ib->length_dw++] = upper_32_bits(value); ib->ptr[ib->length_dw++] = incr; /* increment size */ @@ -516,12 +517,12 @@ static int si_dma_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* DMA0 trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq); if (r) return r; /* DMA1 trap event */ - r = amdgpu_irq_add_id(adev, 244, &adev->sdma.trap_irq_1); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1); if (r) return r; @@ -766,6 +767,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, .align_mask = 0xf, .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), + .support_64bit_ptrs = false, .get_rptr = si_dma_ring_get_rptr, .get_wptr = si_dma_ring_get_wptr, .set_wptr = si_dma_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index c5dec210d529..7c1c5d127281 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -7700,11 +7700,11 @@ static int si_dpm_sw_init(void *handle) int ret; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); + ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); if (ret) return ret; - ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); + ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); if (ret) return ret; @@ -7982,6 +7982,46 @@ static int si_check_state_equal(struct amdgpu_device *adev, return 0; } +static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx, + void *value, int *size) +{ + struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); + struct amdgpu_ps *rps = &eg_pi->current_rps; + struct si_ps *ps = si_get_ps(rps); + uint32_t sclk, mclk; + u32 pl_index = + (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> + CURRENT_STATE_INDEX_SHIFT; + + /* size must be at least 4 bytes for all sensors */ + if (*size < 4) + return -EINVAL; + + switch (idx) { + case AMDGPU_PP_SENSOR_GFX_SCLK: + if (pl_index < ps->performance_level_count) { + sclk = ps->performance_levels[pl_index].sclk; + *((uint32_t *)value) = sclk; + *size = 4; + return 0; + } + return -EINVAL; + case AMDGPU_PP_SENSOR_GFX_MCLK: + if (pl_index < ps->performance_level_count) { + mclk = ps->performance_levels[pl_index].mclk; + *((uint32_t *)value) = mclk; + *size = 4; + return 0; + } + return -EINVAL; + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = si_dpm_get_temp(adev); + *size = 4; + return 0; + default: + return -EINVAL; + } +} const struct amd_ip_funcs si_dpm_ip_funcs = { .name = "si_dpm", @@ -8018,6 +8058,7 @@ static const struct amdgpu_dpm_funcs si_dpm_funcs = { .get_fan_speed_percent = &si_dpm_get_fan_speed_percent, .check_state_equal = &si_check_state_equal, .get_vce_clock_state = amdgpu_get_vce_clock_state, + .read_sensor = &si_dpm_read_sensor, }; static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 81f90800ba73..e66084211c74 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -129,8 +129,9 @@ static void si_ih_decode_iv(struct amdgpu_device *adev, dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; entry->src_id = dw[0] & 0xff; - entry->src_data = dw[1] & 0xfffffff; + entry->src_data[0] = dw[1] & 0xfffffff; entry->ring_id = dw[2] & 0xff; entry->vm_id = (dw[2] >> 8) & 0xff; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c new file mode 100644 index 000000000000..bb14a45997b5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -0,0 +1,871 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include <linux/firmware.h> +#include <linux/slab.h> +#include <linux/module.h> +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "amdgpu_ih.h" +#include "amdgpu_uvd.h" +#include "amdgpu_vce.h" +#include "amdgpu_ucode.h" +#include "amdgpu_psp.h" +#include "atom.h" +#include "amd_pcie.h" + +#include "vega10/soc15ip.h" +#include "vega10/UVD/uvd_7_0_offset.h" +#include "vega10/GC/gc_9_0_offset.h" +#include "vega10/GC/gc_9_0_sh_mask.h" +#include "vega10/SDMA0/sdma0_4_0_offset.h" +#include "vega10/SDMA1/sdma1_4_0_offset.h" +#include "vega10/HDP/hdp_4_0_offset.h" +#include "vega10/HDP/hdp_4_0_sh_mask.h" +#include "vega10/MP/mp_9_0_offset.h" +#include "vega10/MP/mp_9_0_sh_mask.h" +#include "vega10/SMUIO/smuio_9_0_offset.h" +#include "vega10/SMUIO/smuio_9_0_sh_mask.h" + +#include "soc15.h" +#include "soc15_common.h" +#include "gfx_v9_0.h" +#include "gmc_v9_0.h" +#include "gfxhub_v1_0.h" +#include "mmhub_v1_0.h" +#include "vega10_ih.h" +#include "sdma_v4_0.h" +#include "uvd_v7_0.h" +#include "vce_v4_0.h" +#include "amdgpu_powerplay.h" +#include "dce_virtual.h" +#include "mxgpu_ai.h" + +MODULE_FIRMWARE("amdgpu/vega10_smc.bin"); + +#define mmFabricConfigAccessControl 0x0410 +#define mmFabricConfigAccessControl_BASE_IDX 0 +#define mmFabricConfigAccessControl_DEFAULT 0x00000000 +//FabricConfigAccessControl +#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0 +#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1 +#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10 +#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L +#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L +#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L + + +#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc +#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0 +//DF_PIE_AON0_DfGlobalClkGater +#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0 +#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL + +enum { + DF_MGCG_DISABLE = 0, + DF_MGCG_ENABLE_00_CYCLE_DELAY =1, + DF_MGCG_ENABLE_01_CYCLE_DELAY =2, + DF_MGCG_ENABLE_15_CYCLE_DELAY =13, + DF_MGCG_ENABLE_31_CYCLE_DELAY =14, + DF_MGCG_ENABLE_63_CYCLE_DELAY =15 +}; + +#define mmMP0_MISC_CGTT_CTRL0 0x01b9 +#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 +#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba +#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 + +/* + * Indirect registers accessor + */ +static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags, address, data; + u32 r; + struct nbio_pcie_index_data *nbio_pcie_id; + + if (adev->asic_type == CHIP_VEGA10) + nbio_pcie_id = &nbio_v6_1_pcie_index_data; + + address = nbio_pcie_id->index_offset; + data = nbio_pcie_id->data_offset; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(address, reg); + (void)RREG32(address); + r = RREG32(data); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + return r; +} + +static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags, address, data; + struct nbio_pcie_index_data *nbio_pcie_id; + + if (adev->asic_type == CHIP_VEGA10) + nbio_pcie_id = &nbio_v6_1_pcie_index_data; + + address = nbio_pcie_id->index_offset; + data = nbio_pcie_id->data_offset; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(address, reg); + (void)RREG32(address); + WREG32(data, v); + (void)RREG32(data); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags, address, data; + u32 r; + + address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); + data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); + + spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + WREG32(address, ((reg) & 0x1ff)); + r = RREG32(data); + spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + return r; +} + +static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags, address, data; + + address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); + data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); + + spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + WREG32(address, ((reg) & 0x1ff)); + WREG32(data, (v)); + spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); +} + +static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags, address, data; + u32 r; + + address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); + data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); + + spin_lock_irqsave(&adev->didt_idx_lock, flags); + WREG32(address, (reg)); + r = RREG32(data); + spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + return r; +} + +static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags, address, data; + + address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); + data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); + + spin_lock_irqsave(&adev->didt_idx_lock, flags); + WREG32(address, (reg)); + WREG32(data, (v)); + spin_unlock_irqrestore(&adev->didt_idx_lock, flags); +} + +static u32 soc15_get_config_memsize(struct amdgpu_device *adev) +{ + return nbio_v6_1_get_memsize(adev); +} + +static const u32 vega10_golden_init[] = +{ +}; + +static void soc15_init_golden_registers(struct amdgpu_device *adev) +{ + /* Some of the registers might be dependent on GRBM_GFX_INDEX */ + mutex_lock(&adev->grbm_idx_mutex); + + switch (adev->asic_type) { + case CHIP_VEGA10: + amdgpu_program_register_sequence(adev, + vega10_golden_init, + (const u32)ARRAY_SIZE(vega10_golden_init)); + break; + default: + break; + } + mutex_unlock(&adev->grbm_idx_mutex); +} +static u32 soc15_get_xclk(struct amdgpu_device *adev) +{ + if (adev->asic_type == CHIP_VEGA10) + return adev->clock.spll.reference_freq/4; + else + return adev->clock.spll.reference_freq; +} + + +void soc15_grbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid) +{ + u32 grbm_gfx_cntl = 0; + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); +} + +static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) +{ + /* todo */ +} + +static bool soc15_read_disabled_bios(struct amdgpu_device *adev) +{ + /* todo */ + return false; +} + +static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, + u8 *bios, u32 length_bytes) +{ + u32 *dw_ptr; + u32 i, length_dw; + + if (bios == NULL) + return false; + if (length_bytes == 0) + return false; + /* APU vbios image is part of sbios image */ + if (adev->flags & AMD_IS_APU) + return false; + + dw_ptr = (u32 *)bios; + length_dw = ALIGN(length_bytes, 4) / 4; + + /* set rom index to 0 */ + WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); + /* read out the rom data */ + for (i = 0; i < length_dw; i++) + dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); + + return true; +} + +static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = { + /* todo */ +}; + +static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = { + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false}, + { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false}, + { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false}, + { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false}, + { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false}, + { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false}, +}; + +static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset) +{ + uint32_t val; + + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); + + val = RREG32(reg_offset); + + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + return val; +} + +static uint32_t soc15_get_register_value(struct amdgpu_device *adev, + bool indexed, u32 se_num, + u32 sh_num, u32 reg_offset) +{ + if (indexed) { + return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); + } else { + switch (reg_offset) { + case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG): + return adev->gfx.config.gb_addr_config; + default: + return RREG32(reg_offset); + } + } +} + +static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset, u32 *value) +{ + struct amdgpu_allowed_register_entry *asic_register_table = NULL; + struct amdgpu_allowed_register_entry *asic_register_entry; + uint32_t size, i; + + *value = 0; + switch (adev->asic_type) { + case CHIP_VEGA10: + asic_register_table = vega10_allowed_read_registers; + size = ARRAY_SIZE(vega10_allowed_read_registers); + break; + default: + return -EINVAL; + } + + if (asic_register_table) { + for (i = 0; i < size; i++) { + asic_register_entry = asic_register_table + i; + if (reg_offset != asic_register_entry->reg_offset) + continue; + if (!asic_register_entry->untouched) + *value = soc15_get_register_value(adev, + asic_register_entry->grbm_indexed, + se_num, sh_num, reg_offset); + return 0; + } + } + + for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { + if (reg_offset != soc15_allowed_read_registers[i].reg_offset) + continue; + + if (!soc15_allowed_read_registers[i].untouched) + *value = soc15_get_register_value(adev, + soc15_allowed_read_registers[i].grbm_indexed, + se_num, sh_num, reg_offset); + return 0; + } + return -EINVAL; +} + +static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev) +{ + u32 i; + + dev_info(adev->dev, "GPU pci config reset\n"); + + /* disable BM */ + pci_clear_master(adev->pdev); + /* reset */ + amdgpu_pci_config_reset(adev); + + udelay(100); + + /* wait for asic to come out of reset */ + for (i = 0; i < adev->usec_timeout; i++) { + if (nbio_v6_1_get_memsize(adev) != 0xffffffff) + break; + udelay(1); + } + +} + +static int soc15_asic_reset(struct amdgpu_device *adev) +{ + amdgpu_atombios_scratch_regs_engine_hung(adev, true); + + soc15_gpu_pci_config_reset(adev); + + amdgpu_atombios_scratch_regs_engine_hung(adev, false); + + return 0; +} + +/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, + u32 cntl_reg, u32 status_reg) +{ + return 0; +}*/ + +static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) +{ + /*int r; + + r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); + if (r) + return r; + + r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); + */ + return 0; +} + +static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) +{ + /* todo */ + + return 0; +} + +static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) +{ + if (pci_is_root_bus(adev->pdev->bus)) + return; + + if (amdgpu_pcie_gen2 == 0) + return; + + if (adev->flags & AMD_IS_APU) + return; + + if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) + return; + + /* todo */ +} + +static void soc15_program_aspm(struct amdgpu_device *adev) +{ + + if (amdgpu_aspm == 0) + return; + + /* todo */ +} + +static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) +{ + nbio_v6_1_enable_doorbell_aperture(adev, enable); + nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable); +} + +static const struct amdgpu_ip_block_version vega10_common_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &soc15_common_ip_funcs, +}; + +int soc15_set_ip_blocks(struct amdgpu_device *adev) +{ + nbio_v6_1_detect_hw_virt(adev); + + if (amdgpu_sriov_vf(adev)) + adev->virt.ops = &xgpu_ai_virt_ops; + + switch (adev->asic_type) { + case CHIP_VEGA10: + amdgpu_ip_block_add(adev, &vega10_common_ip_block); + amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block); + amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block); + amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); + amdgpu_ip_block_add(adev, &vega10_ih_ip_block); + amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); + if (!amdgpu_sriov_vf(adev)) + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); + if (!amdgpu_sriov_vf(adev)) + amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); + amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); + break; + default: + return -EINVAL; + } + + return 0; +} + +static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) +{ + return nbio_v6_1_get_rev_id(adev); +} + + +int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev) +{ + /* to be implemented in MC IP*/ + return 0; +} + +static const struct amdgpu_asic_funcs soc15_asic_funcs = +{ + .read_disabled_bios = &soc15_read_disabled_bios, + .read_bios_from_rom = &soc15_read_bios_from_rom, + .read_register = &soc15_read_register, + .reset = &soc15_asic_reset, + .set_vga_state = &soc15_vga_set_state, + .get_xclk = &soc15_get_xclk, + .set_uvd_clocks = &soc15_set_uvd_clocks, + .set_vce_clocks = &soc15_set_vce_clocks, + .get_config_memsize = &soc15_get_config_memsize, +}; + +static int soc15_common_early_init(void *handle) +{ + bool psp_enabled = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->smc_rreg = NULL; + adev->smc_wreg = NULL; + adev->pcie_rreg = &soc15_pcie_rreg; + adev->pcie_wreg = &soc15_pcie_wreg; + adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; + adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; + adev->didt_rreg = &soc15_didt_rreg; + adev->didt_wreg = &soc15_didt_wreg; + + adev->asic_funcs = &soc15_asic_funcs; + + if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && + (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) + psp_enabled = true; + + if (amdgpu_sriov_vf(adev)) { + amdgpu_virt_init_setting(adev); + } + + /* + * nbio need be used for both sdma and gfx9, but only + * initializes once + */ + switch(adev->asic_type) { + case CHIP_VEGA10: + nbio_v6_1_init(adev); + break; + default: + return -EINVAL; + } + + adev->rev_id = soc15_get_rev_id(adev); + adev->external_rev_id = 0xFF; + switch (adev->asic_type) { + case CHIP_VEGA10: + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_DRM_MGCG | + AMD_CG_SUPPORT_DRM_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_DF_MGCG | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS; + adev->pg_flags = 0; + adev->external_rev_id = 0x1; + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); + + amdgpu_get_pcie_info(adev); + + return 0; +} + +static int soc15_common_sw_init(void *handle) +{ + return 0; +} + +static int soc15_common_sw_fini(void *handle) +{ + return 0; +} + +static int soc15_common_hw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* move the golden regs per IP block */ + soc15_init_golden_registers(adev); + /* enable pcie gen2/3 link */ + soc15_pcie_gen3_enable(adev); + /* enable aspm */ + soc15_program_aspm(adev); + /* enable the doorbell aperture */ + soc15_enable_doorbell_aperture(adev, true); + + return 0; +} + +static int soc15_common_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* disable the doorbell aperture */ + soc15_enable_doorbell_aperture(adev, false); + + return 0; +} + +static int soc15_common_suspend(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return soc15_common_hw_fini(adev); +} + +static int soc15_common_resume(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return soc15_common_hw_init(adev); +} + +static bool soc15_common_is_idle(void *handle) +{ + return true; +} + +static int soc15_common_wait_for_idle(void *handle) +{ + return 0; +} + +static int soc15_common_soft_reset(void *handle) +{ + return 0; +} + +static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) + data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; + else + data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; + + if (def != data) + WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); +} + +static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) + data &= ~(0x01000000 | + 0x02000000 | + 0x04000000 | + 0x08000000 | + 0x10000000 | + 0x20000000 | + 0x40000000 | + 0x80000000); + else + data |= (0x01000000 | + 0x02000000 | + 0x04000000 | + 0x08000000 | + 0x10000000 | + 0x20000000 | + 0x40000000 | + 0x80000000); + + if (def != data) + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); +} + +static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) + data |= 1; + else + data &= ~1; + + if (def != data) + WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); +} + +static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) + data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); + else + data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; + + if (def != data) + WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); +} + +static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t data; + + /* Put DF on broadcast mode */ + data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl)); + data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; + WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) { + data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); + data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; + data |= DF_MGCG_ENABLE_15_CYCLE_DELAY; + WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data); + } else { + data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); + data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; + data |= DF_MGCG_DISABLE; + WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data); + } + + WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), + mmFabricConfigAccessControl_DEFAULT); +} + +static int soc15_common_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_sriov_vf(adev)) + return 0; + + switch (adev->asic_type) { + case CHIP_VEGA10: + nbio_v6_1_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + nbio_v6_1_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_hdp_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_drm_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_drm_light_sleep(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_rom_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + soc15_update_df_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE ? true : false); + break; + default: + break; + } + return 0; +} + +static void soc15_common_get_clockgating_state(void *handle, u32 *flags) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int data; + + if (amdgpu_sriov_vf(adev)) + *flags = 0; + + nbio_v6_1_get_clockgating_state(adev, flags); + + /* AMD_CG_SUPPORT_HDP_LS */ + data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); + if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_HDP_LS; + + /* AMD_CG_SUPPORT_DRM_MGCG */ + data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); + if (!(data & 0x01000000)) + *flags |= AMD_CG_SUPPORT_DRM_MGCG; + + /* AMD_CG_SUPPORT_DRM_LS */ + data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); + if (data & 0x1) + *flags |= AMD_CG_SUPPORT_DRM_LS; + + /* AMD_CG_SUPPORT_ROM_MGCG */ + data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); + if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) + *flags |= AMD_CG_SUPPORT_ROM_MGCG; + + /* AMD_CG_SUPPORT_DF_MGCG */ + data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); + if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY) + *flags |= AMD_CG_SUPPORT_DF_MGCG; +} + +static int soc15_common_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + /* todo */ + return 0; +} + +const struct amd_ip_funcs soc15_common_ip_funcs = { + .name = "soc15_common", + .early_init = soc15_common_early_init, + .late_init = NULL, + .sw_init = soc15_common_sw_init, + .sw_fini = soc15_common_sw_fini, + .hw_init = soc15_common_hw_init, + .hw_fini = soc15_common_hw_fini, + .suspend = soc15_common_suspend, + .resume = soc15_common_resume, + .is_idle = soc15_common_is_idle, + .wait_for_idle = soc15_common_wait_for_idle, + .soft_reset = soc15_common_soft_reset, + .set_clockgating_state = soc15_common_set_clockgating_state, + .set_powergating_state = soc15_common_set_powergating_state, + .get_clockgating_state= soc15_common_get_clockgating_state, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h new file mode 100644 index 000000000000..378a46da585a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SOC15_H__ +#define __SOC15_H__ + +#include "nbio_v6_1.h" + +extern const struct amd_ip_funcs soc15_common_ip_funcs; + +void soc15_grbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid); +int soc15_set_ip_blocks(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h new file mode 100644 index 000000000000..2b96c806baa1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -0,0 +1,57 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SOC15_COMMON_H__ +#define __SOC15_COMMON_H__ + +struct nbio_hdp_flush_reg { + u32 hdp_flush_req_offset; + u32 hdp_flush_done_offset; + u32 ref_and_mask_cp0; + u32 ref_and_mask_cp1; + u32 ref_and_mask_cp2; + u32 ref_and_mask_cp3; + u32 ref_and_mask_cp4; + u32 ref_and_mask_cp5; + u32 ref_and_mask_cp6; + u32 ref_and_mask_cp7; + u32 ref_and_mask_cp8; + u32 ref_and_mask_cp9; + u32 ref_and_mask_sdma0; + u32 ref_and_mask_sdma1; +}; + +struct nbio_pcie_index_data { + u32 index_offset; + u32 data_offset; +}; +// Register Access Macro +#define SOC15_REG_OFFSET(ip, inst, reg) (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ + (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ + (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ + (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ + (ip##_BASE__INST##inst##_SEG4 + reg))))) + +#endif + + diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h new file mode 100644 index 000000000000..75403c7c8c9e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -0,0 +1,288 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SOC15_H +#define SOC15_H + +#define GFX9_NUM_GFX_RINGS 1 +#define GFX9_NUM_COMPUTE_RINGS 8 + +/* + * PM4 + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + ((reg) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_SET_BASE 0x11 +#define PACKET3_BASE_INDEX(x) ((x) << 0) +#define CE_PARTITION_BASE 3 +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ATOMIC_GDS 0x1D +#define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_INDIRECT_BUFFER_CONST 0x33 +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_DRAW_PREAMBLE 0x36 +#define PACKET3_WRITE_DATA 0x37 +#define WRITE_DATA_DST_SEL(x) ((x) << 8) + /* 0 - register + * 1 - memory (sync - via GRBM) + * 2 - gl2 + * 3 - gds + * 4 - reserved + * 5 - memory (async - direct) + */ +#define WR_ONE_ADDR (1 << 16) +#define WR_CONFIRM (1 << 20) +#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) + /* 0 - me + * 1 - pfp + * 2 - ce + */ +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) +# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ +# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) +# define PACKET3_SEM_SEL_WAIT (0x7 << 29) +#define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ +#define PACKET3_INDIRECT_BUFFER 0x3F +#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) +#define PACKET3_COPY_DATA 0x40 +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + */ +#define PACKET3_RELEASE_MEM 0x49 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) +#define EOP_TCL1_VOL_ACTION_EN (1 << 12) +#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ +#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ +#define EOP_TCL1_ACTION_EN (1 << 16) +#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ +#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */ + +#define DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit GPU counter value + * 4 - send 64bit sys counter value + */ +#define INT_SEL(x) ((x) << 24) + /* 0 - none + * 1 - interrupt only (DATA_SEL = 0) + * 2 - interrupt when data write is confirmed + */ +#define DST_SEL(x) ((x) << 16) + /* 0 - MC + * 1 - TC/L2 + */ + + + +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_DMA_DATA 0x50 +/* 1. header + * 2. CONTROL + * 3. SRC_ADDR_LO or DATA [31:0] + * 4. SRC_ADDR_HI [31:0] + * 5. DST_ADDR_LO [31:0] + * 6. DST_ADDR_HI [7:0] + * 7. COMMAND [30:21] | BYTE_COUNT [20:0] + */ +/* CONTROL */ +# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) + /* 0 - LRU + * 1 - Stream + */ +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) +/* COMMAND */ +# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +#define PACKET3_AQUIRE_MEM 0x58 +#define PACKET3_REWIND 0x59 +#define PACKET3_LOAD_UCONFIG_REG 0x5E +#define PACKET3_LOAD_SH_REG 0x5F +#define PACKET3_LOAD_CONFIG_REG 0x60 +#define PACKET3_LOAD_CONTEXT_REG 0x61 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_SET_QUEUE_REG 0x78 +#define PACKET3_SET_UCONFIG_REG 0x79 +#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 +#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SCRATCH_RAM_WRITE 0x7D +#define PACKET3_SCRATCH_RAM_READ 0x7E +#define PACKET3_LOAD_CONST_RAM 0x80 +#define PACKET3_WRITE_CONST_RAM 0x81 +#define PACKET3_DUMP_CONST_RAM 0x83 +#define PACKET3_INCREMENT_CE_COUNTER 0x84 +#define PACKET3_INCREMENT_DE_COUNTER 0x85 +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 +#define PACKET3_SWITCH_BUFFER 0x8B +#define PACKET3_SET_RESOURCES 0xA0 +#define PACKET3_MAP_QUEUES 0xA2 + +#define VCE_CMD_NO_OP 0x00000000 +#define VCE_CMD_END 0x00000001 +#define VCE_CMD_IB 0x00000002 +#define VCE_CMD_FENCE 0x00000003 +#define VCE_CMD_TRAP 0x00000004 +#define VCE_CMD_IB_AUTO 0x00000005 +#define VCE_CMD_SEMAPHORE 0x00000006 + +#define VCE_CMD_IB_VM 0x00000102 +#define VCE_CMD_WAIT_GE 0x00000106 +#define VCE_CMD_UPDATE_PTB 0x00000107 +#define VCE_CMD_FLUSH_TLB 0x00000108 +#define VCE_CMD_REG_WRITE 0x00000109 +#define VCE_CMD_REG_WAIT 0x0000010a + +#define HEVC_ENC_CMD_NO_OP 0x00000000 +#define HEVC_ENC_CMD_END 0x00000001 +#define HEVC_ENC_CMD_FENCE 0x00000003 +#define HEVC_ENC_CMD_TRAP 0x00000004 +#define HEVC_ENC_CMD_IB_VM 0x00000102 +#define HEVC_ENC_CMD_REG_WRITE 0x00000109 +#define HEVC_ENC_CMD_REG_WAIT 0x0000010a + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 52b71ee58793..3a5097ac2bb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -238,8 +238,9 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev, dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; entry->src_id = dw[0] & 0xff; - entry->src_data = dw[1] & 0xfffffff; + entry->src_data[0] = dw[1] & 0xfffffff; entry->ring_id = dw[2] & 0xff; entry->vm_id = (dw[2] >> 8) & 0xff; entry->pas_id = (dw[2] >> 16) & 0xffff; @@ -288,7 +289,7 @@ static int tonga_ih_sw_init(void *handle) int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - r = amdgpu_ih_ring_init(adev, 4 * 1024, true); + r = amdgpu_ih_ring_init(adev, 64 * 1024, true); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index b34cefc7ebd5..9a4129d881aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -55,7 +55,7 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, * * Returns the current hardware read pointer */ -static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -69,7 +69,7 @@ static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) * * Returns the current hardware write pointer */ -static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -87,7 +87,7 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); } static int uvd_v4_2_early_init(void *handle) @@ -107,7 +107,7 @@ static int uvd_v4_2_sw_init(void *handle) int r; /* UVD TRAP */ - r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq); if (r) return r; @@ -367,7 +367,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev) WREG32(mmUVD_RBC_RB_RPTR, 0x0); ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); - WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); /* set the ring address */ WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); @@ -770,6 +770,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .type = AMDGPU_RING_TYPE_UVD, .align_mask = 0xf, .nop = PACKET0(mmUVD_NO_OP, 0), + .support_64bit_ptrs = false, .get_rptr = uvd_v4_2_ring_get_rptr, .get_wptr = uvd_v4_2_ring_get_wptr, .set_wptr = uvd_v4_2_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index ad8c02e423d4..e448f7d86bc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -51,7 +51,7 @@ static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, * * Returns the current hardware read pointer */ -static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -65,7 +65,7 @@ static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) * * Returns the current hardware write pointer */ -static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -83,7 +83,7 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); } static int uvd_v5_0_early_init(void *handle) @@ -103,7 +103,7 @@ static int uvd_v5_0_sw_init(void *handle) int r; /* UVD TRAP */ - r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq); if (r) return r; @@ -424,7 +424,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev) WREG32(mmUVD_RBC_RB_RPTR, 0); ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); - WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); @@ -879,6 +879,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .type = AMDGPU_RING_TYPE_UVD, .align_mask = 0xf, .nop = PACKET0(mmUVD_NO_OP, 0), + .support_64bit_ptrs = false, .get_rptr = uvd_v5_0_ring_get_rptr, .get_wptr = uvd_v5_0_ring_get_wptr, .set_wptr = uvd_v5_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 18a6de4e1512..5679a4249bd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -54,7 +54,7 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, * * Returns the current hardware read pointer */ -static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -68,7 +68,7 @@ static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) * * Returns the current hardware write pointer */ -static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -86,7 +86,7 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); } static int uvd_v6_0_early_init(void *handle) @@ -106,7 +106,7 @@ static int uvd_v6_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* UVD TRAP */ - r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq); if (r) return r; @@ -521,7 +521,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) WREG32(mmUVD_RBC_RB_RPTR, 0); ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); - WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); @@ -1068,8 +1068,12 @@ static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags) mutex_lock(&adev->pm.mutex); - if (RREG32_SMC(ixCURRENT_PG_STATUS) & - CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { + if (adev->flags & AMD_IS_APU) + data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); + else + data = RREG32_SMC(ixCURRENT_PG_STATUS); + + if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); goto out; } @@ -1108,6 +1112,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { .type = AMDGPU_RING_TYPE_UVD, .align_mask = 0xf, .nop = PACKET0(mmUVD_NO_OP, 0), + .support_64bit_ptrs = false, .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, @@ -1134,6 +1139,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_UVD, .align_mask = 0xf, .nop = PACKET0(mmUVD_NO_OP, 0), + .support_64bit_ptrs = false, .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c new file mode 100644 index 000000000000..13f52e0af9b8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -0,0 +1,1543 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <linux/firmware.h> +#include <drm/drmP.h> +#include "amdgpu.h" +#include "amdgpu_uvd.h" +#include "soc15d.h" +#include "soc15_common.h" + +#include "vega10/soc15ip.h" +#include "vega10/UVD/uvd_7_0_offset.h" +#include "vega10/UVD/uvd_7_0_sh_mask.h" +#include "vega10/NBIF/nbif_6_1_offset.h" +#include "vega10/HDP/hdp_4_0_offset.h" +#include "vega10/MMHUB/mmhub_1_0_offset.h" +#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" + +static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); +static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); +static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); +static int uvd_v7_0_start(struct amdgpu_device *adev); +static void uvd_v7_0_stop(struct amdgpu_device *adev); + +/** + * uvd_v7_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR)); +} + +/** + * uvd_v7_0_enc_ring_get_rptr - get enc read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware enc read pointer + */ +static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->uvd.ring_enc[0]) + return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR)); + else + return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2)); +} + +/** + * uvd_v7_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR)); +} + +/** + * uvd_v7_0_enc_ring_get_wptr - get enc write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware enc write pointer + */ +static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->uvd.ring_enc[0]) + return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR)); + else + return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2)); +} + +/** + * uvd_v7_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr)); +} + +/** + * uvd_v7_0_enc_ring_set_wptr - set enc write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the enc write pointer to the hardware + */ +static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->uvd.ring_enc[0]) + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), + lower_32_bits(ring->wptr)); + else + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), + lower_32_bits(ring->wptr)); +} + +/** + * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working + * + * @ring: the engine to test on + * + */ +static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t rptr = amdgpu_ring_get_rptr(ring); + unsigned i; + int r; + + r = amdgpu_ring_alloc(ring, 16); + if (r) { + DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, HEVC_ENC_CMD_END); + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + if (amdgpu_ring_get_rptr(ring) != rptr) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed\n", + ring->idx); + r = -ETIMEDOUT; + } + + return r; +} + +/** + * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg + * + * @adev: amdgpu_device pointer + * @ring: ring we should submit the msg to + * @handle: session handle to use + * @fence: optional fence to return + * + * Open up a stream for HW test + */ +static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct dma_fence **fence) +{ + const unsigned ib_size_dw = 16; + struct amdgpu_job *job; + struct amdgpu_ib *ib; + struct dma_fence *f = NULL; + uint64_t dummy; + int i, r; + + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); + if (r) + return r; + + ib = &job->ibs[0]; + dummy = ib->gpu_addr + 1024; + + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = upper_32_bits(dummy); + ib->ptr[ib->length_dw++] = dummy; + + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ + + for (i = ib->length_dw; i < ib_size_dw; ++i) + ib->ptr[i] = 0x0; + + r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + job->fence = dma_fence_get(f); + if (r) + goto err; + + amdgpu_job_free(job); + if (fence) + *fence = dma_fence_get(f); + dma_fence_put(f); + return 0; + +err: + amdgpu_job_free(job); + return r; +} + +/** + * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg + * + * @adev: amdgpu_device pointer + * @ring: ring we should submit the msg to + * @handle: session handle to use + * @fence: optional fence to return + * + * Close up a stream for HW test or if userspace failed to do so + */ +int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + bool direct, struct dma_fence **fence) +{ + const unsigned ib_size_dw = 16; + struct amdgpu_job *job; + struct amdgpu_ib *ib; + struct dma_fence *f = NULL; + uint64_t dummy; + int i, r; + + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); + if (r) + return r; + + ib = &job->ibs[0]; + dummy = ib->gpu_addr + 1024; + + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = upper_32_bits(dummy); + ib->ptr[ib->length_dw++] = dummy; + + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ + + for (i = ib->length_dw; i < ib_size_dw; ++i) + ib->ptr[i] = 0x0; + + if (direct) { + r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); + job->fence = dma_fence_get(f); + if (r) + goto err; + + amdgpu_job_free(job); + } else { + r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity, + AMDGPU_FENCE_OWNER_UNDEFINED, &f); + if (r) + goto err; + } + + if (fence) + *fence = dma_fence_get(f); + dma_fence_put(f); + return 0; + +err: + amdgpu_job_free(job); + return r; +} + +/** + * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working + * + * @ring: the engine to test on + * + */ +static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct dma_fence *fence = NULL; + long r; + + r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); + goto error; + } + + r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); + goto error; + } + + r = dma_fence_wait_timeout(fence, false, timeout); + if (r == 0) { + DRM_ERROR("amdgpu: IB test timed out.\n"); + r = -ETIMEDOUT; + } else if (r < 0) { + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + } else { + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + r = 0; + } +error: + dma_fence_put(fence); + return r; +} + +static int uvd_v7_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->uvd.num_enc_rings = 2; + uvd_v7_0_set_ring_funcs(adev); + uvd_v7_0_set_enc_ring_funcs(adev); + uvd_v7_0_set_irq_funcs(adev); + + return 0; +} + +static int uvd_v7_0_sw_init(void *handle) +{ + struct amdgpu_ring *ring; + struct amd_sched_rq *rq; + int i, r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* UVD TRAP */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq); + if (r) + return r; + + /* UVD ENC TRAP */ + for (i = 0; i < adev->uvd.num_enc_rings; ++i) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq); + if (r) + return r; + } + + r = amdgpu_uvd_sw_init(adev); + if (r) + return r; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + const struct common_firmware_header *hdr; + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); + DRM_INFO("PSP loading UVD firmware\n"); + } + + ring = &adev->uvd.ring_enc[0]; + rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; + r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, + rq, amdgpu_sched_jobs); + if (r) { + DRM_ERROR("Failed setting up UVD ENC run queue.\n"); + return r; + } + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); + if (r) + return r; + + for (i = 0; i < adev->uvd.num_enc_rings; ++i) { + ring = &adev->uvd.ring_enc[i]; + sprintf(ring->name, "uvd_enc%d", i); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); + if (r) + return r; + } + + return r; +} + +static int uvd_v7_0_sw_fini(void *handle) +{ + int i, r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc); + + for (i = 0; i < adev->uvd.num_enc_rings; ++i) + amdgpu_ring_fini(&adev->uvd.ring_enc[i]); + + r = amdgpu_uvd_sw_fini(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v7_0_hw_init - start and test UVD block + * + * @adev: amdgpu_device pointer + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int uvd_v7_0_hw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t tmp; + int i, r; + + r = uvd_v7_0_start(adev); + if (r) + goto done; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + + r = amdgpu_ring_alloc(ring, 10); + if (r) { + DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + goto done; + } + + tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0, + mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0, + mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0, + mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + /* Clear timeout status bits */ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, + mmUVD_SEMA_TIMEOUT_STATUS), 0)); + amdgpu_ring_write(ring, 0x8); + + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, + mmUVD_SEMA_CNTL), 0)); + amdgpu_ring_write(ring, 3); + + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->uvd.num_enc_rings; ++i) { + ring = &adev->uvd.ring_enc[i]; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + } + +done: + if (!r) + DRM_INFO("UVD and UVD ENC initialized successfully.\n"); + + return r; +} + +/** + * uvd_v7_0_hw_fini - stop the hardware block + * + * @adev: amdgpu_device pointer + * + * Stop the UVD block, mark ring as not ready any more + */ +static int uvd_v7_0_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ring *ring = &adev->uvd.ring; + + uvd_v7_0_stop(adev); + ring->ready = false; + + return 0; +} + +static int uvd_v7_0_suspend(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = uvd_v7_0_hw_fini(adev); + if (r) + return r; + + /* Skip this for APU for now */ + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + } + + return r; +} + +static int uvd_v7_0_resume(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* Skip this for APU for now */ + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_uvd_resume(adev); + if (r) + return r; + } + r = uvd_v7_0_hw_init(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v7_0_mc_resume - memory controller programming + * + * @adev: amdgpu_device pointer + * + * Let the UVD memory controller know it's offsets + */ +static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) +{ + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + uint32_t offset; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); + offset = 0; + } else { + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + lower_32_bits(adev->uvd.gpu_addr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + upper_32_bits(adev->uvd.gpu_addr)); + offset = size; + } + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), + AMDGPU_UVD_FIRMWARE_OFFSET >> 3); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size); + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), + lower_32_bits(adev->uvd.gpu_addr + offset)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), + upper_32_bits(adev->uvd.gpu_addr + offset)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), + lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), + upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), + AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG), + adev->gfx.config.gb_addr_config); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG), + adev->gfx.config.gb_addr_config); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG), + adev->gfx.config.gb_addr_config); + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); +} + +/** + * uvd_v7_0_start - start UVD block + * + * @adev: amdgpu_device pointer + * + * Setup and start the UVD block + */ +static int uvd_v7_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t rb_bufsz, tmp; + uint32_t lmi_swap_cntl; + uint32_t mp_swap_cntl; + int i, j, r; + + /* disable DPG */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, + ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); + + /* disable byte swapping */ + lmi_swap_cntl = 0; + mp_swap_cntl = 0; + + uvd_v7_0_mc_resume(adev); + + /* disable clock gating */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0, + ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); + + /* disable interupt */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, + ~UVD_MASTINT_EN__VCPU_EN_MASK); + + /* stall UMC and register bus before resetting VCPU */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), + UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + mdelay(1); + + /* put LMI, VCPU, RBC etc... into reset */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | + UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | + UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | + UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); + mdelay(5); + + /* initialize UVD memory controller */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL), + (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | + 0x00100000L); + +#ifdef __BIG_ENDIAN + /* swap (8 in 32) RB and IB */ + lmi_swap_cntl = 0xa; + mp_swap_cntl = 0; +#endif + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), lmi_swap_cntl); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), mp_swap_cntl); + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88); + + /* take all subblocks out of reset, except VCPU */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* enable VCPU clock */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), + UVD_VCPU_CNTL__CLK_EN_MASK); + + /* enable UMC */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + + /* boot up the VCPU */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0); + mdelay(10); + + for (i = 0; i < 10; ++i) { + uint32_t status; + + for (j = 0; j < 100; ++j) { + status = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS)); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + if (r) { + DRM_ERROR("UVD not responding, giving up!!!\n"); + return r; + } + /* enable master interrupt */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), + (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), + ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); + + /* clear the bit 4 of UVD_STATUS */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); + + /* force RBC into idle state */ + rb_bufsz = order_base_2(ring->ring_size); + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp); + + /* set the write pointer delay */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0); + + /* set the wb address */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR), + (upper_32_bits(ring->gpu_addr) >> 2)); + + /* programm the RB_BASE for ring buffer */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), + lower_32_bits(ring->gpu_addr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), + upper_32_bits(ring->gpu_addr)); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR), 0); + + ring->wptr = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), + lower_32_bits(ring->wptr)); + + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, + ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); + + ring = &adev->uvd.ring_enc[0]; + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4); + + ring = &adev->uvd.ring_enc[1]; + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4); + + return 0; +} + +/** + * uvd_v7_0_stop - stop UVD block + * + * @adev: amdgpu_device pointer + * + * stop the UVD block + */ +static void uvd_v7_0_stop(struct amdgpu_device *adev) +{ + /* force RBC into idle state */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0x11010101); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), + UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + mdelay(1); + + /* put VCPU into reset */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* disable VCPU clock */ + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0x0); + + /* Unstall UMC and register bus */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); +} + +/** + * uvd_v7_0_ring_emit_fence - emit an fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write a fence and a trap command to the ring. + */ +static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + unsigned flags) +{ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, addr & 0xffffffff); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, 2); +} + +/** + * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write enc a fence and a trap command to the ring. + */ +static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) +{ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); + amdgpu_ring_write(ring, addr); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); +} + +/** + * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush + * + * @ring: amdgpu_ring pointer + * + * Emits an hdp flush. + */ +static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0, + mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0)); + amdgpu_ring_write(ring, 0); +} + +/** + * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate + * + * @ring: amdgpu_ring pointer + * + * Emits an hdp invalidate. + */ +static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0)); + amdgpu_ring_write(ring, 1); +} + +/** + * uvd_v7_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully write to the context register + */ +static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t tmp = 0; + unsigned i; + int r; + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD); + r = amdgpu_ring_alloc(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_commit(ring); + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID)); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + return r; +} + +/** + * uvd_v7_0_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write ring commands to execute the indirect buffer + */ +static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); + amdgpu_ring_write(ring, vm_id); + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); + amdgpu_ring_write(ring, ib->length_dw); +} + +/** + * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write enc ring commands to execute the indirect buffer + */ +static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) +{ + amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); + amdgpu_ring_write(ring, vm_id); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); +} + +static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, data1); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, 8); +} + +static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1, uint32_t mask) +{ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); + amdgpu_ring_write(ring, data1); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); + amdgpu_ring_write(ring, mask); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, 12); +} + +static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + uint32_t data0, data1, mask; + unsigned eng = ring->idx; + unsigned i; + + pd_addr = pd_addr | 0x1; /* valid bit */ + /* now only use physical base address of PDE and valid */ + BUG_ON(pd_addr & 0xFFFF00000000003EULL); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; + uint32_t req = hub->get_invalidate_req(vm_id); + + data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2; + data1 = upper_32_bits(pd_addr); + uvd_v7_0_vm_reg_write(ring, data0, data1); + + data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; + data1 = lower_32_bits(pd_addr); + uvd_v7_0_vm_reg_write(ring, data0, data1); + + data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2; + data1 = lower_32_bits(pd_addr); + mask = 0xffffffff; + uvd_v7_0_vm_reg_wait(ring, data0, data1, mask); + + /* flush TLB */ + data0 = (hub->vm_inv_eng0_req + eng) << 2; + data1 = req; + uvd_v7_0_vm_reg_write(ring, data0, data1); + + /* wait for flush */ + data0 = (hub->vm_inv_eng0_ack + eng) << 2; + data1 = 1 << vm_id; + mask = 1 << vm_id; + uvd_v7_0_vm_reg_wait(ring, data0, data1, mask); + } +} + +static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, HEVC_ENC_CMD_END); +} + +static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned int vm_id, uint64_t pd_addr) +{ + unsigned eng = ring->idx; + unsigned i; + + pd_addr = pd_addr | 0x1; /* valid bit */ + /* now only use physical base address of PDE and valid */ + BUG_ON(pd_addr & 0xFFFF00000000003EULL); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; + uint32_t req = hub->get_invalidate_req(vm_id); + + amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, upper_32_bits(pd_addr)); + + amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, 0xffffffff); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + /* flush TLB */ + amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); + amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2); + amdgpu_ring_write(ring, req); + + /* wait for flush */ + amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); + amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); + amdgpu_ring_write(ring, 1 << vm_id); + amdgpu_ring_write(ring, 1 << vm_id); + } +} + +#if 0 +static bool uvd_v7_0_is_idle(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); +} + +static int uvd_v7_0_wait_for_idle(void *handle) +{ + unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + for (i = 0; i < adev->usec_timeout; i++) { + if (uvd_v7_0_is_idle(handle)) + return 0; + } + return -ETIMEDOUT; +} + +#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd +static bool uvd_v7_0_check_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || + REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || + (RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS) & + AMDGPU_UVD_STATUS_BUSY_MASK))) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); + + if (srbm_soft_reset) { + adev->uvd.srbm_soft_reset = srbm_soft_reset; + return true; + } else { + adev->uvd.srbm_soft_reset = 0; + return false; + } +} + +static int uvd_v7_0_pre_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!adev->uvd.srbm_soft_reset) + return 0; + + uvd_v7_0_stop(adev); + return 0; +} + +static int uvd_v7_0_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 srbm_soft_reset; + + if (!adev->uvd.srbm_soft_reset) + return 0; + srbm_soft_reset = adev->uvd.srbm_soft_reset; + + if (srbm_soft_reset) { + u32 tmp; + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + } + + return 0; +} + +static int uvd_v7_0_post_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!adev->uvd.srbm_soft_reset) + return 0; + + mdelay(5); + + return uvd_v7_0_start(adev); +} +#endif + +static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + // TODO + return 0; +} + +static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: UVD TRAP\n"); + switch (entry->src_id) { + case 124: + amdgpu_fence_process(&adev->uvd.ring); + break; + case 119: + amdgpu_fence_process(&adev->uvd.ring_enc[0]); + break; + case 120: + amdgpu_fence_process(&adev->uvd.ring_enc[1]); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +#if 0 +static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data1, data2, suvd_flags; + + data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL)); + data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE)); + data2 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL)); + + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | + UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + + suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK; + + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | + (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | + (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); + + data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | + UVD_CGC_CTRL__UDEC_CM_MODE_MASK | + UVD_CGC_CTRL__UDEC_IT_MODE_MASK | + UVD_CGC_CTRL__UDEC_DB_MODE_MASK | + UVD_CGC_CTRL__UDEC_MP_MODE_MASK | + UVD_CGC_CTRL__SYS_MODE_MASK | + UVD_CGC_CTRL__UDEC_MODE_MASK | + UVD_CGC_CTRL__MPEG2_MODE_MASK | + UVD_CGC_CTRL__REGS_MODE_MASK | + UVD_CGC_CTRL__RBC_MODE_MASK | + UVD_CGC_CTRL__LMI_MC_MODE_MASK | + UVD_CGC_CTRL__LMI_UMC_MODE_MASK | + UVD_CGC_CTRL__IDCT_MODE_MASK | + UVD_CGC_CTRL__MPRD_MODE_MASK | + UVD_CGC_CTRL__MPC_MODE_MASK | + UVD_CGC_CTRL__LBSI_MODE_MASK | + UVD_CGC_CTRL__LRBBM_MODE_MASK | + UVD_CGC_CTRL__WCB_MODE_MASK | + UVD_CGC_CTRL__VCPU_MODE_MASK | + UVD_CGC_CTRL__JPEG_MODE_MASK | + UVD_CGC_CTRL__JPEG2_MODE_MASK | + UVD_CGC_CTRL__SCPU_MODE_MASK); + data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | + UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | + UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | + UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | + UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); + data1 |= suvd_flags; + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), data); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), 0); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_CTRL), data2); +} + +static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data1, cgc_flags, suvd_flags; + + data = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE)); + data1 = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE)); + + cgc_flags = UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__VCPU_MASK | + UVD_CGC_GATE__SCPU_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__JPEG2_MASK; + + suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK; + + data |= cgc_flags; + data1 |= suvd_flags; + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_GATE), data); + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SUVD_CGC_GATE), data1); +} + +static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) +{ + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); + + if (enable) + tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | + GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + else + tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | + GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); +} + + +static int uvd_v7_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + + uvd_v7_0_set_bypass_mode(adev, enable); + + if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) + return 0; + + if (enable) { + /* disable HW gating and enable Sw gating */ + uvd_v7_0_set_sw_clock_gating(adev); + } else { + /* wait for STATUS to clear */ + if (uvd_v7_0_wait_for_idle(handle)) + return -EBUSY; + + /* enable HW gates because UVD is idle */ + /* uvd_v7_0_set_hw_clock_gating(adev); */ + } + + return 0; +} + +static int uvd_v7_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + /* This doesn't actually powergate the UVD block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) + return 0; + + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), UVD_POWER_STATUS__UVD_PG_EN_MASK); + + if (state == AMD_PG_STATE_GATE) { + uvd_v7_0_stop(adev); + return 0; + } else { + return uvd_v7_0_start(adev); + } +} +#endif + +static int uvd_v7_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + /* needed for driver unload*/ + return 0; +} + +const struct amd_ip_funcs uvd_v7_0_ip_funcs = { + .name = "uvd_v7_0", + .early_init = uvd_v7_0_early_init, + .late_init = NULL, + .sw_init = uvd_v7_0_sw_init, + .sw_fini = uvd_v7_0_sw_fini, + .hw_init = uvd_v7_0_hw_init, + .hw_fini = uvd_v7_0_hw_fini, + .suspend = uvd_v7_0_suspend, + .resume = uvd_v7_0_resume, + .is_idle = NULL /* uvd_v7_0_is_idle */, + .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, + .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, + .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, + .soft_reset = NULL /* uvd_v7_0_soft_reset */, + .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, + .set_clockgating_state = uvd_v7_0_set_clockgating_state, + .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, +}; + +static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0), + .support_64bit_ptrs = false, + .get_rptr = uvd_v7_0_ring_get_rptr, + .get_wptr = uvd_v7_0_ring_get_wptr, + .set_wptr = uvd_v7_0_ring_set_wptr, + .emit_frame_size = + 2 + /* uvd_v7_0_ring_emit_hdp_flush */ + 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */ + 34 * AMDGPU_MAX_VMHUBS + /* uvd_v7_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ + .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ + .emit_ib = uvd_v7_0_ring_emit_ib, + .emit_fence = uvd_v7_0_ring_emit_fence, + .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, + .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, + .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v7_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_uvd_ring_begin_use, + .end_use = amdgpu_uvd_ring_end_use, +}; + +static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_UVD_ENC, + .align_mask = 0x3f, + .nop = HEVC_ENC_CMD_NO_OP, + .support_64bit_ptrs = false, + .get_rptr = uvd_v7_0_enc_ring_get_rptr, + .get_wptr = uvd_v7_0_enc_ring_get_wptr, + .set_wptr = uvd_v7_0_enc_ring_set_wptr, + .emit_frame_size = + 17 * AMDGPU_MAX_VMHUBS + /* uvd_v7_0_enc_ring_emit_vm_flush */ + 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ + 1, /* uvd_v7_0_enc_ring_insert_end */ + .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ + .emit_ib = uvd_v7_0_enc_ring_emit_ib, + .emit_fence = uvd_v7_0_enc_ring_emit_fence, + .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, + .test_ring = uvd_v7_0_enc_ring_test_ring, + .test_ib = uvd_v7_0_enc_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_end = uvd_v7_0_enc_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_uvd_ring_begin_use, + .end_use = amdgpu_uvd_ring_end_use, +}; + +static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs; + DRM_INFO("UVD is enabled in VM mode\n"); +} + +static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->uvd.num_enc_rings; ++i) + adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; + + DRM_INFO("UVD ENC is enabled in VM mode\n"); +} + +static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { + .set = uvd_v7_0_set_interrupt_state, + .process = uvd_v7_0_process_interrupt, +}; + +static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1; + adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs; +} + +const struct amdgpu_ip_block_version uvd_v7_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &uvd_v7_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h new file mode 100644 index 000000000000..cbe82ab3224f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __UVD_V7_0_H__ +#define __UVD_V7_0_H__ + +extern const struct amdgpu_ip_block_version uvd_v7_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 9ea99348e493..49a6c45e65be 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -52,7 +52,7 @@ static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); * * Returns the current hardware read pointer */ -static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -69,7 +69,7 @@ static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring) * * Returns the current hardware write pointer */ -static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -91,9 +91,9 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->vce.ring[0]) - WREG32(mmVCE_RB_WPTR, ring->wptr); + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); else - WREG32(mmVCE_RB_WPTR2, ring->wptr); + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); } static int vce_v2_0_lmi_clean(struct amdgpu_device *adev) @@ -167,8 +167,7 @@ static void vce_v2_0_init_cg(struct amdgpu_device *adev) static void vce_v2_0_mc_resume(struct amdgpu_device *adev) { - uint64_t addr = adev->vce.gpu_addr; - uint32_t size; + uint32_t size, offset; WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); @@ -181,19 +180,21 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_SWAP_CNTL1, 0); WREG32(mmVCE_LMI_VM_CTRL, 0); - addr += AMDGPU_VCE_FIRMWARE_OFFSET; + WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); + + offset = AMDGPU_VCE_FIRMWARE_OFFSET; size = VCE_V2_0_FW_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); - addr += size; + offset += size; size = VCE_V2_0_STACK_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size); - addr += size; + offset += size; size = VCE_V2_0_DATA_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size); WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); @@ -240,15 +241,15 @@ static int vce_v2_0_start(struct amdgpu_device *adev) vce_v2_0_mc_resume(adev); ring = &adev->vce.ring[0]; - WREG32(mmVCE_RB_RPTR, ring->wptr); - WREG32(mmVCE_RB_WPTR, ring->wptr); + WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); ring = &adev->vce.ring[1]; - WREG32(mmVCE_RB_RPTR2, ring->wptr); - WREG32(mmVCE_RB_WPTR2, ring->wptr); + WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); @@ -273,24 +274,14 @@ static int vce_v2_0_start(struct amdgpu_device *adev) static int vce_v2_0_stop(struct amdgpu_device *adev) { - int i, j; + int i; int status; if (vce_v2_0_lmi_clean(adev)) { DRM_INFO("vce is not idle \n"); return 0; } -/* - for (i = 0; i < 10; ++i) { - for (j = 0; j < 100; ++j) { - status = RREG32(mmVCE_FW_REG_STATUS); - if (!(status & 1)) - break; - mdelay(1); - } - break; - } -*/ + if (vce_v2_0_wait_for_idle(adev)) { DRM_INFO("VCE is busy, Can't set clock gateing"); return 0; @@ -299,14 +290,11 @@ static int vce_v2_0_stop(struct amdgpu_device *adev) /* Stall UMC and register bus before resetting VCPU */ WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8)); - for (i = 0; i < 10; ++i) { - for (j = 0; j < 100; ++j) { - status = RREG32(mmVCE_LMI_STATUS); - if (status & 0x240) - break; - mdelay(1); - } - break; + for (i = 0; i < 100; ++i) { + status = RREG32(mmVCE_LMI_STATUS); + if (status & 0x240) + break; + mdelay(1); } WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001); @@ -429,7 +417,7 @@ static int vce_v2_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* VCE */ - r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq); if (r) return r; @@ -559,14 +547,14 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { DRM_DEBUG("IH: VCE\n"); - switch (entry->src_data) { + switch (entry->src_data[0]) { case 0: case 1: - amdgpu_fence_process(&adev->vce.ring[entry->src_data]); + amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); break; default: DRM_ERROR("Unhandled interrupt: %d %d\n", - entry->src_id, entry->src_data); + entry->src_id, entry->src_data[0]); break; } @@ -630,6 +618,7 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .type = AMDGPU_RING_TYPE_VCE, .align_mask = 0xf, .nop = VCE_CMD_NO_OP, + .support_64bit_ptrs = false, .get_rptr = vce_v2_0_ring_get_rptr, .get_wptr = vce_v2_0_ring_get_wptr, .set_wptr = vce_v2_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 93ec8815bb13..db0adac073c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -65,7 +65,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); static int vce_v3_0_wait_for_idle(void *handle); - +static int vce_v3_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state); /** * vce_v3_0_ring_get_rptr - get read pointer * @@ -73,7 +74,7 @@ static int vce_v3_0_wait_for_idle(void *handle); * * Returns the current hardware read pointer */ -static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) +static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -92,7 +93,7 @@ static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) * * Returns the current hardware write pointer */ -static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) +static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -116,11 +117,11 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->vce.ring[0]) - WREG32(mmVCE_RB_WPTR, ring->wptr); + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); else if (ring == &adev->vce.ring[1]) - WREG32(mmVCE_RB_WPTR2, ring->wptr); + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); else - WREG32(mmVCE_RB_WPTR3, ring->wptr); + WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); } static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override) @@ -231,22 +232,22 @@ static int vce_v3_0_start(struct amdgpu_device *adev) int idx, r; ring = &adev->vce.ring[0]; - WREG32(mmVCE_RB_RPTR, ring->wptr); - WREG32(mmVCE_RB_WPTR, ring->wptr); + WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); ring = &adev->vce.ring[1]; - WREG32(mmVCE_RB_RPTR2, ring->wptr); - WREG32(mmVCE_RB_WPTR2, ring->wptr); + WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); ring = &adev->vce.ring[2]; - WREG32(mmVCE_RB_RPTR3, ring->wptr); - WREG32(mmVCE_RB_WPTR3, ring->wptr); + WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4); @@ -305,12 +306,8 @@ static int vce_v3_0_stop(struct amdgpu_device *adev) /* hold on ECPU */ WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); - /* clear BUSY flag */ - WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); - - /* Set Clock-Gating off */ - if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG) - vce_v3_0_set_vce_sw_clock_gating(adev, false); + /* clear VCE STATUS */ + WREG32(mmVCE_STATUS, 0); } WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); @@ -383,7 +380,7 @@ static int vce_v3_0_sw_init(void *handle) int r, i; /* VCE */ - r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq); if (r) return r; @@ -461,7 +458,8 @@ static int vce_v3_0_hw_fini(void *handle) if (r) return r; - return vce_v3_0_stop(adev); + vce_v3_0_stop(adev); + return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); } static int vce_v3_0_suspend(void *handle) @@ -695,15 +693,15 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1); - switch (entry->src_data) { + switch (entry->src_data[0]) { case 0: case 1: case 2: - amdgpu_fence_process(&adev->vce.ring[entry->src_data]); + amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); break; default: DRM_ERROR("Unhandled interrupt: %d %d\n", - entry->src_id, entry->src_data); + entry->src_id, entry->src_data[0]); break; } @@ -728,7 +726,7 @@ static int vce_v3_0_set_clockgating_state(void *handle, WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i)); - if (enable) { + if (!enable) { /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */ uint32_t data = RREG32(mmVCE_CLOCK_GATING_A); data &= ~(0xf | 0xff0); @@ -785,8 +783,12 @@ static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags) mutex_lock(&adev->pm.mutex); - if (RREG32_SMC(ixCURRENT_PG_STATUS) & - CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) { + if (adev->flags & AMD_IS_APU) + data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); + else + data = RREG32_SMC(ixCURRENT_PG_STATUS); + + if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) { DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); goto out; } @@ -860,6 +862,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { .type = AMDGPU_RING_TYPE_VCE, .align_mask = 0xf, .nop = VCE_CMD_NO_OP, + .support_64bit_ptrs = false, .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, @@ -882,6 +885,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCE, .align_mask = 0xf, .nop = VCE_CMD_NO_OP, + .support_64bit_ptrs = false, .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c new file mode 100644 index 000000000000..becc5f744a98 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -0,0 +1,1141 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ + +#include <linux/firmware.h> +#include <drm/drmP.h> +#include "amdgpu.h" +#include "amdgpu_vce.h" +#include "soc15d.h" +#include "soc15_common.h" +#include "mmsch_v1_0.h" + +#include "vega10/soc15ip.h" +#include "vega10/VCE/vce_4_0_offset.h" +#include "vega10/VCE/vce_4_0_default.h" +#include "vega10/VCE/vce_4_0_sh_mask.h" +#include "vega10/MMHUB/mmhub_1_0_offset.h" +#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" + +#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 + +#define VCE_V4_0_FW_SIZE (384 * 1024) +#define VCE_V4_0_STACK_SIZE (64 * 1024) +#define VCE_V4_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) + +static void vce_v4_0_mc_resume(struct amdgpu_device *adev); +static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev); +static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev); + +static inline void mmsch_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt, + uint32_t *init_table, + uint32_t reg_offset, + uint32_t value) +{ + direct_wt->cmd_header.reg_offset = reg_offset; + direct_wt->reg_value = value; + memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write)); +} + +static inline void mmsch_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, + uint32_t *init_table, + uint32_t reg_offset, + uint32_t mask, uint32_t data) +{ + direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; + direct_rd_mod_wt->mask_value = mask; + direct_rd_mod_wt->write_data = data; + memcpy((void *)init_table, direct_rd_mod_wt, + sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)); +} + +static inline void mmsch_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll, + uint32_t *init_table, + uint32_t reg_offset, + uint32_t mask, uint32_t wait) +{ + direct_poll->cmd_header.reg_offset = reg_offset; + direct_poll->mask_value = mask; + direct_poll->wait_value = wait; + memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling)); +} + +#define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ + mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \ + init_table, (reg), \ + (mask), (data)); \ + init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \ + table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \ +} + +#define INSERT_DIRECT_WT(reg, value) { \ + mmsch_insert_direct_wt(&direct_wt, \ + init_table, (reg), \ + (value)); \ + init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \ + table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \ +} + +#define INSERT_DIRECT_POLL(reg, mask, wait) { \ + mmsch_insert_direct_poll(&direct_poll, \ + init_table, (reg), \ + (mask), (wait)); \ + init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \ + table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \ +} + +/** + * vce_v4_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); + else if (ring == &adev->vce.ring[1]) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); + else + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); +} + +/** + * vce_v4_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) + return adev->wb.wb[ring->wptr_offs]; + + if (ring == &adev->vce.ring[0]) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); + else if (ring == &adev->vce.ring[1]) + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); + else + return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); +} + +/** + * vce_v4_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); + return; + } + + if (ring == &adev->vce.ring[0]) + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), + lower_32_bits(ring->wptr)); + else if (ring == &adev->vce.ring[1]) + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), + lower_32_bits(ring->wptr)); + else + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), + lower_32_bits(ring->wptr)); +} + +static int vce_v4_0_firmware_loaded(struct amdgpu_device *adev) +{ + int i, j; + + for (i = 0; i < 10; ++i) { + for (j = 0; j < 100; ++j) { + uint32_t status = + RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); + + if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK) + return 0; + mdelay(10); + } + + DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + + } + + return -ETIMEDOUT; +} + +static int vce_v4_0_mmsch_start(struct amdgpu_device *adev, + struct amdgpu_mm_table *table) +{ + uint32_t data = 0, loop; + uint64_t addr = table->gpu_addr; + struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; + uint32_t size; + + size = header->header_size + header->vce_table_size + header->uvd_table_size; + + /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr)); + + /* 2, update vmid of descriptor */ + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID)); + data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; + data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data); + + /* 3, notify mmsch about the size of this descriptor */ + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size); + + /* 4, set resp to zero */ + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0); + + /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); + loop = 1000; + while ((data & 0x10000002) != 0x10000002) { + udelay(10); + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP)); + loop--; + if (!loop) + break; + } + + if (!loop) { + dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); + return -EBUSY; + } + + return 0; +} + +static int vce_v4_0_sriov_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + uint32_t offset, size; + uint32_t table_size = 0; + struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; + struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; + struct mmsch_v1_0_cmd_direct_polling direct_poll = { { 0 } }; + struct mmsch_v1_0_cmd_end end = { { 0 } }; + uint32_t *init_table = adev->virt.mm_table.cpu_addr; + struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; + + direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; + direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; + direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; + end.cmd_header.command_type = MMSCH_COMMAND__END; + + if (header->vce_table_offset == 0 && header->vce_table_size == 0) { + header->version = MMSCH_VERSION; + header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; + + if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) + header->vce_table_offset = header->header_size; + else + header->vce_table_offset = header->uvd_table_size + header->uvd_table_offset; + + init_table += header->vce_table_offset; + + ring = &adev->vce.ring[0]; + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), ring->wptr); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), ring->wptr); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), lower_32_bits(ring->gpu_addr)); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4); + + /* BEGING OF MC_RESUME */ + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), ~(1 << 16), 0); + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), ~0xFF9FF000, 0x1FF000); + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), ~0x3F, 0x3F); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF); + + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000); + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); + + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->vce.gpu_addr >> 8); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), adev->vce.gpu_addr >> 8); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), adev->vce.gpu_addr >> 8); + + offset = AMDGPU_VCE_FIRMWARE_OFFSET; + size = VCE_V4_0_FW_SIZE; + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & 0x7FFFFFFF); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); + + offset += size; + size = VCE_V4_0_STACK_SIZE; + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), offset & 0x7FFFFFFF); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); + + offset += size; + size = VCE_V4_0_DATA_SIZE; + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), offset & 0x7FFFFFFF); + INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); + + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), + 0xffffffff, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + + /* end of MC_RESUME */ + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), + ~0x200001, VCE_VCPU_CNTL__CLK_EN_MASK); + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 0); + + INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), + VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK, + VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK); + + /* clear BUSY flag */ + INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), + ~VCE_STATUS__JOB_BUSY_MASK, 0); + + /* add end packet */ + memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); + table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; + header->vce_table_size = table_size; + + return vce_v4_0_mmsch_start(adev, &adev->virt.mm_table); + } + + return -EINVAL; /* already initializaed ? */ +} + +/** + * vce_v4_0_start - start VCE block + * + * @adev: amdgpu_device pointer + * + * Setup and start the VCE block + */ +static int vce_v4_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + ring = &adev->vce.ring[0]; + + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4); + + ring = &adev->vce.ring[1]; + + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4); + + ring = &adev->vce.ring[2]; + + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4); + + vce_v4_0_mc_resume(adev); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK, + ~VCE_STATUS__JOB_BUSY_MASK); + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(100); + + r = vce_v4_0_firmware_loaded(adev); + + /* clear BUSY flag */ + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); + + if (r) { + DRM_ERROR("VCE not responding, giving up!!!\n"); + return r; + } + + return 0; +} + +static int vce_v4_0_stop(struct amdgpu_device *adev) +{ + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); + + /* hold on ECPU */ + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + /* clear BUSY flag */ + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); + + /* Set Clock-Gating off */ + /* if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG) + vce_v4_0_set_vce_sw_clock_gating(adev, false); + */ + + return 0; +} + +static int vce_v4_0_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_sriov_vf(adev)) /* currently only VCN0 support SRIOV */ + adev->vce.num_rings = 1; + else + adev->vce.num_rings = 3; + + vce_v4_0_set_ring_funcs(adev); + vce_v4_0_set_irq_funcs(adev); + + return 0; +} + +static int vce_v4_0_sw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ring *ring; + unsigned size; + int r, i; + + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCE0, 167, &adev->vce.irq); + if (r) + return r; + + size = (VCE_V4_0_STACK_SIZE + VCE_V4_0_DATA_SIZE) * 2; + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) + size += VCE_V4_0_FW_SIZE; + + r = amdgpu_vce_sw_init(adev, size); + if (r) + return r; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + const struct common_firmware_header *hdr; + hdr = (const struct common_firmware_header *)adev->vce.fw->data; + adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].ucode_id = AMDGPU_UCODE_ID_VCE; + adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); + DRM_INFO("PSP loading VCE firmware\n"); + } + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + r = amdgpu_vce_resume(adev); + if (r) + return r; + } + + for (i = 0; i < adev->vce.num_rings; i++) { + ring = &adev->vce.ring[i]; + sprintf(ring->name, "vce%d", i); + if (amdgpu_sriov_vf(adev)) { + /* DOORBELL only works under SRIOV */ + ring->use_doorbell = true; + if (i == 0) + ring->doorbell_index = AMDGPU_DOORBELL64_RING0_1 * 2; + else if (i == 1) + ring->doorbell_index = AMDGPU_DOORBELL64_RING2_3 * 2; + else + ring->doorbell_index = AMDGPU_DOORBELL64_RING2_3 * 2 + 1; + } + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); + if (r) + return r; + } + + if (amdgpu_sriov_vf(adev)) { + r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->virt.mm_table.bo, + &adev->virt.mm_table.gpu_addr, + (void *)&adev->virt.mm_table.cpu_addr); + if (!r) { + memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); + printk("mm table gpu addr = 0x%llx, cpu addr = %p. \n", + adev->virt.mm_table.gpu_addr, + adev->virt.mm_table.cpu_addr); + } + return r; + } + + return r; +} + +static int vce_v4_0_sw_fini(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + /* free MM table */ + if (amdgpu_sriov_vf(adev)) + amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, + &adev->virt.mm_table.gpu_addr, + (void *)&adev->virt.mm_table.cpu_addr); + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + r = amdgpu_vce_sw_fini(adev); + if (r) + return r; + + return r; +} + +static int vce_v4_0_hw_init(void *handle) +{ + int r, i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_sriov_vf(adev)) + r = vce_v4_0_sriov_start(adev); + else + r = vce_v4_0_start(adev); + if (r) + return r; + + for (i = 0; i < adev->vce.num_rings; i++) + adev->vce.ring[i].ready = false; + + for (i = 0; i < adev->vce.num_rings; i++) { + r = amdgpu_ring_test_ring(&adev->vce.ring[i]); + if (r) + return r; + else + adev->vce.ring[i].ready = true; + } + + DRM_INFO("VCE initialized successfully.\n"); + + return 0; +} + +static int vce_v4_0_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; + + /* vce_v4_0_wait_for_idle(handle); */ + vce_v4_0_stop(adev); + for (i = 0; i < adev->vce.num_rings; i++) + adev->vce.ring[i].ready = false; + + return 0; +} + +static int vce_v4_0_suspend(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = vce_v4_0_hw_fini(adev); + if (r) + return r; + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + return r; +} + +static int vce_v4_0_resume(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + + r = vce_v4_0_hw_init(adev); + if (r) + return r; + + return r; +} + +static void vce_v4_0_mc_resume(struct amdgpu_device *adev) +{ + uint32_t offset, size; + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF); + + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff); + } else { + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), + (adev->vce.gpu_addr >> 8)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), + (adev->vce.gpu_addr >> 40) & 0xff); + } + + offset = AMDGPU_VCE_FIRMWARE_OFFSET; + size = VCE_V4_0_FW_SIZE; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); + + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff); + offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0; + size = VCE_V4_0_STACK_SIZE; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); + + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff); + offset += size; + size = VCE_V4_0_DATA_SIZE; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), + VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK, + ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); +} + +static int vce_v4_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + /* needed for driver unload*/ + return 0; +} + +#if 0 +static bool vce_v4_0_is_idle(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 mask = 0; + + mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK; + mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK; + + return !(RREG32(mmSRBM_STATUS2) & mask); +} + +static int vce_v4_0_wait_for_idle(void *handle) +{ + unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + for (i = 0; i < adev->usec_timeout; i++) + if (vce_v4_0_is_idle(handle)) + return 0; + + return -ETIMEDOUT; +} + +#define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK 0x00000008L /* AUTO_BUSY */ +#define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK 0x00000010L /* RB0_BUSY */ +#define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK 0x00000020L /* RB1_BUSY */ +#define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \ + VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK) + +static bool vce_v4_0_check_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 srbm_soft_reset = 0; + + /* According to VCE team , we should use VCE_STATUS instead + * SRBM_STATUS.VCE_BUSY bit for busy status checking. + * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE + * instance's registers are accessed + * (0 for 1st instance, 10 for 2nd instance). + * + *VCE_STATUS + *|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB | + *|----+----+-----------+----+----+----+----------+---------+----| + *|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0| + * + * VCE team suggest use bit 3--bit 6 for busy status check + */ + mutex_lock(&adev->grbm_idx_mutex); + WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); + if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); + } + WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10); + if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); + } + WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); + mutex_unlock(&adev->grbm_idx_mutex); + + if (srbm_soft_reset) { + adev->vce.srbm_soft_reset = srbm_soft_reset; + return true; + } else { + adev->vce.srbm_soft_reset = 0; + return false; + } +} + +static int vce_v4_0_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 srbm_soft_reset; + + if (!adev->vce.srbm_soft_reset) + return 0; + srbm_soft_reset = adev->vce.srbm_soft_reset; + + if (srbm_soft_reset) { + u32 tmp; + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + } + + return 0; +} + +static int vce_v4_0_pre_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!adev->vce.srbm_soft_reset) + return 0; + + mdelay(5); + + return vce_v4_0_suspend(adev); +} + + +static int vce_v4_0_post_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!adev->vce.srbm_soft_reset) + return 0; + + mdelay(5); + + return vce_v4_0_resume(adev); +} + +static void vce_v4_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override) +{ + u32 tmp, data; + + tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL)); + if (override) + data |= VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK; + else + data &= ~VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK; + + if (tmp != data) + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data); +} + +static void vce_v4_0_set_vce_sw_clock_gating(struct amdgpu_device *adev, + bool gated) +{ + u32 data; + + /* Set Override to disable Clock Gating */ + vce_v4_0_override_vce_clock_gating(adev, true); + + /* This function enables MGCG which is controlled by firmware. + With the clocks in the gated state the core is still + accessible but the firmware will throttle the clocks on the + fly as necessary. + */ + if (gated) { + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B)); + data |= 0x1ff; + data &= ~0xef0000; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); + data |= 0x3ff000; + data &= ~0xffc00000; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2)); + data |= 0x2; + data &= ~0x00010000; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING)); + data |= 0x37f; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); + data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK | + VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK | + VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK | + 0x8; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); + } else { + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B)); + data &= ~0x80010; + data |= 0xe70008; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); + data |= 0xffc00000; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2)); + data |= 0x10000; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING)); + data &= ~0xffc00000; + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data); + + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); + data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK | + VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK | + VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK | + 0x8); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); + } + vce_v4_0_override_vce_clock_gating(adev, false); +} + +static void vce_v4_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) +{ + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); + + if (enable) + tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; + else + tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; + + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); +} + +static int vce_v4_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + int i; + + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_TONGA) || + (adev->asic_type == CHIP_FIJI)) + vce_v4_0_set_bypass_mode(adev, enable); + + if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) + return 0; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < 2; i++) { + /* Program VCE Instance 0 or 1 if not harvested */ + if (adev->vce.harvest_config & (1 << i)) + continue; + + WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i); + + if (enable) { + /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */ + uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A); + data &= ~(0xf | 0xff0); + data |= ((0x0 << 0) | (0x04 << 4)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data); + + /* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */ + data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING); + data &= ~(0xf | 0xff0); + data |= ((0x0 << 0) | (0x04 << 4)); + WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data); + } + + vce_v4_0_set_vce_sw_clock_gating(adev, enable); + } + + WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); + mutex_unlock(&adev->grbm_idx_mutex); + + return 0; +} + +static int vce_v4_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + /* This doesn't actually powergate the VCE block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE)) + return 0; + + if (state == AMD_PG_STATE_GATE) + /* XXX do we need a vce_v4_0_stop()? */ + return 0; + else + return vce_v4_0_start(adev); +} +#endif + +static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch) +{ + amdgpu_ring_write(ring, VCE_CMD_IB_VM); + amdgpu_ring_write(ring, vm_id); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); +} + +static void vce_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) +{ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, VCE_CMD_FENCE); + amdgpu_ring_write(ring, addr); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, VCE_CMD_TRAP); +} + +static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, VCE_CMD_END); +} + +static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, + unsigned int vm_id, uint64_t pd_addr) +{ + unsigned eng = ring->idx; + unsigned i; + + pd_addr = pd_addr | 0x1; /* valid bit */ + /* now only use physical base address of PDE and valid */ + BUG_ON(pd_addr & 0xFFFF00000000003EULL); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; + uint32_t req = hub->get_invalidate_req(vm_id); + + amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, upper_32_bits(pd_addr)); + + amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + amdgpu_ring_write(ring, VCE_CMD_REG_WAIT); + amdgpu_ring_write(ring, + (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2); + amdgpu_ring_write(ring, 0xffffffff); + amdgpu_ring_write(ring, lower_32_bits(pd_addr)); + + /* flush TLB */ + amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); + amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2); + amdgpu_ring_write(ring, req); + + /* wait for flush */ + amdgpu_ring_write(ring, VCE_CMD_REG_WAIT); + amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); + amdgpu_ring_write(ring, 1 << vm_id); + amdgpu_ring_write(ring, 1 << vm_id); + } +} + +static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + uint32_t val = 0; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val, + ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + return 0; +} + +static int vce_v4_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: VCE\n"); + + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_STATUS), + VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK, + ~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK); + + switch (entry->src_data[0]) { + case 0: + case 1: + case 2: + amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +const struct amd_ip_funcs vce_v4_0_ip_funcs = { + .name = "vce_v4_0", + .early_init = vce_v4_0_early_init, + .late_init = NULL, + .sw_init = vce_v4_0_sw_init, + .sw_fini = vce_v4_0_sw_fini, + .hw_init = vce_v4_0_hw_init, + .hw_fini = vce_v4_0_hw_fini, + .suspend = vce_v4_0_suspend, + .resume = vce_v4_0_resume, + .is_idle = NULL /* vce_v4_0_is_idle */, + .wait_for_idle = NULL /* vce_v4_0_wait_for_idle */, + .check_soft_reset = NULL /* vce_v4_0_check_soft_reset */, + .pre_soft_reset = NULL /* vce_v4_0_pre_soft_reset */, + .soft_reset = NULL /* vce_v4_0_soft_reset */, + .post_soft_reset = NULL /* vce_v4_0_post_soft_reset */, + .set_clockgating_state = vce_v4_0_set_clockgating_state, + .set_powergating_state = NULL /* vce_v4_0_set_powergating_state */, +}; + +static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0x3f, + .nop = VCE_CMD_NO_OP, + .support_64bit_ptrs = false, + .get_rptr = vce_v4_0_ring_get_rptr, + .get_wptr = vce_v4_0_ring_get_wptr, + .set_wptr = vce_v4_0_ring_set_wptr, + .parse_cs = amdgpu_vce_ring_parse_cs_vm, + .emit_frame_size = + 17 * AMDGPU_MAX_VMHUBS + /* vce_v4_0_emit_vm_flush */ + 5 + 5 + /* amdgpu_vce_ring_emit_fence x2 vm fence */ + 1, /* vce_v4_0_ring_insert_end */ + .emit_ib_size = 5, /* vce_v4_0_ring_emit_ib */ + .emit_ib = vce_v4_0_ring_emit_ib, + .emit_vm_flush = vce_v4_0_emit_vm_flush, + .emit_fence = vce_v4_0_ring_emit_fence, + .test_ring = amdgpu_vce_ring_test_ring, + .test_ib = amdgpu_vce_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_end = vce_v4_0_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vce_ring_begin_use, + .end_use = amdgpu_vce_ring_end_use, +}; + +static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->vce.num_rings; i++) + adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs; + DRM_INFO("VCE enabled in VM mode\n"); +} + +static const struct amdgpu_irq_src_funcs vce_v4_0_irq_funcs = { + .set = vce_v4_0_set_interrupt_state, + .process = vce_v4_0_process_interrupt, +}; + +static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->vce.irq.num_types = 1; + adev->vce.irq.funcs = &vce_v4_0_irq_funcs; +}; + +const struct amdgpu_ip_block_version vce_v4_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 4, + .minor = 0, + .rev = 0, + .funcs = &vce_v4_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.h new file mode 100644 index 000000000000..a32beda6a473 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCE_V4_0_H__ +#define __VCE_V4_0_H__ + +extern const struct amdgpu_ip_block_version vce_v4_0_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c new file mode 100644 index 000000000000..071f56e439bb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -0,0 +1,424 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "soc15.h" + + +#include "vega10/soc15ip.h" +#include "vega10/OSSSYS/osssys_4_0_offset.h" +#include "vega10/OSSSYS/osssys_4_0_sh_mask.h" + +#include "soc15_common.h" +#include "vega10_ih.h" + + + +static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); + +/** + * vega10_ih_enable_interrupts - Enable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Enable the interrupt ring buffer (VEGA10). + */ +static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + adev->irq.ih.enabled = true; +} + +/** + * vega10_ih_disable_interrupts - Disable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Disable the interrupt ring buffer (VEGA10). + */ +static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + /* set rptr, wptr to 0 */ + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); + adev->irq.ih.enabled = false; + adev->irq.ih.rptr = 0; +} + +/** + * vega10_ih_irq_init - init and enable the interrupt ring + * + * @adev: amdgpu_device pointer + * + * Allocate a ring buffer for the interrupt controller, + * enable the RLC, disable interrupts, enable the IH + * ring buffer and enable it (VI). + * Called at device load and reume. + * Returns 0 for success, errors for failure. + */ +static int vega10_ih_irq_init(struct amdgpu_device *adev) +{ + int ret = 0; + int rb_bufsz; + u32 ih_rb_cntl, ih_doorbell_rtpr; + u32 tmp; + u64 wptr_off; + + /* disable irqs */ + vega10_ih_disable_interrupts(adev); + + nbio_v6_1_ih_control(adev); + + ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ + if (adev->irq.ih.use_bus_addr) { + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); + } else { + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); + } + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); + /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); + + if (adev->irq.msi_enabled) + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); + + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + + /* set the writeback address whether it's enabled or not */ + if (adev->irq.ih.use_bus_addr) + wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); + else + wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off)); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF); + + /* set rptr, wptr to 0 */ + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); + + ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR)); + if (adev->irq.ih.use_doorbell) { + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, + OFFSET, adev->irq.ih.doorbell_index); + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, + ENABLE, 1); + } else { + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, + ENABLE, 0); + } + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr); + nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); + + tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL)); + tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, + CLIENT18_IS_STORM_CLIENT, 1); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp); + + tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL)); + tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp); + + pci_set_master(adev->pdev); + + /* enable interrupts */ + vega10_ih_enable_interrupts(adev); + + return ret; +} + +/** + * vega10_ih_irq_disable - disable interrupts + * + * @adev: amdgpu_device pointer + * + * Disable interrupts on the hw (VEGA10). + */ +static void vega10_ih_irq_disable(struct amdgpu_device *adev) +{ + vega10_ih_disable_interrupts(adev); + + /* Wait and acknowledge irq */ + mdelay(1); +} + +/** + * vega10_ih_get_wptr - get the IH ring buffer wptr + * + * @adev: amdgpu_device pointer + * + * Get the IH ring buffer wptr from either the register + * or the writeback memory buffer (VEGA10). Also check for + * ring buffer overflow and deal with it. + * Returns the value of the wptr. + */ +static u32 vega10_ih_get_wptr(struct amdgpu_device *adev) +{ + u32 wptr, tmp; + + if (adev->irq.ih.use_bus_addr) + wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); + else + wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); + + /* When a ring buffer overflow happen start parsing interrupt + * from the last not overwritten vector (wptr + 32). Hopefully + * this should allow us to catchup. + */ + tmp = (wptr + 32) & adev->irq.ih.ptr_mask; + dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", + wptr, adev->irq.ih.rptr, tmp); + adev->irq.ih.rptr = tmp; + + tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); + } + return (wptr & adev->irq.ih.ptr_mask); +} + +/** + * vega10_ih_decode_iv - decode an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Decodes the interrupt vector at the current rptr + * position and also advance the position. + */ +static void vega10_ih_decode_iv(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + /* wptr/rptr are in bytes! */ + u32 ring_index = adev->irq.ih.rptr >> 2; + uint32_t dw[8]; + + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); + dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); + dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); + dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); + dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); + dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]); + dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]); + + entry->client_id = dw[0] & 0xff; + entry->src_id = (dw[0] >> 8) & 0xff; + entry->ring_id = (dw[0] >> 16) & 0xff; + entry->vm_id = (dw[0] >> 24) & 0xf; + entry->vm_id_src = (dw[0] >> 31); + entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); + entry->timestamp_src = dw[2] >> 31; + entry->pas_id = dw[3] & 0xffff; + entry->pasid_src = dw[3] >> 31; + entry->src_data[0] = dw[4]; + entry->src_data[1] = dw[5]; + entry->src_data[2] = dw[6]; + entry->src_data[3] = dw[7]; + + + /* wptr/rptr are in bytes! */ + adev->irq.ih.rptr += 32; +} + +/** + * vega10_ih_set_rptr - set the IH ring buffer rptr + * + * @adev: amdgpu_device pointer + * + * Set the IH ring buffer rptr. + */ +static void vega10_ih_set_rptr(struct amdgpu_device *adev) +{ + if (adev->irq.ih.use_doorbell) { + /* XXX check if swapping is necessary on BE */ + if (adev->irq.ih.use_bus_addr) + adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; + else + adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; + WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); + } else { + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr); + } +} + +static int vega10_ih_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + vega10_ih_set_interrupt_funcs(adev); + return 0; +} + +static int vega10_ih_sw_init(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = amdgpu_ih_ring_init(adev, 256 * 1024, true); + if (r) + return r; + + adev->irq.ih.use_doorbell = true; + adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; + + r = amdgpu_irq_init(adev); + + return r; +} + +static int vega10_ih_sw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_irq_fini(adev); + amdgpu_ih_ring_fini(adev); + + return 0; +} + +static int vega10_ih_hw_init(void *handle) +{ + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + r = vega10_ih_irq_init(adev); + if (r) + return r; + + return 0; +} + +static int vega10_ih_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + vega10_ih_irq_disable(adev); + + return 0; +} + +static int vega10_ih_suspend(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return vega10_ih_hw_fini(adev); +} + +static int vega10_ih_resume(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return vega10_ih_hw_init(adev); +} + +static bool vega10_ih_is_idle(void *handle) +{ + /* todo */ + return true; +} + +static int vega10_ih_wait_for_idle(void *handle) +{ + /* todo */ + return -ETIMEDOUT; +} + +static int vega10_ih_soft_reset(void *handle) +{ + /* todo */ + + return 0; +} + +static int vega10_ih_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + return 0; +} + +static int vega10_ih_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +const struct amd_ip_funcs vega10_ih_ip_funcs = { + .name = "vega10_ih", + .early_init = vega10_ih_early_init, + .late_init = NULL, + .sw_init = vega10_ih_sw_init, + .sw_fini = vega10_ih_sw_fini, + .hw_init = vega10_ih_hw_init, + .hw_fini = vega10_ih_hw_fini, + .suspend = vega10_ih_suspend, + .resume = vega10_ih_resume, + .is_idle = vega10_ih_is_idle, + .wait_for_idle = vega10_ih_wait_for_idle, + .soft_reset = vega10_ih_soft_reset, + .set_clockgating_state = vega10_ih_set_clockgating_state, + .set_powergating_state = vega10_ih_set_powergating_state, +}; + +static const struct amdgpu_ih_funcs vega10_ih_funcs = { + .get_wptr = vega10_ih_get_wptr, + .decode_iv = vega10_ih_decode_iv, + .set_rptr = vega10_ih_set_rptr +}; + +static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) +{ + if (adev->irq.ih_funcs == NULL) + adev->irq.ih_funcs = &vega10_ih_funcs; +} + +const struct amdgpu_ip_block_version vega10_ih_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 4, + .minor = 0, + .rev = 0, + .funcs = &vega10_ih_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.h b/drivers/gpu/drm/amd/amdgpu/vega10_ih.h new file mode 100644 index 000000000000..82edd28b9972 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.h @@ -0,0 +1,30 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VEGA10_IH_H__ +#define __VEGA10_IH_H__ + +extern const struct amd_ip_funcs vega10_ih_ip_funcs; +extern const struct amdgpu_ip_block_version vega10_ih_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h new file mode 100644 index 000000000000..8de4ccce5e38 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h @@ -0,0 +1,3335 @@ +/* + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VEGA10_SDMA_PKT_OPEN_H_ +#define __VEGA10_SDMA_PKT_OPEN_H_ + +#define SDMA_OP_NOP 0 +#define SDMA_OP_COPY 1 +#define SDMA_OP_WRITE 2 +#define SDMA_OP_INDIRECT 4 +#define SDMA_OP_FENCE 5 +#define SDMA_OP_TRAP 6 +#define SDMA_OP_SEM 7 +#define SDMA_OP_POLL_REGMEM 8 +#define SDMA_OP_COND_EXE 9 +#define SDMA_OP_ATOMIC 10 +#define SDMA_OP_CONST_FILL 11 +#define SDMA_OP_PTEPDE 12 +#define SDMA_OP_TIMESTAMP 13 +#define SDMA_OP_SRBM_WRITE 14 +#define SDMA_OP_PRE_EXE 15 +#define SDMA_OP_DUMMY_TRAP 16 +#define SDMA_SUBOP_TIMESTAMP_SET 0 +#define SDMA_SUBOP_TIMESTAMP_GET 1 +#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 +#define SDMA_SUBOP_COPY_LINEAR 0 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 +#define SDMA_SUBOP_COPY_TILED 1 +#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 +#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 +#define SDMA_SUBOP_COPY_SOA 3 +#define SDMA_SUBOP_COPY_DIRTY_PAGE 7 +#define SDMA_SUBOP_COPY_LINEAR_PHY 8 +#define SDMA_SUBOP_WRITE_LINEAR 0 +#define SDMA_SUBOP_WRITE_TILED 1 +#define SDMA_SUBOP_PTEPDE_GEN 0 +#define SDMA_SUBOP_PTEPDE_COPY 1 +#define SDMA_SUBOP_PTEPDE_RMW 2 +#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 +#define SDMA_SUBOP_DATA_FILL_MULTI 1 +#define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 +#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 +#define SDMA_SUBOP_POLL_MEM_VERIFY 3 +#define HEADER_AGENT_DISPATCH 4 +#define HEADER_BARRIER 5 +#define SDMA_OP_AQL_COPY 0 +#define SDMA_OP_AQL_BARRIER_OR 0 + +/*define for op field*/ +#define SDMA_PKT_HEADER_op_offset 0 +#define SDMA_PKT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_HEADER_op_shift 0 +#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_HEADER_sub_op_offset 0 +#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_HEADER_sub_op_shift 8 +#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) + +/*define for all field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) + +/*define for dst_gcc field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) + +/*define for dst_sys field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) + +/*define for dst_snoop field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) + +/*define for dst_gpa field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) + +/*define for src_sys field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) + +/*define for src_snoop field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) + +/*define for src_gpa field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_gcc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) + +/*define for dst_sys field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) + +/*define for dst_log field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) + +/*define for dst_snoop field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) + +/*define for dst_gpa field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_gcc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) + +/*define for src_sys field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) + +/*define for src_snoop field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) + +/*define for src_gpa field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) + +/*define for dst1_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST1_ADDR_LO word*/ +/*define for dst1_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) + +/*define for DST1_ADDR_HI word*/ +/*define for dst1_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) + +/*define for DST2_ADDR_LO word*/ +/*define for dst2_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) + +/*define for DST2_ADDR_HI word*/ +/*define for dst2_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) + +/*define for elementsize field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) + +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_8 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) + +/*define for DW_9 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) + +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) + +/*define for DW_10 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) + +/*define for DW_11 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) + +/*define for DW_12 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 +#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 +#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 +#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 +#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16 +#define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 +#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 +#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 +#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 +#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 +#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift) + +/*define for videocopy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) + +/*define for TILED_ADDR_LO_0 word*/ +/*define for tiled_addr0_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) + +/*define for TILED_ADDR_HI_0 word*/ +/*define for tiled_addr0_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) + +/*define for TILED_ADDR_LO_1 word*/ +/*define for tiled_addr1_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) + +/*define for TILED_ADDR_HI_1 word*/ +/*define for tiled_addr1_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) + +/*define for DW_5 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) + +/*define for DW_6 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) + +/*define for DW_7 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift) + +/*define for DW_8 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) + +/*define for DW_9 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) + +/*define for DW_10 word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_T2T packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 +#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) + +/*define for src_width field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) + +/*define for DW_5 word*/ +/*define for src_height field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) + +/*define for src_depth field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) + +/*define for DW_6 word*/ +/*define for src_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) + +/*define for src_swizzle_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) + +/*define for src_dimension field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) + +/*define for src_epitch field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 16 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) + +/*define for DW_10 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) + +/*define for dst_width field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 +#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) + +/*define for DW_11 word*/ +/*define for dst_height field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 +#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) + +/*define for dst_depth field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 +#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) + +/*define for DW_12 word*/ +/*define for dst_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) + +/*define for dst_swizzle_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) + +/*define for dst_dimension field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 +#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) + +/*define for dst_epitch field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 16 +#define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift) + +/*define for DW_13 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) + +/*define for DW_14 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 +#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 +#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 20 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift) + +/*define for mip_id field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for tiled_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) + +/*define for tiled_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) + +/*define for DW_4 word*/ +/*define for tiled_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) + +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) + +/*define for DW_5 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) + +/*define for DW_6 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for linear_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) + +/*define for linear_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) + +/*define for DW_10 word*/ +/*define for linear_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) + +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) + +/*define for DW_11 word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) + +/*define for DW_13 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_STRUCT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) + +/*define for SB_ADDR_LO word*/ +/*define for sb_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) + +/*define for SB_ADDR_HI word*/ +/*define for sb_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) + +/*define for START_INDEX word*/ +/*define for start_index field*/ +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 +#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 +#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) + +/*define for DW_5 word*/ +/*define for stride field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) + +/*define for struct_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_UNTILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 +#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 +#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 +#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F +#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 20 +#define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 +#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 +#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) + +/*define for epitch field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF +#define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 +#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 +#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_COPY packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) + +/*define for ptepde_op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 +#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 +#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) + +/*define for pte_size field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) + +/*define for direction field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) + +/*define for ptepde_op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_BIT_FOR_DW word*/ +/*define for mask_first_xfer field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) + +/*define for mask_last_xfer field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) + +/*define for COUNT_IN_32B_XFER word*/ +/*define for count field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_RMW packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) + +/*define for gcc field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 +#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) + +/*define for sys field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) + +/*define for snp field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) + +/*define for gpa field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 +#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) + +/*define for MASK_LO word*/ +/*define for mask_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) + +/*define for MASK_HI word*/ +/*define for mask_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) + +/*define for VALUE_LO word*/ +/*define for value_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) + +/*define for VALUE_HI word*/ +/*define for value_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_INCR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) + +/*define for INIT_DW0 word*/ +/*define for init_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) + +/*define for INIT_DW1 word*/ +/*define for init_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) + +/*define for INCR_DW0 word*/ +/*define for incr_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) + +/*define for INCR_DW1 word*/ +/*define for incr_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 +#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_INDIRECT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 +#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 +#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) + +/*define for vmid field*/ +#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F +#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 +#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) + +/*define for BASE_LO word*/ +/*define for ib_base_31_0 field*/ +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 +#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) + +/*define for BASE_HI word*/ +/*define for ib_base_63_32 field*/ +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 +#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) + +/*define for IB_SIZE word*/ +/*define for ib_size field*/ +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 +#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) + +/*define for CSA_ADDR_LO word*/ +/*define for csa_addr_31_0 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) + +/*define for CSA_ADDR_HI word*/ +/*define for csa_addr_63_32 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_SEMAPHORE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 +#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) + +/*define for write_one field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 +#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) + +/*define for signal field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 +#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) + +/*define for mailbox field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 +#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_FENCE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_FENCE_HEADER_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_op_shift 0 +#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 +#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_FENCE_DATA_data_offset 3 +#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_DATA_data_shift 0 +#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_SRBM_WRITE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) + +/*define for byte_en field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 +#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) + +/*define for ADDR word*/ +/*define for addr field*/ +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 +#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 +#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 +#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_PRE_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 +#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) + +/*define for dev_sel field*/ +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 +#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_COND_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 +#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) + +/*define for REFERENCE word*/ +/*define for reference field*/ +#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 +#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 +#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_CONSTANT_FILL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) + +/*define for sw field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) + +/*define for fillsize field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 +#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DATA word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 +#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_DATA_FILL_MULTI packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) + +/*define for memlog_clr field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) + +/*define for BYTE_STRIDE word*/ +/*define for byte_stride field*/ +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) + +/*define for DMA_COUNT word*/ +/*define for dma_count field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for BYTE_COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REGMEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) + +/*define for hdp_flush field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 +#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) + +/*define for func field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 +#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) + +/*define for mem_poll field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 +#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) + +/*define for VALUE word*/ +/*define for value field*/ +#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 +#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 +#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) + +/*define for MASK word*/ +/*define for mask field*/ +#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 +#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 +#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) + +/*define for DW5 word*/ +/*define for interval field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF +#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 +#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) + +/*define for retry_count field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 +#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) + +/*define for SRC_ADDR word*/ +/*define for addr_31_2 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) + +/*define for DST_ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) + +/*define for ea field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) + +/*define for DST_ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) + +/*define for START_PAGE word*/ +/*define for addr_31_4 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) + +/*define for PAGE_NUM word*/ +/*define for page_num_31_0 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) + + +/* +** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) + +/*define for mode field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) + +/*define for PATTERN word*/ +/*define for pattern field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) + +/*define for CMP0_ADDR_START_LO word*/ +/*define for cmp0_start_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) + +/*define for CMP0_ADDR_START_HI word*/ +/*define for cmp0_start_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) + +/*define for CMP0_ADDR_END_LO word*/ +/*define for cmp1_end_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) + +/*define for CMP0_ADDR_END_HI word*/ +/*define for cmp1_end_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) + +/*define for CMP1_ADDR_START_LO word*/ +/*define for cmp1_start_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) + +/*define for CMP1_ADDR_START_HI word*/ +/*define for cmp1_start_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) + +/*define for CMP1_ADDR_END_LO word*/ +/*define for cmp1_end_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) + +/*define for CMP1_ADDR_END_HI word*/ +/*define for cmp1_end_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) + +/*define for REC_ADDR_LO word*/ +/*define for rec_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) + +/*define for REC_ADDR_HI word*/ +/*define for rec_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) + +/*define for RESERVED word*/ +/*define for reserved field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) + + +/* +** Definitions for SDMA_PKT_ATOMIC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 +#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) + +/*define for loop field*/ +#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 +#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) + +/*define for tmz field*/ +#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 +#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) + +/*define for atomic_op field*/ +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 +#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) + +/*define for SRC_DATA_LO word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) + +/*define for SRC_DATA_HI word*/ +/*define for src_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) + +/*define for CMP_DATA_LO word*/ +/*define for cmp_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) + +/*define for CMP_DATA_HI word*/ +/*define for cmp_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) + +/*define for LOOP_INTERVAL word*/ +/*define for loop_interval field*/ +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_SET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) + +/*define for INIT_DATA_LO word*/ +/*define for init_data_31_0 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) + +/*define for INIT_DATA_HI word*/ +/*define for init_data_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_DUMMY_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_NOP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_NOP_HEADER_op_offset 0 +#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_op_shift 0 +#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 +#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 +#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) + +/*define for count field*/ +#define SDMA_PKT_NOP_HEADER_count_offset 0 +#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF +#define SDMA_PKT_NOP_HEADER_count_shift 16 +#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_NOP_DATA0_data0_offset 1 +#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_NOP_DATA0_data0_shift 0 +#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) + + +/* +** Definitions for SDMA_AQL_PKT_HEADER packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 +#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 +#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) + + +/* +** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) + +/*define for RESERVED_DW1 word*/ +/*define for reserved_dw1 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) + +/*define for RETURN_ADDR_LO word*/ +/*define for return_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) + +/*define for RETURN_ADDR_HI word*/ +/*define for return_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for RESERVED_DW10 word*/ +/*define for reserved_dw10 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) + +/*define for RESERVED_DW11 word*/ +/*define for reserved_dw11 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) + +/*define for RESERVED_DW12 word*/ +/*define for reserved_dw12 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) + +/*define for RESERVED_DW13 word*/ +/*define for reserved_dw13 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) + +/*define for COMPLETION_SIGNAL_LO word*/ +/*define for completion_signal_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) + +/*define for COMPLETION_SIGNAL_HI word*/ +/*define for completion_signal_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) + + +/* +** Definitions for SDMA_AQL_PKT_BARRIER_OR packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) + +/*define for RESERVED_DW1 word*/ +/*define for reserved_dw1 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) + +/*define for DEPENDENT_ADDR_0_LO word*/ +/*define for dependent_addr_0_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) + +/*define for DEPENDENT_ADDR_0_HI word*/ +/*define for dependent_addr_0_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) + +/*define for DEPENDENT_ADDR_1_LO word*/ +/*define for dependent_addr_1_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) + +/*define for DEPENDENT_ADDR_1_HI word*/ +/*define for dependent_addr_1_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) + +/*define for DEPENDENT_ADDR_2_LO word*/ +/*define for dependent_addr_2_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) + +/*define for DEPENDENT_ADDR_2_HI word*/ +/*define for dependent_addr_2_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) + +/*define for DEPENDENT_ADDR_3_LO word*/ +/*define for dependent_addr_3_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) + +/*define for DEPENDENT_ADDR_3_HI word*/ +/*define for dependent_addr_3_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) + +/*define for DEPENDENT_ADDR_4_LO word*/ +/*define for dependent_addr_4_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) + +/*define for DEPENDENT_ADDR_4_HI word*/ +/*define for dependent_addr_4_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) + +/*define for RESERVED_DW12 word*/ +/*define for reserved_dw12 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) + +/*define for RESERVED_DW13 word*/ +/*define for reserved_dw13 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) + +/*define for COMPLETION_SIGNAL_LO word*/ +/*define for completion_signal_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) + +/*define for COMPLETION_SIGNAL_HI word*/ +/*define for completion_signal_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) + + +#endif /* __SDMA_PKT_OPEN_H_ */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 4a785d6acfb9..b1132f5e84fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -464,15 +464,9 @@ static void vi_detect_hw_virtualization(struct amdgpu_device *adev) } static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { - {mmGB_MACROTILE_MODE7, true}, }; static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { - {mmGB_TILE_MODE7, true}, - {mmGB_TILE_MODE12, true}, - {mmGB_TILE_MODE17, true}, - {mmGB_TILE_MODE23, true}, - {mmGB_MACROTILE_MODE7, true}, }; static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { @@ -751,6 +745,11 @@ static int vi_asic_reset(struct amdgpu_device *adev) return r; } +static u32 vi_get_config_memsize(struct amdgpu_device *adev) +{ + return RREG32(mmCONFIG_MEMSIZE); +} + static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, u32 cntl_reg, u32 status_reg) { @@ -790,6 +789,8 @@ static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) return r; r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); + if (r) + return r; return 0; } @@ -900,8 +901,12 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .get_xclk = &vi_get_xclk, .set_uvd_clocks = &vi_set_uvd_clocks, .set_vce_clocks = &vi_set_vce_clocks, + .get_config_memsize = &vi_get_config_memsize, }; +#define CZ_REV_BRISTOL(rev) \ + ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6)) + static int vi_common_early_init(void *handle) { bool smc_enabled = false; @@ -1027,7 +1032,25 @@ static int vi_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x50; break; case CHIP_POLARIS12: - adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_DRM_LS | + AMD_CG_SUPPORT_UVD_MGCG | + AMD_CG_SUPPORT_VCE_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x64; break; @@ -1038,7 +1061,6 @@ static int vi_common_early_init(void *handle) AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_CGTS | - AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_CGTS_LS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | @@ -1050,7 +1072,7 @@ static int vi_common_early_init(void *handle) AMD_CG_SUPPORT_VCE_MGCG; /* rev0 hardware requires workarounds to support PG */ adev->pg_flags = 0; - if (adev->rev_id != 0x00) { + if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | AMD_PG_SUPPORT_GFX_PIPELINE | @@ -1067,7 +1089,6 @@ static int vi_common_early_init(void *handle) AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_CGTS | - AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_CGTS_LS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | @@ -1090,8 +1111,8 @@ static int vi_common_early_init(void *handle) return -EINVAL; } - if (amdgpu_smc_load_fw && smc_enabled) - adev->firmware.smu_load = true; + /* vi use smc load by default */ + adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); amdgpu_get_pcie_info(adev); @@ -1391,27 +1412,30 @@ static int vi_common_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (amdgpu_sriov_vf(adev)) + return 0; + switch (adev->asic_type) { case CHIP_FIJI: vi_update_bif_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); vi_update_hdp_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); vi_update_hdp_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); vi_update_rom_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; case CHIP_CARRIZO: case CHIP_STONEY: vi_update_bif_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); vi_update_hdp_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); vi_update_hdp_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); vi_update_drm_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; case CHIP_TONGA: case CHIP_POLARIS10: @@ -1435,6 +1459,9 @@ static void vi_common_get_clockgating_state(void *handle, u32 *flags) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int data; + if (amdgpu_sriov_vf(adev)) + *flags = 0; + /* AMD_CG_SUPPORT_BIF_LS */ data = RREG32_PCIE(ixPCIE_CNTL2); if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h index 719587b8b0cb..575d7aed5d32 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.h +++ b/drivers/gpu/drm/amd/amdgpu/vi.h @@ -28,116 +28,4 @@ void vi_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int vi_set_ip_blocks(struct amdgpu_device *adev); -struct amdgpu_ce_ib_state -{ - uint32_t ce_ib_completion_status; - uint32_t ce_constegnine_count; - uint32_t ce_ibOffset_ib1; - uint32_t ce_ibOffset_ib2; -}; /* Total of 4 DWORD */ - -struct amdgpu_de_ib_state -{ - uint32_t ib_completion_status; - uint32_t de_constEngine_count; - uint32_t ib_offset_ib1; - uint32_t ib_offset_ib2; - uint32_t preamble_begin_ib1; - uint32_t preamble_begin_ib2; - uint32_t preamble_end_ib1; - uint32_t preamble_end_ib2; - uint32_t draw_indirect_baseLo; - uint32_t draw_indirect_baseHi; - uint32_t disp_indirect_baseLo; - uint32_t disp_indirect_baseHi; - uint32_t gds_backup_addrlo; - uint32_t gds_backup_addrhi; - uint32_t index_base_addrlo; - uint32_t index_base_addrhi; - uint32_t sample_cntl; -}; /* Total of 17 DWORD */ - -struct amdgpu_ce_ib_state_chained_ib -{ - /* section of non chained ib part */ - uint32_t ce_ib_completion_status; - uint32_t ce_constegnine_count; - uint32_t ce_ibOffset_ib1; - uint32_t ce_ibOffset_ib2; - - /* section of chained ib */ - uint32_t ce_chainib_addrlo_ib1; - uint32_t ce_chainib_addrlo_ib2; - uint32_t ce_chainib_addrhi_ib1; - uint32_t ce_chainib_addrhi_ib2; - uint32_t ce_chainib_size_ib1; - uint32_t ce_chainib_size_ib2; -}; /* total 10 DWORD */ - -struct amdgpu_de_ib_state_chained_ib -{ - /* section of non chained ib part */ - uint32_t ib_completion_status; - uint32_t de_constEngine_count; - uint32_t ib_offset_ib1; - uint32_t ib_offset_ib2; - - /* section of chained ib */ - uint32_t chain_ib_addrlo_ib1; - uint32_t chain_ib_addrlo_ib2; - uint32_t chain_ib_addrhi_ib1; - uint32_t chain_ib_addrhi_ib2; - uint32_t chain_ib_size_ib1; - uint32_t chain_ib_size_ib2; - - /* section of non chained ib part */ - uint32_t preamble_begin_ib1; - uint32_t preamble_begin_ib2; - uint32_t preamble_end_ib1; - uint32_t preamble_end_ib2; - - /* section of chained ib */ - uint32_t chain_ib_pream_addrlo_ib1; - uint32_t chain_ib_pream_addrlo_ib2; - uint32_t chain_ib_pream_addrhi_ib1; - uint32_t chain_ib_pream_addrhi_ib2; - - /* section of non chained ib part */ - uint32_t draw_indirect_baseLo; - uint32_t draw_indirect_baseHi; - uint32_t disp_indirect_baseLo; - uint32_t disp_indirect_baseHi; - uint32_t gds_backup_addrlo; - uint32_t gds_backup_addrhi; - uint32_t index_base_addrlo; - uint32_t index_base_addrhi; - uint32_t sample_cntl; -}; /* Total of 27 DWORD */ - -struct amdgpu_gfx_meta_data -{ - /* 4 DWORD, address must be 4KB aligned */ - struct amdgpu_ce_ib_state ce_payload; - uint32_t reserved1[60]; - /* 17 DWORD, address must be 64B aligned */ - struct amdgpu_de_ib_state de_payload; - /* PFP IB base address which get pre-empted */ - uint32_t DeIbBaseAddrLo; - uint32_t DeIbBaseAddrHi; - uint32_t reserved2[941]; -}; /* Total of 4K Bytes */ - -struct amdgpu_gfx_meta_data_chained_ib -{ - /* 10 DWORD, address must be 4KB aligned */ - struct amdgpu_ce_ib_state_chained_ib ce_payload; - uint32_t reserved1[54]; - /* 27 DWORD, address must be 64B aligned */ - struct amdgpu_de_ib_state_chained_ib de_payload; - /* PFP IB base address which get pre-empted */ - uint32_t DeIbBaseAddrLo; - uint32_t DeIbBaseAddrHi; - uint32_t reserved2[931]; -}; /* Total of 4K Bytes */ - #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h index 7a3863a45f0a..b3a86e0e96e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vid.h +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -195,6 +195,7 @@ * 1 - Stream * 2 - Bypass */ +#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) #define PACKET3_COPY_DATA 0x40 #define PACKET3_PFP_SYNC_ME 0x42 #define PACKET3_SURFACE_SYNC 0x43 diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h index 50e893325141..9b9699fc433f 100644 --- a/drivers/gpu/drm/amd/include/amd_acpi.h +++ b/drivers/gpu/drm/amd/include/amd_acpi.h @@ -146,6 +146,7 @@ struct atcs_pref_req_output { # define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED (1 << 7) # define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED (1 << 12) # define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED (1 << 14) +# define ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED (1 << 20) #define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS 0x1 /* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS * ARG1: none @@ -300,6 +301,17 @@ struct atcs_pref_req_output { # define ATIF_XGP_PORT (1 << 1) # define ATIF_VGA_ENABLED_GRAPHICS_DEVICE (1 << 2) # define ATIF_XGP_PORT_IN_DOCK (1 << 3) +#define ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION 0x15 +/* ARG0: ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION + * ARG1: none + * OUTPUT: + * WORD - number of reported external gfx devices + * WORD - device structure size in bytes (excludes device size field) + * WORD - flags \ + * WORD - bus number / repeated structure + */ +/* flags */ +# define ATIF_EXTERNAL_GRAPHICS_PORT (1 << 0) /* ATPX */ #define ATPX_FUNCTION_VERIFY_INTERFACE 0x0 diff --git a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h index 5725bf85eacc..7e5a965450c7 100644 --- a/drivers/gpu/drm/amd/include/amd_pcie_helpers.h +++ b/drivers/gpu/drm/amd/include/amd_pcie_helpers.h @@ -82,7 +82,7 @@ static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, switch (pcie_lane_width_cap) { case 0: - printk(KERN_ERR "No valid PCIE lane width reported"); + pr_err("No valid PCIE lane width reported\n"); break; case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: new_pcie_lanes = 1; @@ -126,7 +126,7 @@ static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap, } } if (j > 7) - printk(KERN_ERR "Cannot find a valid PCIE lane width!"); + pr_err("Cannot find a valid PCIE lane width!\n"); } } break; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 43f45adeccd1..2ccf44e580de 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -47,6 +47,7 @@ enum amd_asic_type { CHIP_POLARIS10, CHIP_POLARIS11, CHIP_POLARIS12, + CHIP_VEGA10, CHIP_LAST, }; @@ -67,12 +68,15 @@ enum amd_ip_block_type { AMD_IP_BLOCK_TYPE_GMC, AMD_IP_BLOCK_TYPE_IH, AMD_IP_BLOCK_TYPE_SMC, + AMD_IP_BLOCK_TYPE_PSP, AMD_IP_BLOCK_TYPE_DCE, AMD_IP_BLOCK_TYPE_GFX, AMD_IP_BLOCK_TYPE_SDMA, AMD_IP_BLOCK_TYPE_UVD, AMD_IP_BLOCK_TYPE_VCE, AMD_IP_BLOCK_TYPE_ACP, + AMD_IP_BLOCK_TYPE_GFXHUB, + AMD_IP_BLOCK_TYPE_MMHUB }; enum amd_clockgating_state { @@ -120,6 +124,20 @@ enum amd_vce_level { AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ }; +enum amd_pp_profile_type { + AMD_PP_GFX_PROFILE, + AMD_PP_COMPUTE_PROFILE, +}; + +struct amd_pp_profile { + enum amd_pp_profile_type type; + uint32_t min_sclk; + uint32_t min_mclk; + uint16_t activity_threshold; + uint8_t up_hyst; + uint8_t down_hyst; +}; + /* CG flags */ #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) @@ -143,6 +161,8 @@ enum amd_vce_level { #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) +#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) +#define AMD_CG_SUPPORT_DF_MGCG (1 << 23) /* PG flags */ #define AMD_PG_SUPPORT_GFX_PG (1 << 0) diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h index 0f6c6c8d089b..7155312326e8 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h @@ -11891,5 +11891,9 @@ #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002 +#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000001L +#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000000 +#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000002L +#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000001 #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h index 4446d43d2a8f..bd3685166779 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h @@ -1272,5 +1272,6 @@ #define ixROM_SW_DATA_63 0xc0600120 #define ixROM_SW_DATA_64 0xc0600124 #define ixCURRENT_PG_STATUS 0xc020029c +#define ixCURRENT_PG_STATUS_APU 0xd020029c #endif /* SMU_7_1_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h index 0333d880bc9e..b89347ed1a40 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h @@ -1245,4 +1245,6 @@ #define ixGC_CAC_ACC_CU15 0xc9 #define ixGC_CAC_OVRD_CU 0xe7 #define ixCURRENT_PG_STATUS 0xc020029c +#define ixCURRENT_PG_STATUS_APU 0xd020029c + #endif /* SMU_7_1_3_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h new file mode 100644 index 000000000000..1650dc369f7d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_DEFAULT_HEADER +#define _athub_1_0_DEFAULT_HEADER + + +// addressBlock: athub_atsdec +#define mmATC_ATS_CNTL_DEFAULT 0x009a0800 +#define mmATC_ATS_STATUS_DEFAULT 0x00000000 +#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff +#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000 +#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000 +#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000 +#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff +#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000 +#define mmATHUB_MISC_CNTL_DEFAULT 0x00040200 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000 +#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000 +#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000 +#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000 +#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +#define mmATHUB_COMMAND_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 +#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 +#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmATS_IH_CREDIT_DEFAULT 0x00150002 +#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002 +#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000 +#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000 +#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000 + + +// addressBlock: athub_xpbdec +#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000 +#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000 +#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000 +#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG0_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG1_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG2_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG3_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG4_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG5_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG6_DEFAULT 0x00000000 +#define mmXPB_CLG_CFG7_DEFAULT 0x00000000 +#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000 +#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000 +#define mmXPB_LB_ADDR_DEFAULT 0x00000000 +#define mmXPB_WCB_STS_DEFAULT 0x00000000 +#define mmXPB_HST_CFG_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f +#define mmXPB_P2P_BAR0_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR1_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR2_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR3_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR4_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR5_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR6_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR7_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000 +#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000 +#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000 +#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000 +#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000 +#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000 +#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000 +#define mmXPB_CLK_GAT_DEFAULT 0x00040400 +#define mmXPB_INTF_CFG_DEFAULT 0x000f1040 +#define mmXPB_INTF_STS_DEFAULT 0x00000000 +#define mmXPB_PIPE_STS_DEFAULT 0x00000000 +#define mmXPB_SUB_CTRL_DEFAULT 0x00000000 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000 +#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000 +#define mmXPB_STICKY_DEFAULT 0x00000000 +#define mmXPB_STICKY_W1C_DEFAULT 0x00000000 +#define mmXPB_MISC_CFG_DEFAULT 0x4d585042 +#define mmXPB_INTF_CFG2_DEFAULT 0x00000040 +#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000 +#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000 +#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000 +#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x00000000 +#define mmXPB_CLG_MM_MATCH_DEFAULT 0x03000000 +#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000 +#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000 +#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040 +#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080 +#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0 +#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100 +#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140 +#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000 +#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0 +#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000 +#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040 +#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080 +#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0 + + +// addressBlock: athub_rpbdec +#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230 +#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0 +#define mmRPB_TAG_CONF_DEFAULT 0x00204020 +#define mmRPB_EFF_CNTL_DEFAULT 0x00001010 +#define mmRPB_ARB_CNTL_DEFAULT 0x00040404 +#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104 +#define mmRPB_BIF_CNTL_DEFAULT 0x01000404 +#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810 +#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810 +#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000 +#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000 +#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000 +#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000 +#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810 +#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000004 +#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00004040 +#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000 +#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000 +#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000 +#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000 +#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000 +#define mmRPB_ATS_CNTL_DEFAULT 0x58088422 +#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13 +#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14814 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h new file mode 100644 index 000000000000..80042e1c8770 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h @@ -0,0 +1,453 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_OFFSET_HEADER +#define _athub_1_0_OFFSET_HEADER + + + +// addressBlock: athub_atsdec +// base address: 0x3080 +#define mmATC_ATS_CNTL 0x0000 +#define mmATC_ATS_CNTL_BASE_IDX 0 +#define mmATC_ATS_STATUS 0x0003 +#define mmATC_ATS_STATUS_BASE_IDX 0 +#define mmATC_ATS_FAULT_CNTL 0x0004 +#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_INFO 0x0005 +#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006 +#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 +#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007 +#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 +#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008 +#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009 +#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 +#define mmATHUB_MISC_CNTL 0x000a +#define mmATHUB_MISC_CNTL_BASE_IDX 0 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 +#define mmATC_VMID0_PASID_MAPPING 0x000c +#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID1_PASID_MAPPING 0x000d +#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID2_PASID_MAPPING 0x000e +#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID3_PASID_MAPPING 0x000f +#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID4_PASID_MAPPING 0x0010 +#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID5_PASID_MAPPING 0x0011 +#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID6_PASID_MAPPING 0x0012 +#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID7_PASID_MAPPING 0x0013 +#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID8_PASID_MAPPING 0x0014 +#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID9_PASID_MAPPING 0x0015 +#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID10_PASID_MAPPING 0x0016 +#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID11_PASID_MAPPING 0x0017 +#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID12_PASID_MAPPING 0x0018 +#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID13_PASID_MAPPING 0x0019 +#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID14_PASID_MAPPING 0x001a +#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID15_PASID_MAPPING 0x001b +#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0 +#define mmATC_ATS_VMID_STATUS 0x001c +#define mmATC_ATS_VMID_STATUS_BASE_IDX 0 +#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d +#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0 +#define mmATC_PERFCOUNTER0_CFG 0x001e +#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER1_CFG 0x001f +#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER2_CFG 0x0020 +#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER3_CFG 0x0021 +#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022 +#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmATC_PERFCOUNTER_LO 0x0023 +#define mmATC_PERFCOUNTER_LO_BASE_IDX 0 +#define mmATC_PERFCOUNTER_HI 0x0024 +#define mmATC_PERFCOUNTER_HI_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL 0x0025 +#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_PASID_CNTL 0x0026 +#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027 +#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 +#define mmATHUB_COMMAND 0x0029 +#define mmATHUB_COMMAND_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a +#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b +#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c +#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d +#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e +#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f +#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030 +#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031 +#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032 +#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033 +#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034 +#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035 +#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036 +#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037 +#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038 +#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039 +#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 +#define mmATHUB_MEM_POWER_LS 0x003a +#define mmATHUB_MEM_POWER_LS_BASE_IDX 0 +#define mmATS_IH_CREDIT 0x003b +#define mmATS_IH_CREDIT_BASE_IDX 0 +#define mmATHUB_IH_CREDIT 0x003c +#define mmATHUB_IH_CREDIT_BASE_IDX 0 +#define mmATC_VMID16_PASID_MAPPING 0x003d +#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID17_PASID_MAPPING 0x003e +#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID18_PASID_MAPPING 0x003f +#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID19_PASID_MAPPING 0x0040 +#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID20_PASID_MAPPING 0x0041 +#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID21_PASID_MAPPING 0x0042 +#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID22_PASID_MAPPING 0x0043 +#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID23_PASID_MAPPING 0x0044 +#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID24_PASID_MAPPING 0x0045 +#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID25_PASID_MAPPING 0x0046 +#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID26_PASID_MAPPING 0x0047 +#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID27_PASID_MAPPING 0x0048 +#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID28_PASID_MAPPING 0x0049 +#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID29_PASID_MAPPING 0x004a +#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID30_PASID_MAPPING 0x004b +#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID31_PASID_MAPPING 0x004c +#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0 +#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d +#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0 +#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e +#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f +#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmATC_ATS_SDPPORT_CNTL 0x0050 +#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0 + + +// addressBlock: athub_xpbdec +// base address: 0x31f0 +#define mmXPB_RTR_SRC_APRTR0 0x005c +#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR1 0x005d +#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR2 0x005e +#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR3 0x005f +#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR4 0x0060 +#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR5 0x0061 +#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR6 0x0062 +#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR7 0x0063 +#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR8 0x0064 +#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR9 0x0065 +#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066 +#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067 +#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068 +#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069 +#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP0 0x006a +#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP1 0x006b +#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP2 0x006c +#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP3 0x006d +#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP4 0x006e +#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP5 0x006f +#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP6 0x0070 +#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP7 0x0071 +#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP8 0x0072 +#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP9 0x0073 +#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074 +#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075 +#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076 +#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077 +#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0 +#define mmXPB_CLG_CFG0 0x0078 +#define mmXPB_CLG_CFG0_BASE_IDX 0 +#define mmXPB_CLG_CFG1 0x0079 +#define mmXPB_CLG_CFG1_BASE_IDX 0 +#define mmXPB_CLG_CFG2 0x007a +#define mmXPB_CLG_CFG2_BASE_IDX 0 +#define mmXPB_CLG_CFG3 0x007b +#define mmXPB_CLG_CFG3_BASE_IDX 0 +#define mmXPB_CLG_CFG4 0x007c +#define mmXPB_CLG_CFG4_BASE_IDX 0 +#define mmXPB_CLG_CFG5 0x007d +#define mmXPB_CLG_CFG5_BASE_IDX 0 +#define mmXPB_CLG_CFG6 0x007e +#define mmXPB_CLG_CFG6_BASE_IDX 0 +#define mmXPB_CLG_CFG7 0x007f +#define mmXPB_CLG_CFG7_BASE_IDX 0 +#define mmXPB_CLG_EXTRA 0x0080 +#define mmXPB_CLG_EXTRA_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_MSK 0x0081 +#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0 +#define mmXPB_LB_ADDR 0x0082 +#define mmXPB_LB_ADDR_BASE_IDX 0 +#define mmXPB_WCB_STS 0x0083 +#define mmXPB_WCB_STS_BASE_IDX 0 +#define mmXPB_HST_CFG 0x0084 +#define mmXPB_HST_CFG_BASE_IDX 0 +#define mmXPB_P2P_BAR_CFG 0x0085 +#define mmXPB_P2P_BAR_CFG_BASE_IDX 0 +#define mmXPB_P2P_BAR0 0x0086 +#define mmXPB_P2P_BAR0_BASE_IDX 0 +#define mmXPB_P2P_BAR1 0x0087 +#define mmXPB_P2P_BAR1_BASE_IDX 0 +#define mmXPB_P2P_BAR2 0x0088 +#define mmXPB_P2P_BAR2_BASE_IDX 0 +#define mmXPB_P2P_BAR3 0x0089 +#define mmXPB_P2P_BAR3_BASE_IDX 0 +#define mmXPB_P2P_BAR4 0x008a +#define mmXPB_P2P_BAR4_BASE_IDX 0 +#define mmXPB_P2P_BAR5 0x008b +#define mmXPB_P2P_BAR5_BASE_IDX 0 +#define mmXPB_P2P_BAR6 0x008c +#define mmXPB_P2P_BAR6_BASE_IDX 0 +#define mmXPB_P2P_BAR7 0x008d +#define mmXPB_P2P_BAR7_BASE_IDX 0 +#define mmXPB_P2P_BAR_SETUP 0x008e +#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0 +#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090 +#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0 +#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091 +#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR0 0x0092 +#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR1 0x0093 +#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR2 0x0094 +#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR3 0x0095 +#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR4 0x0096 +#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR5 0x0097 +#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR6 0x0098 +#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR7 0x0099 +#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR8 0x009a +#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR9 0x009b +#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c +#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d +#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e +#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f +#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0 +#define mmXPB_CLK_GAT 0x00a0 +#define mmXPB_CLK_GAT_BASE_IDX 0 +#define mmXPB_INTF_CFG 0x00a1 +#define mmXPB_INTF_CFG_BASE_IDX 0 +#define mmXPB_INTF_STS 0x00a2 +#define mmXPB_INTF_STS_BASE_IDX 0 +#define mmXPB_PIPE_STS 0x00a3 +#define mmXPB_PIPE_STS_BASE_IDX 0 +#define mmXPB_SUB_CTRL 0x00a4 +#define mmXPB_SUB_CTRL_BASE_IDX 0 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0 +#define mmXPB_PERF_KNOBS 0x00a6 +#define mmXPB_PERF_KNOBS_BASE_IDX 0 +#define mmXPB_STICKY 0x00a7 +#define mmXPB_STICKY_BASE_IDX 0 +#define mmXPB_STICKY_W1C 0x00a8 +#define mmXPB_STICKY_W1C_BASE_IDX 0 +#define mmXPB_MISC_CFG 0x00a9 +#define mmXPB_MISC_CFG_BASE_IDX 0 +#define mmXPB_INTF_CFG2 0x00aa +#define mmXPB_INTF_CFG2_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_RD 0x00ab +#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac +#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0 +#define mmXPB_CLG_GFX_MATCH 0x00ad +#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0 +#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae +#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0 +#define mmXPB_CLG_MM_MATCH 0x00af +#define mmXPB_CLG_MM_MATCH_BASE_IDX 0 +#define mmXPB_CLG_MM_MATCH_MSK 0x00b0 +#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1 +#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2 +#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3 +#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4 +#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5 +#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6 +#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7 +#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8 +#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9 +#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba +#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb +#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc +#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0 + + +// addressBlock: athub_rpbdec +// base address: 0x33b0 +#define mmRPB_PASSPW_CONF 0x00cc +#define mmRPB_PASSPW_CONF_BASE_IDX 0 +#define mmRPB_BLOCKLEVEL_CONF 0x00cd +#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0 +#define mmRPB_TAG_CONF 0x00cf +#define mmRPB_TAG_CONF_BASE_IDX 0 +#define mmRPB_EFF_CNTL 0x00d1 +#define mmRPB_EFF_CNTL_BASE_IDX 0 +#define mmRPB_ARB_CNTL 0x00d2 +#define mmRPB_ARB_CNTL_BASE_IDX 0 +#define mmRPB_ARB_CNTL2 0x00d3 +#define mmRPB_ARB_CNTL2_BASE_IDX 0 +#define mmRPB_BIF_CNTL 0x00d4 +#define mmRPB_BIF_CNTL_BASE_IDX 0 +#define mmRPB_WR_SWITCH_CNTL 0x00d5 +#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0 +#define mmRPB_RD_SWITCH_CNTL 0x00d7 +#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0 +#define mmRPB_CID_QUEUE_WR 0x00d8 +#define mmRPB_CID_QUEUE_WR_BASE_IDX 0 +#define mmRPB_CID_QUEUE_RD 0x00d9 +#define mmRPB_CID_QUEUE_RD_BASE_IDX 0 +#define mmRPB_CID_QUEUE_EX 0x00dc +#define mmRPB_CID_QUEUE_EX_BASE_IDX 0 +#define mmRPB_CID_QUEUE_EX_DATA 0x00dd +#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0 +#define mmRPB_SWITCH_CNTL2 0x00de +#define mmRPB_SWITCH_CNTL2_BASE_IDX 0 +#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df +#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0 +#define mmRPB_VC_SWITCH_RDWR 0x00e0 +#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_LO 0x00e1 +#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_HI 0x00e2 +#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0 +#define mmRPB_PERFCOUNTER0_CFG 0x00e3 +#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER1_CFG 0x00e4 +#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER2_CFG 0x00e5 +#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER3_CFG 0x00e6 +#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7 +#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmRPB_RD_QUEUE_CNTL 0x00e9 +#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0 +#define mmRPB_RD_QUEUE_CNTL2 0x00ea +#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0 +#define mmRPB_WR_QUEUE_CNTL 0x00eb +#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0 +#define mmRPB_WR_QUEUE_CNTL2 0x00ec +#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0 +#define mmRPB_EA_QUEUE_WR 0x00ed +#define mmRPB_EA_QUEUE_WR_BASE_IDX 0 +#define mmRPB_ATS_CNTL 0x00ee +#define mmRPB_ATS_CNTL_BASE_IDX 0 +#define mmRPB_ATS_CNTL2 0x00ef +#define mmRPB_ATS_CNTL2_BASE_IDX 0 +#define mmRPB_SDPPORT_CNTL 0x00f0 +#define mmRPB_SDPPORT_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h new file mode 100644 index 000000000000..777b05c89708 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h @@ -0,0 +1,2045 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_SH_MASK_HEADER +#define _athub_1_0_SH_MASK_HEADER + + +// addressBlock: athub_atsdec +//ATC_ATS_CNTL +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 +#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 +#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L +#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L +#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L +#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L +//ATC_ATS_STATUS +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L +#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L +#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L +#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L +//ATC_ATS_FAULT_CNTL +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L +//ATC_ATS_FAULT_STATUS_INFO +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L +//ATC_ATS_FAULT_STATUS_ADDR +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL +//ATC_ATS_DEFAULT_PAGE_LOW +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL +//ATC_TRANS_FAULT_RSPCNTRL +#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa +#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb +#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc +#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd +#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe +#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf +#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a +#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b +#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c +#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d +#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e +#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f +#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L +//ATC_ATS_FAULT_STATUS_INFO2 +#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 +#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L +#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL +#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L +//ATHUB_MISC_CNTL +#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 +#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 +#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 +#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 +#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 +#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b +#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c +#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L +#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L +#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L +#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L +#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L +#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L +#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L +//ATC_VMID_PASID_MAPPING_UPDATE_STATUS +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L +//ATC_VMID0_PASID_MAPPING +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID1_PASID_MAPPING +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID2_PASID_MAPPING +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID3_PASID_MAPPING +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID4_PASID_MAPPING +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID5_PASID_MAPPING +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID6_PASID_MAPPING +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID7_PASID_MAPPING +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID8_PASID_MAPPING +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID9_PASID_MAPPING +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID10_PASID_MAPPING +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID11_PASID_MAPPING +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID12_PASID_MAPPING +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID13_PASID_MAPPING +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID14_PASID_MAPPING +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID15_PASID_MAPPING +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_ATS_VMID_STATUS +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf +#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 +#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 +#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 +#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 +#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 +#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 +#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 +#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 +#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 +#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 +#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a +#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b +#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c +#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d +#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e +#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L +#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L +#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L +#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L +#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L +#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L +#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L +#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L +#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L +#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L +#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L +#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L +#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L +#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L +#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L +#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L +#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L +//ATC_ATS_GFX_ATCL2_STATUS +#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 +#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L +//ATC_PERFCOUNTER0_CFG +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER1_CFG +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER2_CFG +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER3_CFG +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER_RSLT_CNTL +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//ATC_PERFCOUNTER_LO +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_PERFCOUNTER_HI +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//ATHUB_PCIE_ATS_CNTL +#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_PASID_CNTL +#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 +#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 +#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 +#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L +#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L +#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L +//ATHUB_PCIE_PAGE_REQ_CNTL +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L +//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//ATHUB_COMMAND +#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L +//ATHUB_PCIE_ATS_CNTL_VF_0 +#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_1 +#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_2 +#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_3 +#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_4 +#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_5 +#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_6 +#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_7 +#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_8 +#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_9 +#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_10 +#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_11 +#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_12 +#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_13 +#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_14 +#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_15 +#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//ATHUB_MEM_POWER_LS +#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATS_IH_CREDIT +#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//ATHUB_IH_CREDIT +#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//ATC_VMID16_PASID_MAPPING +#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID17_PASID_MAPPING +#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID18_PASID_MAPPING +#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID19_PASID_MAPPING +#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID20_PASID_MAPPING +#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID21_PASID_MAPPING +#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID22_PASID_MAPPING +#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID23_PASID_MAPPING +#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID24_PASID_MAPPING +#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID25_PASID_MAPPING +#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID26_PASID_MAPPING +#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID27_PASID_MAPPING +#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID28_PASID_MAPPING +#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID29_PASID_MAPPING +#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID30_PASID_MAPPING +#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID31_PASID_MAPPING +#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_ATS_MMHUB_ATCL2_STATUS +#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 +#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L +//ATHUB_SHARED_VIRT_RESET_REQ +#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//ATHUB_SHARED_ACTIVE_FCN_ID +#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//ATC_ATS_SDPPORT_CNTL +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe +#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L +//ATC_ATS_VMID_SNAPSHOT_GFX_STAT +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L +//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L + + +// addressBlock: athub_xpbdec +//XPB_RTR_SRC_APRTR0 +#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR1 +#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR2 +#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR3 +#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR4 +#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR5 +#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR6 +#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR7 +#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR8 +#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR9 +#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR0 +#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR1 +#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR2 +#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR3 +#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_DEST_MAP0 +#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP1 +#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP2 +#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP3 +#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP4 +#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP5 +#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP6 +#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP7 +#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP8 +#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP9 +#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP0 +#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP1 +#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP2 +#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP3 +#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L +//XPB_CLG_CFG0 +#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG1 +#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG2 +#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG3 +#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG4 +#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG5 +#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG6 +#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG7 +#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_EXTRA +#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb +#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc +#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf +#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 +#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a +#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b +#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L +#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L +#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L +#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L +#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L +#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L +//XPB_CLG_EXTRA_MSK +#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb +#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 +#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L +#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L +//XPB_LB_ADDR +#define XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define XPB_LB_ADDR__MASK0__SHIFT 0xa +#define XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL +#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L +#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L +#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L +//XPB_WCB_STS +#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL +#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L +#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L +//XPB_HST_CFG +#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 +#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L +//XPB_P2P_BAR_CFG +#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL +#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L +#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L +#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L +#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L +#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L +#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L +#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L +#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L +//XPB_P2P_BAR0 +#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR0__VALID__SHIFT 0xc +#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR0__VALID_MASK 0x00001000L +#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR1 +#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR1__VALID__SHIFT 0xc +#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR1__VALID_MASK 0x00001000L +#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR2 +#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR2__VALID__SHIFT 0xc +#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR2__VALID_MASK 0x00001000L +#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR3 +#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR3__VALID__SHIFT 0xc +#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR3__VALID_MASK 0x00001000L +#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR4 +#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR4__VALID__SHIFT 0xc +#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR4__VALID_MASK 0x00001000L +#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR5 +#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR5__VALID__SHIFT 0xc +#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR5__VALID_MASK 0x00001000L +#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR6 +#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR6__VALID__SHIFT 0xc +#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR6__VALID_MASK 0x00001000L +#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR7 +#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR7__VALID__SHIFT 0xc +#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR7__VALID_MASK 0x00001000L +#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR_SETUP +#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL +#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L +#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR_DELTA_ABOVE +#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL +#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L +//XPB_P2P_BAR_DELTA_BELOW +#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL +#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L +//XPB_PEER_SYS_BAR0 +#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR1 +#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR2 +#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR3 +#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR4 +#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR5 +#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR6 +#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR7 +#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR8 +#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR9 +#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR0 +#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR1 +#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR2 +#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR3 +#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL +//XPB_CLK_GAT +#define XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL +#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L +#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L +#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L +#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L +//XPB_INTF_CFG +#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL +#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L +#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L +#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L +#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L +#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L +#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L +#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L +#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L +#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L +#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L +//XPB_INTF_STS +#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL +#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L +#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L +#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L +#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L +#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L +#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L +//XPB_PIPE_STS +#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L +#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL +#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L +#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L +#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L +#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L +#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L +#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L +#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L +#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L +#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L +#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L +#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L +//XPB_SUB_CTRL +#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L +#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L +#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L +#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L +#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L +#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L +#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L +#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L +#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L +#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L +#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L +#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L +#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L +#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L +#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L +#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L +#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L +#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L +#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L +#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L +//XPB_MAP_INVERT_FLUSH_NUM_LSB +#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL +//XPB_PERF_KNOBS +#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL +#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L +#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L +//XPB_STICKY +#define XPB_STICKY__BITS__SHIFT 0x0 +#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL +//XPB_STICKY_W1C +#define XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL +//XPB_MISC_CFG +#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL +#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L +#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L +#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L +#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L +//XPB_INTF_CFG2 +#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL +//XPB_CLG_EXTRA_RD +#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb +#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc +#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf +#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 +#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a +#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b +#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L +#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L +#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L +#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L +#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L +#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L +//XPB_CLG_EXTRA_MSK_RD +#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb +#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 +#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L +#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L +//XPB_CLG_GFX_MATCH +#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 +#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 +#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc +#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 +#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 +#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 +#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a +#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b +#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL +#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L +#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L +#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L +#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L +#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L +#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L +#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L +//XPB_CLG_GFX_MATCH_MSK +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L +//XPB_CLG_MM_MATCH +#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 +#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 +#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc +#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 +#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 +#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 +#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a +#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b +#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL +#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L +#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L +#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L +#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L +#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L +#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L +#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L +//XPB_CLG_MM_MATCH_MSK +#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc +#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL +#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L +#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L +#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L +//XPB_CLG_GFX_UNITID_MAPPING0 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING1 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING2 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING3 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING4 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING5 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING6 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING7 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING0 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING1 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING2 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING3 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L + + +// addressBlock: athub_rpbdec +//RPB_PASSPW_CONF +#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 +#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 +#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 +#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 +#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 +#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 +#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 +#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 +#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L +#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L +#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L +#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L +#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L +#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L +#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L +#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L +//RPB_BLOCKLEVEL_CONF +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 +#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 +#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 +#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L +#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL +#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L +#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L +//RPB_TAG_CONF +#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 +#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 +#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 +#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL +#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L +#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L +//RPB_EFF_CNTL +#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL +#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L +//RPB_ARB_CNTL +#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 +#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 +#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 +#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 +#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 +#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL +#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L +#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L +#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L +//RPB_ARB_CNTL2 +#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 +#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 +#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 +#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL +#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L +//RPB_BIF_CNTL +#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 +#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 +#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 +#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 +#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 +#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 +#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b +#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c +#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d +#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e +#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL +#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L +#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L +#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L +#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L +#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L +#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L +#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L +#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L +//RPB_WR_SWITCH_CNTL +#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 +#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe +#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 +#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c +#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL +#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L +#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L +#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L +#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L +//RPB_RD_SWITCH_CNTL +#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 +#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe +#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 +#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c +#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL +#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L +#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L +#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L +#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L +//RPB_CID_QUEUE_WR +#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 +#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 +#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb +#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc +#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf +#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 +#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL +#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L +#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L +#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L +#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L +#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L +//RPB_CID_QUEUE_RD +#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 +#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 +#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb +#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe +#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL +#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L +#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L +#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L +//RPB_CID_QUEUE_EX +#define RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L +#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL +//RPB_CID_QUEUE_EX_DATA +#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL +#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L +//RPB_SWITCH_CNTL2 +#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 +#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 +#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe +#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 +#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL +#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L +#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L +#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L +//RPB_DEINTRLV_COMBINE_CNTL +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L +#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L +//RPB_VC_SWITCH_RDWR +#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 +#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 +#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa +#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L +#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL +#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L +//RPB_PERFCOUNTER_LO +#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//RPB_PERFCOUNTER_HI +#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//RPB_PERFCOUNTER0_CFG +#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER1_CFG +#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER2_CFG +#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER3_CFG +#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER_RSLT_CNTL +#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//RPB_RD_QUEUE_CNTL +#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 +#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 +#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 +#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 +#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 +#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L +#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L +#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L +#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L +#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L +//RPB_RD_QUEUE_CNTL2 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L +//RPB_WR_QUEUE_CNTL +#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 +#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 +#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 +#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 +#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 +#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L +#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L +#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L +#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L +#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L +//RPB_WR_QUEUE_CNTL2 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L +//RPB_EA_QUEUE_WR +#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 +#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 +#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 +#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb +#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL +#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L +#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L +#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L +//RPB_ATS_CNTL +#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 +#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 +#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 +#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 +#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf +#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 +#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 +#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 +#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L +#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L +#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL +#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L +#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L +#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L +#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L +#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L +//RPB_ATS_CNTL2 +#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 +#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 +#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc +#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf +#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 +#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL +#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L +#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L +#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L +#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L +//RPB_SDPPORT_CNTL +#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 +#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 +#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 +#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa +#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf +#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 +#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 +#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b +#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L +#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L +#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L +#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L +#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L +#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L +#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L +#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h new file mode 100644 index 000000000000..8a0007ce43dc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h @@ -0,0 +1,9868 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dce_12_0_DEFAULT_HEADER +#define _dce_12_0_DEFAULT_HEADER + + +// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR +#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR +#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon0_dispdec +#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon13_dispdec +#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_displaypllregs_dispdec +#define mmPPLL_VREG_CFG_DEFAULT 0x00000000 +#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100 +#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040 +#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002 +#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090 +#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004 +#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500 +#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004 +#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000 +#define mmPPLL_POSTDIV_DEFAULT 0x00000400 +#define mmPPLL_OBSERVE0_DEFAULT 0x00000000 +#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000 +#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000 +#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dccg_pll0_dispdec +#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon1_dispdec +#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mcif_wb0_dispdec +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 +#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff + + +// addressBlock: dce_dc_mcif_wb1_dispdec +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 +#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff + + +// addressBlock: dce_dc_mcif_wb2_dispdec +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 +#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 +#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 +#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 +#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff +#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff + + +// addressBlock: dce_dc_cwb0_dispdec +#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110 +#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff +#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff +#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000 +#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff +#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000 +#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_cwb1_dispdec +#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110 +#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff +#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff +#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000 +#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff +#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff +#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000 +#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon9_dispdec +#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dispdec +#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 +#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 +#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f +#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f +#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 +#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 +#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 +#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 +#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 +#define mmD1VGA_CONTROL_DEFAULT 0x00000000 +#define mmD2VGA_CONTROL_DEFAULT 0x00000000 +#define mmVGA_STATUS_DEFAULT 0x00000000 +#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 +#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 +#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 +#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 +#define mmCRTC8_IDX_DEFAULT 0x00000000 +#define mmCRTC8_DATA_DEFAULT 0x00000000 +#define mmGENFC_WT_DEFAULT 0x00000000 +#define mmGENS1_DEFAULT 0x00000000 +#define mmATTRDW_DEFAULT 0x00000000 +#define mmATTRX_DEFAULT 0x00000000 +#define mmATTRDR_DEFAULT 0x00000000 +#define mmGENMO_WT_DEFAULT 0x00000000 +#define mmGENS0_DEFAULT 0x00000000 +#define mmGENENB_DEFAULT 0x00000000 +#define mmSEQ8_IDX_DEFAULT 0x00000000 +#define mmSEQ8_DATA_DEFAULT 0x00000000 +#define mmDAC_MASK_DEFAULT 0x00000000 +#define mmDAC_R_INDEX_DEFAULT 0x00000000 +#define mmDAC_W_INDEX_DEFAULT 0x00000000 +#define mmDAC_DATA_DEFAULT 0x00000000 +#define mmGENFC_RD_DEFAULT 0x00000000 +#define mmGENMO_RD_DEFAULT 0x00000000 +#define mmGRPH8_IDX_DEFAULT 0x00000000 +#define mmGRPH8_DATA_DEFAULT 0x00000000 +#define mmCRTC8_IDX_1_DEFAULT 0x00000000 +#define mmCRTC8_DATA_1_DEFAULT 0x00000000 +#define mmGENFC_WT_1_DEFAULT 0x00000000 +#define mmGENS1_1_DEFAULT 0x00000000 +#define mmD3VGA_CONTROL_DEFAULT 0x00000000 +#define mmD4VGA_CONTROL_DEFAULT 0x00000000 +#define mmD5VGA_CONTROL_DEFAULT 0x00000000 +#define mmD6VGA_CONTROL_DEFAULT 0x00000000 +#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000 +#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmREFCLK_CNTL_DEFAULT 0x00000000 +#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 +#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 +#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 +#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 +#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 +#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 +#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 +#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 +#define mmDCE_VERSION_DEFAULT 0x00000000 +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 +#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 +#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 +#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064 +#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 +#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 +#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 +#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 +#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 +#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmSMU_CONTROL_DEFAULT 0x00000000 +#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 +#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 +#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001 +#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800 +#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd +#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000 +#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464 +#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f +#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000 +#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO0_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO0_MODULO_DEFAULT 0x00000000 +#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO1_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO1_MODULO_DEFAULT 0x00000000 +#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO2_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO2_MODULO_DEFAULT 0x00000000 +#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO3_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO3_MODULO_DEFAULT 0x00000000 +#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO4_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO4_MODULO_DEFAULT 0x00000000 +#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO5_PHASE_DEFAULT 0x00000000 +#define mmDP_DTO5_MODULO_DEFAULT 0x00000000 +#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000 +#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000 +#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100 +#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200 +#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300 +#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400 +#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500 +#define mmDVOACLKD_CNTL_DEFAULT 0x00070000 +#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000 +#define mmDVOACLKC_CNTL_DEFAULT 0x00030000 +#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030 +#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001 +#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001 +#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff +#define mmFBC_CNTL_DEFAULT 0x00000500 +#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000 +#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000 +#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f +#define mmFBC_COMP_MODE_DEFAULT 0x00000000 +#define mmFBC_IND_LUT0_DEFAULT 0x00000000 +#define mmFBC_IND_LUT1_DEFAULT 0x00000000 +#define mmFBC_IND_LUT2_DEFAULT 0x00000000 +#define mmFBC_IND_LUT3_DEFAULT 0x00000000 +#define mmFBC_IND_LUT4_DEFAULT 0x00000000 +#define mmFBC_IND_LUT5_DEFAULT 0x00000000 +#define mmFBC_IND_LUT6_DEFAULT 0x00000000 +#define mmFBC_IND_LUT7_DEFAULT 0x00000000 +#define mmFBC_IND_LUT8_DEFAULT 0x00000000 +#define mmFBC_IND_LUT9_DEFAULT 0x00000000 +#define mmFBC_IND_LUT10_DEFAULT 0x00000000 +#define mmFBC_IND_LUT11_DEFAULT 0x00000000 +#define mmFBC_IND_LUT12_DEFAULT 0x00000000 +#define mmFBC_IND_LUT13_DEFAULT 0x00000000 +#define mmFBC_IND_LUT14_DEFAULT 0x00000000 +#define mmFBC_IND_LUT15_DEFAULT 0x00000000 +#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000 +#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000 +#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000 +#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000 +#define mmFBC_MISC_DEFAULT 0x0c306008 +#define mmFBC_STATUS_DEFAULT 0x00000000 +#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000 +#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000 +#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001 +#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000 +#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000 +#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001 +#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000 +#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000 +#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001 +#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000 +#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000 +#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001 +#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000 +#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000 +#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001 +#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000 +#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000 +#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001 +#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000 +#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000 +#define mmDSI_PG_CONFIG_DEFAULT 0x00000001 +#define mmDSI_PG_ENABLE_DEFAULT 0x00000000 +#define mmDSI_PG_STATUS_DEFAULT 0x00000000 +#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001 +#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000 +#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000 +#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000 +#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001 +#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000 +#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000 +#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000 +#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000 +#define mmDMIFV_STATUS_DEFAULT 0x00000000 +#define mmDMIF_CONTROL_DEFAULT 0x00000c04 +#define mmDMIF_STATUS_DEFAULT 0x0ff00000 +#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710 +#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmDMIF_P_VMID_DEFAULT 0x00000000 +#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000 +#define mmDMIF_STATUS2_DEFAULT 0x00000000 +#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmPIPE1_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmPIPE2_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmPIPE3_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmPIPE4_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmPIPE5_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmLOW_POWER_TILING_CONTROL_DEFAULT 0x00001000 +#define mmMCIF_CONTROL_DEFAULT 0x00000000 +#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080 +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000 +#define mmSMU_WM_CONTROL_DEFAULT 0x00000000 +#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00 +#define mmRBBMIF_STATUS_DEFAULT 0x80000000 +#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 +#define mmDCI_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCI_MEM_PWR_STATUS2_DEFAULT 0x00000000 +#define mmDCI_CLK_CNTL_DEFAULT 0x00000000 +#define mmDCI_CLK_CNTL2_DEFAULT 0x00020020 +#define mmDCI_MEM_PWR_CNTL_DEFAULT 0x00000000 +#define mmDCI_MEM_PWR_CNTL2_DEFAULT 0x00000000 +#define mmDCI_MEM_PWR_CNTL3_DEFAULT 0x00000000 +#define mmPIPE0_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmPIPE1_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmPIPE2_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmPIPE3_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmPIPE4_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmPIPE5_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000 +#define mmDCI_SOFT_RESET_DEFAULT 0x00000000 +#define mmDMIF_URG_OVERRIDE_DEFAULT 0x00000000 +#define mmPIPE6_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE7_ARBITRATION_CONTROL3_DEFAULT 0x00000000 +#define mmPIPE6_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmPIPE7_MAX_REQUESTS_DEFAULT 0x000003ff +#define mmDVMM_REG_RD_STATUS_DEFAULT 0x00000000 +#define mmDVMM_REG_RD_DATA_DEFAULT 0x00000000 +#define mmDVMM_PTE_REQ_DEFAULT 0x000120ff +#define mmDVMM_CNTL_DEFAULT 0x00000000 +#define mmDVMM_FAULT_STATUS_DEFAULT 0x00000000 +#define mmDVMM_FAULT_ADDR_DEFAULT 0x00000000 +#define mmFMON_CTRL_DEFAULT 0x0000f040 +#define mmDVMM_PTE_PGMEM_CONTROL_DEFAULT 0x00000000 +#define mmDVMM_PTE_PGMEM_STATE_DEFAULT 0x00000000 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 +#define mmDCI_MEM_PWR_CNTL4_DEFAULT 0x0000003f +#define mmMCIF_WB_MISC_CTRL_DEFAULT 0x00010001 +#define mmDCI_MEM_PWR_STATUS3_DEFAULT 0x00000000 +#define mmDMIF_CURSOR_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_CURSOR_MEM_CONTROL_DEFAULT 0x00000000 +#define mmDCHUB_FB_LOCATION_DEFAULT 0x00000000 +#define mmDCHUB_FB_OFFSET_DEFAULT 0x00000000 +#define mmDCHUB_AGP_BASE_DEFAULT 0x00000000 +#define mmDCHUB_AGP_BOT_DEFAULT 0x00000000 +#define mmDCHUB_AGP_TOP_DEFAULT 0x00000000 +#define mmDCHUB_DRAM_APER_BASE_DEFAULT 0x00000000 +#define mmDCHUB_DRAM_APER_DEF_DEFAULT 0x00000000 +#define mmDCHUB_DRAM_APER_TOP_DEFAULT 0x00000000 +#define mmDCHUB_CONTROL_STATUS_DEFAULT 0x00c00000 +#define mmWB_ENABLE_DEFAULT 0x00000000 +#define mmWB_EC_CONFIG_DEFAULT 0x55000000 +#define mmCNV_MODE_DEFAULT 0x00000000 +#define mmCNV_WINDOW_START_DEFAULT 0x00000000 +#define mmCNV_WINDOW_SIZE_DEFAULT 0x00100010 +#define mmCNV_UPDATE_DEFAULT 0x00000000 +#define mmCNV_SOURCE_SIZE_DEFAULT 0x00100010 +#define mmCNV_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCNV_CSC_C11_C12_DEFAULT 0x00000000 +#define mmCNV_CSC_C13_C14_DEFAULT 0x00000000 +#define mmCNV_CSC_C21_C22_DEFAULT 0x00000000 +#define mmCNV_CSC_C23_C24_DEFAULT 0x00000000 +#define mmCNV_CSC_C31_C32_DEFAULT 0x00000000 +#define mmCNV_CSC_C33_C34_DEFAULT 0x00000000 +#define mmCNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 +#define mmCNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 +#define mmCNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 +#define mmCNV_CSC_CLAMP_R_DEFAULT 0x00000fff +#define mmCNV_CSC_CLAMP_G_DEFAULT 0x00000fff +#define mmCNV_CSC_CLAMP_B_DEFAULT 0x00000fff +#define mmCNV_TEST_CNTL_DEFAULT 0x00000000 +#define mmCNV_TEST_CRC_RED_DEFAULT 0x0000fff0 +#define mmCNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 +#define mmCNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 +#define mmCNV_INPUT_SELECT_DEFAULT 0x00000000 +#define mmWB_SOFT_RESET_DEFAULT 0x00000000 +#define mmWB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 +#define mmWB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 +#define mmWBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmWBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmWBSCL_MODE_DEFAULT 0x00000000 +#define mmWBSCL_TAP_CONTROL_DEFAULT 0x00001111 +#define mmWBSCL_DEST_SIZE_DEFAULT 0x00010001 +#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 +#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 +#define mmWBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 +#define mmWBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 +#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 +#define mmWBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 +#define mmWBSCL_ROUND_OFFSET_DEFAULT 0x00800010 +#define mmWBSCL_CLAMP_DEFAULT 0x01fe01fe +#define mmWBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 +#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 +#define mmWBSCL_TEST_CNTL_DEFAULT 0x00000000 +#define mmWBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 +#define mmWBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff +#define mmWBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 +#define mmWBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 +#define mmWB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 +#define mmWBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 +#define mmDMCU_CTRL_DEFAULT 0xffff0101 +#define mmDMCU_STATUS_DEFAULT 0x00000001 +#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000 +#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000 +#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000 +#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004 +#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000 +#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000 +#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000 +#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000 +#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000 +#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000 +#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000 +#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000 +#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000 +#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000 +#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000 +#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000 +#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000 +#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000 +#define mmDMCU_INT_CNT_DEFAULT 0x00000000 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000 +#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102 +#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000 +#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000 +#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000 +#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000 +#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000 +#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000 +#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000 +#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000 +#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000 +#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 +#define mmBL1_PWM_USER_LEVEL_DEFAULT 0x00000000 +#define mmBL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 +#define mmBL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 +#define mmBL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 +#define mmBL1_PWM_ABM_CNTL_DEFAULT 0x00000000 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmBL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000 +#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000 +#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 +#define mmDC_ABM1_CNTL_DEFAULT 0x00000000 +#define mmDC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 +#define mmDC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 +#define mmDC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 +#define mmDC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_OVR_SCAN_BIN_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmDC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 +#define mmDC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_DEFAULT 0x00000000 +#define mmDC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 +#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000 +#define mmAZALIA_AUDIO_DTO_DEFAULT 0x001b0018 +#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000 +#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a +#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a +#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000 +#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000 +#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080 +#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000 +#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000 +#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 +#define mmDAC_ENABLE_DEFAULT 0x00000004 +#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000 +#define mmDAC_CRC_EN_DEFAULT 0x00000000 +#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff +#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f +#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff +#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f +#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000 +#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000 +#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000 +#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b +#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519 +#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000 +#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000 +#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000 +#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6 +#define mmDAC_POWERDOWN_DEFAULT 0x01010100 +#define mmDAC_CONTROL_DEFAULT 0x00000000 +#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000 +#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000 +#define mmDAC_PWR_CNTL_DEFAULT 0x00000000 +#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000 +#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_CONTROL_DEFAULT 0x00000000 +#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001 +#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000 +#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000 +#define mmDC_I2C_DATA_DEFAULT 0x00000000 +#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000 +#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002 +#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000 +#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4 +#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000 +#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000 +#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000 +#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002 +#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000 +#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000 +#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000 +#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000 +#define mmDCO_SCRATCH0_DEFAULT 0x00000000 +#define mmDCO_SCRATCH1_DEFAULT 0x00000000 +#define mmDCO_SCRATCH2_DEFAULT 0x00000000 +#define mmDCO_SCRATCH3_DEFAULT 0x00000000 +#define mmDCO_SCRATCH4_DEFAULT 0x00000000 +#define mmDCO_SCRATCH5_DEFAULT 0x00000000 +#define mmDCO_SCRATCH6_DEFAULT 0x00000000 +#define mmDCO_SCRATCH7_DEFAULT 0x00000000 +#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000 +#define mmDCO_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCO_MEM_PWR_CTRL_DEFAULT 0x6db6d800 +#define mmDCO_MEM_PWR_CTRL2_DEFAULT 0x001b0000 +#define mmDCO_CLK_CNTL_DEFAULT 0x00000000 +#define mmDCO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000 +#define mmDIG_SOFT_RESET_2_DEFAULT 0x00000000 +#define mmDCO_STEREOSYNC_SEL_DEFAULT 0x00000000 +#define mmDCO_SOFT_RESET_DEFAULT 0x00000000 +#define mmDIG_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCO_MEM_PWR_STATUS1_DEFAULT 0x00000000 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000 +#define mmDCO_CLK_CNTL2_DEFAULT 0x00000000 +#define mmDCO_CLK_CNTL3_DEFAULT 0x00000000 +#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000 +#define mmDCO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000 +#define mmDCO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000 +#define mmDCO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000 +#define mmFMT_MEMORY0_CONTROL_DEFAULT 0x00000030 +#define mmFMT_MEMORY1_CONTROL_DEFAULT 0x00000031 +#define mmFMT_MEMORY2_CONTROL_DEFAULT 0x00000032 +#define mmFMT_MEMORY3_CONTROL_DEFAULT 0x00000033 +#define mmFMT_MEMORY4_CONTROL_DEFAULT 0x00000034 +#define mmFMT_MEMORY5_CONTROL_DEFAULT 0x00000035 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000 +#define mmDC_GENERICA_DEFAULT 0x00000000 +#define mmDC_GENERICB_DEFAULT 0x00000000 +#define mmDC_PAD_EXTERN_SIG_DEFAULT 0x00000000 +#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000 +#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101 +#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333 +#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000 +#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000 +#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000 +#define mmBL_PWM_CNTL_DEFAULT 0x00000000 +#define mmBL_PWM_CNTL2_DEFAULT 0x00000000 +#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001 +#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000 +#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000 +#define mmDCIO_GSL0_CNTL_DEFAULT 0x00000000 +#define mmDCIO_GSL1_CNTL_DEFAULT 0x00000000 +#define mmDCIO_GSL2_CNTL_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000 +#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000 +#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000 +#define mmDCO_DCFE_EXT_VSYNC_CNTL_DEFAULT 0x00000000 +#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4 +#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000 +#define mmAUXP_IMPCAL_DEFAULT 0x0a000000 +#define mmAUXN_IMPCAL_DEFAULT 0x04000000 +#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000 +#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000 +#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000 +#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000 +#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000 +#define mmUNIPHYLPA_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYLPB_LINK_CNTL_DEFAULT 0x01100100 +#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 +#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000 +#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000 +#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000 +#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444 +#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000 +#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000 +#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000 +#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040 +#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000 +#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10 +#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000 +#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440 +#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000 +#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202 +#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040 +#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000 +#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47ac470f +#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147 +#define mmPHY_AUX_CNTL_DEFAULT 0x00010001 +#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c +#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060 +#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000 +#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000 +#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000 +#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202 +#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000 +#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000 +#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000 +#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000 +#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f +#define mmBPHYC_DAC_MACRO_CNTL_DEFAULT 0x00202002 +#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_DEFAULT 0x00700255 +#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDISP_DSI_DUAL_CTRL_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDPRX_AUX_REFERENCE_PULSE_DIV_DEFAULT 0x0a640064 +#define mmDPRX_AUX_CONTROL_DEFAULT 0x01012c00 +#define mmDPRX_AUX_HPD_CONTROL1_DEFAULT 0x00001407 +#define mmDPRX_AUX_HPD_CONTROL2_DEFAULT 0x00000000 +#define mmDPRX_AUX_RX_STATUS_DEFAULT 0x00000000 +#define mmDPRX_AUX_RX_ERROR_MASK_DEFAULT 0x00000000 +#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDPRX_AUX_DPHY_TX_CONTROL_DEFAULT 0x00001002 +#define mmDPRX_AUX_DPHY_RX_CONTROL0_DEFAULT 0x203d1210 +#define mmDPRX_AUX_DPHY_RX_CONTROL1_DEFAULT 0x0a00fa00 +#define mmDPRX_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDPRX_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDPRX_AUX_DMCU_HW_INT_STATUS_DEFAULT 0x00003f00 +#define mmDPRX_AUX_DMCU_HW_INT_ACK_DEFAULT 0x00000000 +#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_DEFAULT 0x00000000 +#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_DEFAULT 0x00000001 +#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_DEFAULT 0x00000000 +#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_DEFAULT 0x00000000 +#define mmDPRX_AUX_AUX_BUF_INDEX_DEFAULT 0x00000000 +#define mmDPRX_AUX_AUX_BUF_DATA_DEFAULT 0x00000000 +#define mmDPRX_AUX_EDID_INDEX_DEFAULT 0x00000000 +#define mmDPRX_AUX_EDID_DATA_DEFAULT 0x00000000 +#define mmDPRX_AUX_DPCD_INDEX1_DEFAULT 0x00000000 +#define mmDPRX_AUX_DPCD_DATA1_DEFAULT 0x00000000 +#define mmDPRX_AUX_DPCD_INDEX2_DEFAULT 0x00000000 +#define mmDPRX_AUX_DPCD_DATA2_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG_INDEX1_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG_DATA1_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG_INDEX2_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG_DATA2_DEFAULT 0x00000000 +#define mmDPRX_AUX_KSV_INDEX1_DEFAULT 0x00000000 +#define mmDPRX_AUX_KSV_DATA1_DEFAULT 0x00000000 +#define mmDPRX_AUX_KSV_INDEX2_DEFAULT 0x00000000 +#define mmDPRX_AUX_KSV_DATA2_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_DEFAULT 0x00000032 +#define mmDPRX_AUX_MSG_BUF_CONTROL1_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG_BUF_CONTROL2_DEFAULT 0x00000000 +#define mmDPRX_AUX_SCRATCH1_DEFAULT 0x00000000 +#define mmDPRX_AUX_SCRATCH2_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG1_PENDING_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG2_PENDING_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG3_PENDING_DEFAULT 0x00000000 +#define mmDPRX_AUX_MSG4_PENDING_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_DEFAULT 0x00000003 +#define mmDPRX_DPHY_DPCD_MSTM_CTRL_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_DEFAULT 0x20000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_DEFAULT 0x20000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_DEFAULT 0x20000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_DEFAULT 0x20000000 +#define mmDPRX_DPHY_READY_DEFAULT 0x00000000 +#define mmDPRX_DPHY_COMMA_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_DEFAULT 0x00000000 +#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_DEFAULT 0x00000000 +#define mmDPRX_DPHY_SR_ERROR_COUNT_A_DEFAULT 0x00000000 +#define mmDPRX_DPHY_BS_ERROR_COUNT_A_DEFAULT 0x00000000 +#define mmDPRX_DPHY_BS_ERROR_COUNT_B_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LANESETUP0_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LANESETUP1_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LFSRADV_DEFAULT 0x00000039 +#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_DEFAULT 0x00000000 +#define mmDPRX_DPHY_SET_ENABLE_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ECF_LSB_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ECF_MSB_DEFAULT 0x00000000 +#define mmDPRX_DPHY_ENHANCED_FRAME_EN_DEFAULT 0x00000001 +#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_DEFAULT 0x000a6800 +#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_DEFAULT 0xbcbcbcbc +#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_DEFAULT 0x800071c5 +#define mmDPRX_DPHY_BYPASS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_INT_RESET_DEFAULT 0x00000000 +#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_DEFAULT 0x00000000 +#define mmDPRX_DPHY_SPARE_DEFAULT 0x00000000 +#define mmDCRX_GATE_DISABLE_CNTL_DEFAULT 0x00001f0f +#define mmDCRX_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCRX_LIGHT_SLEEP_CNTL_DEFAULT 0x00000101 +#define mmDCRX_DISPCLK_GATE_CNTL_DEFAULT 0x00000200 +#define mmDCRX_CLK_CNTL_DEFAULT 0x00000000 +#define mmDCRX_TEST_CLK_CNTL_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_DEFAULT 0x00000000 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_DEFAULT 0x00000000 +#define mmI2S0_CNTL_DEFAULT 0x00010000 +#define mmSPDIF0_CNTL_DEFAULT 0x00000000 +#define mmI2S1_CNTL_DEFAULT 0x00010000 +#define mmSPDIF1_CNTL_DEFAULT 0x00000000 +#define mmI2S0_STATUS_DEFAULT 0x00000000 +#define mmI2S1_STATUS_DEFAULT 0x00000000 +#define mmI2S0_CRC_TEST_CNTL_DEFAULT 0x00000100 +#define mmI2S0_CRC_TEST_DATA_01_DEFAULT 0x00000000 +#define mmI2S0_CRC_TEST_DATA_23_DEFAULT 0x00000000 +#define mmI2S1_CRC_TEST_CNTL_DEFAULT 0x00000100 +#define mmI2S1_CRC_TEST_DATA_0_DEFAULT 0x00000000 +#define mmSPDIF0_CRC_TEST_CNTL_DEFAULT 0x00000100 +#define mmSPDIF0_CRC_TEST_DATA_0_DEFAULT 0x00000000 +#define mmSPDIF1_CRC_TEST_CNTL_DEFAULT 0x00000100 +#define mmSPDIF1_CRC_TEST_DATA_DEFAULT 0x00000000 +#define mmCRC_I2S_CONT_REPEAT_NUM_DEFAULT 0x00000000 +#define mmCRC_SPDIF_CONT_REPEAT_NUM_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream0_dispdec +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream1_dispdec +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream2_dispdec +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream3_dispdec +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream4_dispdec +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream5_dispdec +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream6_dispdec +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream7_dispdec +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint0_dispdec +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint1_dispdec +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint2_dispdec +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint3_dispdec +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint4_dispdec +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint5_dispdec +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint6_dispdec +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0endpoint7_dispdec +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream8_dispdec +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream9_dispdec +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream10_dispdec +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream11_dispdec +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream12_dispdec +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream13_dispdec +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream14_dispdec +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0stream15_dispdec +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint0_dispdec +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint1_dispdec +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint2_dispdec +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint3_dispdec +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint4_dispdec +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint5_dispdec +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint6_dispdec +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azf0inputendpoint7_dispdec +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcp0_dispdec +#define mmDCP0_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmDCP0_GRPH_CONTROL_DEFAULT 0x20002040 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_PITCH_DEFAULT 0x00000000 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 +#define mmDCP0_GRPH_X_START_DEFAULT 0x00000000 +#define mmDCP0_GRPH_Y_START_DEFAULT 0x00000000 +#define mmDCP0_GRPH_X_END_DEFAULT 0x00000000 +#define mmDCP0_GRPH_Y_END_DEFAULT 0x00000000 +#define mmDCP0_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmDCP0_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 +#define mmDCP0_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_GRPH_DFQ_STATUS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff +#define mmDCP0_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 +#define mmDCP0_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 +#define mmDCP0_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 +#define mmDCP0_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 +#define mmDCP0_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_INPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP0_INPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP0_INPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP0_INPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP0_INPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP0_INPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP0_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP0_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP0_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP0_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP0_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP0_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP0_DENORM_CONTROL_DEFAULT 0x00000003 +#define mmDCP0_OUT_ROUND_CONTROL_DEFAULT 0x0000000a +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff +#define mmDCP0_KEY_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_KEY_RANGE_ALPHA_DEFAULT 0x00000000 +#define mmDCP0_KEY_RANGE_RED_DEFAULT 0x00000000 +#define mmDCP0_KEY_RANGE_GREEN_DEFAULT 0x00000000 +#define mmDCP0_KEY_RANGE_BLUE_DEFAULT 0x00000000 +#define mmDCP0_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmDCP0_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmDCP0_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmDCP0_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmDCP0_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmDCP0_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 +#define mmDCP0_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmDCP0_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmDCP0_CUR_CONTROL_DEFAULT 0x00000810 +#define mmDCP0_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP0_CUR_SIZE_DEFAULT 0x00000000 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP0_CUR_POSITION_DEFAULT 0x00000000 +#define mmDCP0_CUR_HOT_SPOT_DEFAULT 0x00000000 +#define mmDCP0_CUR_COLOR1_DEFAULT 0x00000000 +#define mmDCP0_CUR_COLOR2_DEFAULT 0x00000000 +#define mmDCP0_CUR_UPDATE_DEFAULT 0x00000000 +#define mmDCP0_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 +#define mmDCP0_CUR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_RW_MODE_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP0_DC_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff +#define mmDCP0_DCP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_DCP_CRC_MASK_DEFAULT 0x00000000 +#define mmDCP0_DCP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmDCP0_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmDCP0_DCP_CRC_LAST_DEFAULT 0x00000000 +#define mmDCP0_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmDCP0_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCP0_DCP_GSL_CONTROL_DEFAULT 0x60000020 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 +#define mmDCP0_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 +#define mmDCP0_HW_ROTATION_DEFAULT 0x00000000 +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 +#define mmDCP0_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP0_ALPHA_CONTROL_DEFAULT 0x00000002 +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 +#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 +#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 +#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 +#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_lb0_dispdec +#define mmLB0_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLB0_LB_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLB0_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLB0_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLB0_LB_VLINE_START_END_DEFAULT 0x00000000 +#define mmLB0_LB_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLB0_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmLB0_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLB0_LB_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLB0_LB_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLB0_LB_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLB0_LB_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLB0_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLB0_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLB0_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLB0_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLB0_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLB0_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLB0_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLB0_LB_BUFFER_STATUS_DEFAULT 0x00000002 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 +#define mmLB0_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 +#define mmLB0_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dcfe0_dispdec +#define mmDCFE0_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFE0_DCFE_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFE0_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFE0_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFE0_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFE0_DCFE_MISC_DEFAULT 0x00000001 +#define mmDCFE0_DCFE_FLUSH_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon3_dispdec +#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmif_pg0_dispdec +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIF_PG0_DPG_DVMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_scl0_dispdec +#define mmSCL0_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCL0_SCL_MODE_DEFAULT 0x00000000 +#define mmSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL0_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCL0_SCL_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCL0_SCL_UPDATE_DEFAULT 0x00000000 +#define mmSCL0_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmSCL0_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCL0_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCL0_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCL0_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCL0_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCL0_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCL0_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blnd0_dispdec +#define mmBLND0_BLND_CONTROL_DEFAULT 0xff0220ff +#define mmBLND0_BLND_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLND0_BLND_CONTROL2_DEFAULT 0x00000010 +#define mmBLND0_BLND_UPDATE_DEFAULT 0x00000000 +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLND0_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLND0_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtc0_dispdec +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTC0_CRTC_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VBI_END_DEFAULT 0x00000003 +#define mmCRTC0_CRTC_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CONTROL_DEFAULT 0x80400110 +#define mmCRTC0_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTC0_CRTC_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_GSL_CONTROL_DEFAULT 0x00020000 +#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC0_CRTC_DRR_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_fmt0_dispdec +#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT0_FMT_CRC_CNTL_DEFAULT 0x01000040 +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT0_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcp1_dispdec +#define mmDCP1_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmDCP1_GRPH_CONTROL_DEFAULT 0x20002040 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_PITCH_DEFAULT 0x00000000 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 +#define mmDCP1_GRPH_X_START_DEFAULT 0x00000000 +#define mmDCP1_GRPH_Y_START_DEFAULT 0x00000000 +#define mmDCP1_GRPH_X_END_DEFAULT 0x00000000 +#define mmDCP1_GRPH_Y_END_DEFAULT 0x00000000 +#define mmDCP1_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmDCP1_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 +#define mmDCP1_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_GRPH_DFQ_STATUS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff +#define mmDCP1_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 +#define mmDCP1_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 +#define mmDCP1_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 +#define mmDCP1_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 +#define mmDCP1_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_INPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP1_INPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP1_INPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP1_INPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP1_INPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP1_INPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP1_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP1_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP1_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP1_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP1_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP1_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP1_DENORM_CONTROL_DEFAULT 0x00000003 +#define mmDCP1_OUT_ROUND_CONTROL_DEFAULT 0x0000000a +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff +#define mmDCP1_KEY_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_KEY_RANGE_ALPHA_DEFAULT 0x00000000 +#define mmDCP1_KEY_RANGE_RED_DEFAULT 0x00000000 +#define mmDCP1_KEY_RANGE_GREEN_DEFAULT 0x00000000 +#define mmDCP1_KEY_RANGE_BLUE_DEFAULT 0x00000000 +#define mmDCP1_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmDCP1_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmDCP1_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmDCP1_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmDCP1_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmDCP1_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 +#define mmDCP1_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmDCP1_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmDCP1_CUR_CONTROL_DEFAULT 0x00000810 +#define mmDCP1_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP1_CUR_SIZE_DEFAULT 0x00000000 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP1_CUR_POSITION_DEFAULT 0x00000000 +#define mmDCP1_CUR_HOT_SPOT_DEFAULT 0x00000000 +#define mmDCP1_CUR_COLOR1_DEFAULT 0x00000000 +#define mmDCP1_CUR_COLOR2_DEFAULT 0x00000000 +#define mmDCP1_CUR_UPDATE_DEFAULT 0x00000000 +#define mmDCP1_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 +#define mmDCP1_CUR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_RW_MODE_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP1_DC_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff +#define mmDCP1_DCP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_DCP_CRC_MASK_DEFAULT 0x00000000 +#define mmDCP1_DCP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmDCP1_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmDCP1_DCP_CRC_LAST_DEFAULT 0x00000000 +#define mmDCP1_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmDCP1_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCP1_DCP_GSL_CONTROL_DEFAULT 0x60000020 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 +#define mmDCP1_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 +#define mmDCP1_HW_ROTATION_DEFAULT 0x00000000 +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 +#define mmDCP1_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP1_ALPHA_CONTROL_DEFAULT 0x00000002 +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 +#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 +#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 +#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 +#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_lb1_dispdec +#define mmLB1_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLB1_LB_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLB1_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLB1_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLB1_LB_VLINE_START_END_DEFAULT 0x00000000 +#define mmLB1_LB_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLB1_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmLB1_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLB1_LB_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLB1_LB_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLB1_LB_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLB1_LB_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLB1_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLB1_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLB1_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLB1_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLB1_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLB1_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLB1_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLB1_LB_BUFFER_STATUS_DEFAULT 0x00000002 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 +#define mmLB1_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 +#define mmLB1_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dcfe1_dispdec +#define mmDCFE1_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFE1_DCFE_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFE1_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFE1_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFE1_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFE1_DCFE_MISC_DEFAULT 0x00000001 +#define mmDCFE1_DCFE_FLUSH_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon4_dispdec +#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmif_pg1_dispdec +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIF_PG1_DPG_DVMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_scl1_dispdec +#define mmSCL1_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCL1_SCL_MODE_DEFAULT 0x00000000 +#define mmSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL1_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCL1_SCL_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCL1_SCL_UPDATE_DEFAULT 0x00000000 +#define mmSCL1_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmSCL1_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCL1_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCL1_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCL1_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCL1_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCL1_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCL1_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blnd1_dispdec +#define mmBLND1_BLND_CONTROL_DEFAULT 0xff0220ff +#define mmBLND1_BLND_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLND1_BLND_CONTROL2_DEFAULT 0x00000010 +#define mmBLND1_BLND_UPDATE_DEFAULT 0x00000000 +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLND1_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLND1_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtc1_dispdec +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTC1_CRTC_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VBI_END_DEFAULT 0x00000003 +#define mmCRTC1_CRTC_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CONTROL_DEFAULT 0x80400110 +#define mmCRTC1_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTC1_CRTC_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_GSL_CONTROL_DEFAULT 0x00020000 +#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC1_CRTC_DRR_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_fmt1_dispdec +#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT1_FMT_CRC_CNTL_DEFAULT 0x01000040 +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT1_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcp2_dispdec +#define mmDCP2_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmDCP2_GRPH_CONTROL_DEFAULT 0x20002040 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_PITCH_DEFAULT 0x00000000 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 +#define mmDCP2_GRPH_X_START_DEFAULT 0x00000000 +#define mmDCP2_GRPH_Y_START_DEFAULT 0x00000000 +#define mmDCP2_GRPH_X_END_DEFAULT 0x00000000 +#define mmDCP2_GRPH_Y_END_DEFAULT 0x00000000 +#define mmDCP2_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmDCP2_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 +#define mmDCP2_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_GRPH_DFQ_STATUS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff +#define mmDCP2_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 +#define mmDCP2_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 +#define mmDCP2_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 +#define mmDCP2_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 +#define mmDCP2_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_INPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP2_INPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP2_INPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP2_INPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP2_INPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP2_INPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP2_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP2_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP2_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP2_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP2_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP2_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP2_DENORM_CONTROL_DEFAULT 0x00000003 +#define mmDCP2_OUT_ROUND_CONTROL_DEFAULT 0x0000000a +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff +#define mmDCP2_KEY_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_KEY_RANGE_ALPHA_DEFAULT 0x00000000 +#define mmDCP2_KEY_RANGE_RED_DEFAULT 0x00000000 +#define mmDCP2_KEY_RANGE_GREEN_DEFAULT 0x00000000 +#define mmDCP2_KEY_RANGE_BLUE_DEFAULT 0x00000000 +#define mmDCP2_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmDCP2_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmDCP2_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmDCP2_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmDCP2_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmDCP2_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 +#define mmDCP2_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmDCP2_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmDCP2_CUR_CONTROL_DEFAULT 0x00000810 +#define mmDCP2_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP2_CUR_SIZE_DEFAULT 0x00000000 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP2_CUR_POSITION_DEFAULT 0x00000000 +#define mmDCP2_CUR_HOT_SPOT_DEFAULT 0x00000000 +#define mmDCP2_CUR_COLOR1_DEFAULT 0x00000000 +#define mmDCP2_CUR_COLOR2_DEFAULT 0x00000000 +#define mmDCP2_CUR_UPDATE_DEFAULT 0x00000000 +#define mmDCP2_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 +#define mmDCP2_CUR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_RW_MODE_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP2_DC_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff +#define mmDCP2_DCP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_DCP_CRC_MASK_DEFAULT 0x00000000 +#define mmDCP2_DCP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmDCP2_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmDCP2_DCP_CRC_LAST_DEFAULT 0x00000000 +#define mmDCP2_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmDCP2_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCP2_DCP_GSL_CONTROL_DEFAULT 0x60000020 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 +#define mmDCP2_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 +#define mmDCP2_HW_ROTATION_DEFAULT 0x00000000 +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 +#define mmDCP2_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP2_ALPHA_CONTROL_DEFAULT 0x00000002 +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 +#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 +#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 +#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 +#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_lb2_dispdec +#define mmLB2_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLB2_LB_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLB2_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLB2_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLB2_LB_VLINE_START_END_DEFAULT 0x00000000 +#define mmLB2_LB_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLB2_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmLB2_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLB2_LB_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLB2_LB_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLB2_LB_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLB2_LB_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLB2_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLB2_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLB2_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLB2_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLB2_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLB2_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLB2_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLB2_LB_BUFFER_STATUS_DEFAULT 0x00000002 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 +#define mmLB2_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 +#define mmLB2_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dcfe2_dispdec +#define mmDCFE2_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFE2_DCFE_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFE2_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFE2_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFE2_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFE2_DCFE_MISC_DEFAULT 0x00000001 +#define mmDCFE2_DCFE_FLUSH_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon5_dispdec +#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmif_pg2_dispdec +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIF_PG2_DPG_DVMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_scl2_dispdec +#define mmSCL2_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCL2_SCL_MODE_DEFAULT 0x00000000 +#define mmSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL2_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCL2_SCL_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCL2_SCL_UPDATE_DEFAULT 0x00000000 +#define mmSCL2_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmSCL2_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCL2_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCL2_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCL2_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCL2_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCL2_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCL2_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blnd2_dispdec +#define mmBLND2_BLND_CONTROL_DEFAULT 0xff0220ff +#define mmBLND2_BLND_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLND2_BLND_CONTROL2_DEFAULT 0x00000010 +#define mmBLND2_BLND_UPDATE_DEFAULT 0x00000000 +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLND2_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLND2_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtc2_dispdec +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTC2_CRTC_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VBI_END_DEFAULT 0x00000003 +#define mmCRTC2_CRTC_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CONTROL_DEFAULT 0x80400110 +#define mmCRTC2_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTC2_CRTC_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_GSL_CONTROL_DEFAULT 0x00020000 +#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC2_CRTC_DRR_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_fmt2_dispdec +#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT2_FMT_CRC_CNTL_DEFAULT 0x01000040 +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT2_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcp3_dispdec +#define mmDCP3_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmDCP3_GRPH_CONTROL_DEFAULT 0x20002040 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_PITCH_DEFAULT 0x00000000 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 +#define mmDCP3_GRPH_X_START_DEFAULT 0x00000000 +#define mmDCP3_GRPH_Y_START_DEFAULT 0x00000000 +#define mmDCP3_GRPH_X_END_DEFAULT 0x00000000 +#define mmDCP3_GRPH_Y_END_DEFAULT 0x00000000 +#define mmDCP3_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmDCP3_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 +#define mmDCP3_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_GRPH_DFQ_STATUS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff +#define mmDCP3_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 +#define mmDCP3_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 +#define mmDCP3_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 +#define mmDCP3_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 +#define mmDCP3_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_INPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP3_INPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP3_INPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP3_INPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP3_INPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP3_INPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP3_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP3_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP3_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP3_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP3_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP3_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP3_DENORM_CONTROL_DEFAULT 0x00000003 +#define mmDCP3_OUT_ROUND_CONTROL_DEFAULT 0x0000000a +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff +#define mmDCP3_KEY_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_KEY_RANGE_ALPHA_DEFAULT 0x00000000 +#define mmDCP3_KEY_RANGE_RED_DEFAULT 0x00000000 +#define mmDCP3_KEY_RANGE_GREEN_DEFAULT 0x00000000 +#define mmDCP3_KEY_RANGE_BLUE_DEFAULT 0x00000000 +#define mmDCP3_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmDCP3_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmDCP3_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmDCP3_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmDCP3_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmDCP3_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 +#define mmDCP3_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmDCP3_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmDCP3_CUR_CONTROL_DEFAULT 0x00000810 +#define mmDCP3_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP3_CUR_SIZE_DEFAULT 0x00000000 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP3_CUR_POSITION_DEFAULT 0x00000000 +#define mmDCP3_CUR_HOT_SPOT_DEFAULT 0x00000000 +#define mmDCP3_CUR_COLOR1_DEFAULT 0x00000000 +#define mmDCP3_CUR_COLOR2_DEFAULT 0x00000000 +#define mmDCP3_CUR_UPDATE_DEFAULT 0x00000000 +#define mmDCP3_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 +#define mmDCP3_CUR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_RW_MODE_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP3_DC_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff +#define mmDCP3_DCP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_DCP_CRC_MASK_DEFAULT 0x00000000 +#define mmDCP3_DCP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmDCP3_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmDCP3_DCP_CRC_LAST_DEFAULT 0x00000000 +#define mmDCP3_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmDCP3_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCP3_DCP_GSL_CONTROL_DEFAULT 0x60000020 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 +#define mmDCP3_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 +#define mmDCP3_HW_ROTATION_DEFAULT 0x00000000 +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 +#define mmDCP3_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP3_ALPHA_CONTROL_DEFAULT 0x00000002 +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 +#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 +#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 +#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 +#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_lb3_dispdec +#define mmLB3_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLB3_LB_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLB3_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLB3_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLB3_LB_VLINE_START_END_DEFAULT 0x00000000 +#define mmLB3_LB_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLB3_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmLB3_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLB3_LB_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLB3_LB_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLB3_LB_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLB3_LB_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLB3_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLB3_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLB3_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLB3_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLB3_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLB3_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLB3_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLB3_LB_BUFFER_STATUS_DEFAULT 0x00000002 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 +#define mmLB3_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 +#define mmLB3_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dcfe3_dispdec +#define mmDCFE3_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFE3_DCFE_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFE3_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFE3_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFE3_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFE3_DCFE_MISC_DEFAULT 0x00000001 +#define mmDCFE3_DCFE_FLUSH_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon6_dispdec +#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmif_pg3_dispdec +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIF_PG3_DPG_DVMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_scl3_dispdec +#define mmSCL3_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCL3_SCL_MODE_DEFAULT 0x00000000 +#define mmSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL3_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCL3_SCL_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCL3_SCL_UPDATE_DEFAULT 0x00000000 +#define mmSCL3_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmSCL3_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCL3_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCL3_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCL3_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCL3_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCL3_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCL3_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blnd3_dispdec +#define mmBLND3_BLND_CONTROL_DEFAULT 0xff0220ff +#define mmBLND3_BLND_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLND3_BLND_CONTROL2_DEFAULT 0x00000010 +#define mmBLND3_BLND_UPDATE_DEFAULT 0x00000000 +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLND3_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLND3_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtc3_dispdec +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTC3_CRTC_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VBI_END_DEFAULT 0x00000003 +#define mmCRTC3_CRTC_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CONTROL_DEFAULT 0x80400110 +#define mmCRTC3_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTC3_CRTC_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_GSL_CONTROL_DEFAULT 0x00020000 +#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC3_CRTC_DRR_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_fmt3_dispdec +#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT3_FMT_CRC_CNTL_DEFAULT 0x01000040 +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT3_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcp4_dispdec +#define mmDCP4_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmDCP4_GRPH_CONTROL_DEFAULT 0x20002040 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_PITCH_DEFAULT 0x00000000 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 +#define mmDCP4_GRPH_X_START_DEFAULT 0x00000000 +#define mmDCP4_GRPH_Y_START_DEFAULT 0x00000000 +#define mmDCP4_GRPH_X_END_DEFAULT 0x00000000 +#define mmDCP4_GRPH_Y_END_DEFAULT 0x00000000 +#define mmDCP4_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmDCP4_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 +#define mmDCP4_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_GRPH_DFQ_STATUS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff +#define mmDCP4_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 +#define mmDCP4_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 +#define mmDCP4_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 +#define mmDCP4_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 +#define mmDCP4_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_INPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP4_INPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP4_INPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP4_INPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP4_INPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP4_INPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP4_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP4_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP4_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP4_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP4_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP4_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP4_DENORM_CONTROL_DEFAULT 0x00000003 +#define mmDCP4_OUT_ROUND_CONTROL_DEFAULT 0x0000000a +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff +#define mmDCP4_KEY_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_KEY_RANGE_ALPHA_DEFAULT 0x00000000 +#define mmDCP4_KEY_RANGE_RED_DEFAULT 0x00000000 +#define mmDCP4_KEY_RANGE_GREEN_DEFAULT 0x00000000 +#define mmDCP4_KEY_RANGE_BLUE_DEFAULT 0x00000000 +#define mmDCP4_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmDCP4_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmDCP4_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmDCP4_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmDCP4_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmDCP4_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 +#define mmDCP4_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmDCP4_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmDCP4_CUR_CONTROL_DEFAULT 0x00000810 +#define mmDCP4_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP4_CUR_SIZE_DEFAULT 0x00000000 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP4_CUR_POSITION_DEFAULT 0x00000000 +#define mmDCP4_CUR_HOT_SPOT_DEFAULT 0x00000000 +#define mmDCP4_CUR_COLOR1_DEFAULT 0x00000000 +#define mmDCP4_CUR_COLOR2_DEFAULT 0x00000000 +#define mmDCP4_CUR_UPDATE_DEFAULT 0x00000000 +#define mmDCP4_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 +#define mmDCP4_CUR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_RW_MODE_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP4_DC_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff +#define mmDCP4_DCP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_DCP_CRC_MASK_DEFAULT 0x00000000 +#define mmDCP4_DCP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmDCP4_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmDCP4_DCP_CRC_LAST_DEFAULT 0x00000000 +#define mmDCP4_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmDCP4_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCP4_DCP_GSL_CONTROL_DEFAULT 0x60000020 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 +#define mmDCP4_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 +#define mmDCP4_HW_ROTATION_DEFAULT 0x00000000 +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 +#define mmDCP4_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP4_ALPHA_CONTROL_DEFAULT 0x00000002 +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 +#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 +#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 +#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 +#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_lb4_dispdec +#define mmLB4_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLB4_LB_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLB4_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLB4_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLB4_LB_VLINE_START_END_DEFAULT 0x00000000 +#define mmLB4_LB_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLB4_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmLB4_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLB4_LB_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLB4_LB_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLB4_LB_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLB4_LB_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLB4_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLB4_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLB4_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLB4_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLB4_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLB4_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLB4_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLB4_LB_BUFFER_STATUS_DEFAULT 0x00000002 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 +#define mmLB4_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 +#define mmLB4_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dcfe4_dispdec +#define mmDCFE4_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFE4_DCFE_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFE4_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFE4_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFE4_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFE4_DCFE_MISC_DEFAULT 0x00000001 +#define mmDCFE4_DCFE_FLUSH_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon7_dispdec +#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmif_pg4_dispdec +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIF_PG4_DPG_DVMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_scl4_dispdec +#define mmSCL4_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCL4_SCL_MODE_DEFAULT 0x00000000 +#define mmSCL4_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL4_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL4_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL4_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCL4_SCL_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCL4_SCL_UPDATE_DEFAULT 0x00000000 +#define mmSCL4_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmSCL4_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCL4_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCL4_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCL4_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCL4_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCL4_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCL4_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blnd4_dispdec +#define mmBLND4_BLND_CONTROL_DEFAULT 0xff0220ff +#define mmBLND4_BLND_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLND4_BLND_CONTROL2_DEFAULT 0x00000010 +#define mmBLND4_BLND_UPDATE_DEFAULT 0x00000000 +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLND4_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLND4_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtc4_dispdec +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTC4_CRTC_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VBI_END_DEFAULT 0x00000003 +#define mmCRTC4_CRTC_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CONTROL_DEFAULT 0x80400110 +#define mmCRTC4_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTC4_CRTC_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_GSL_CONTROL_DEFAULT 0x00020000 +#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC4_CRTC_DRR_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_fmt4_dispdec +#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT4_FMT_CRC_CNTL_DEFAULT 0x01000040 +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT4_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcp5_dispdec +#define mmDCP5_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmDCP5_GRPH_CONTROL_DEFAULT 0x20002040 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_PITCH_DEFAULT 0x00000000 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 +#define mmDCP5_GRPH_X_START_DEFAULT 0x00000000 +#define mmDCP5_GRPH_Y_START_DEFAULT 0x00000000 +#define mmDCP5_GRPH_X_END_DEFAULT 0x00000000 +#define mmDCP5_GRPH_Y_END_DEFAULT 0x00000000 +#define mmDCP5_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmDCP5_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 +#define mmDCP5_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_GRPH_DFQ_STATUS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff +#define mmDCP5_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 +#define mmDCP5_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 +#define mmDCP5_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 +#define mmDCP5_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 +#define mmDCP5_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_INPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP5_INPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP5_INPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP5_INPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP5_INPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP5_INPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP5_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 +#define mmDCP5_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 +#define mmDCP5_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 +#define mmDCP5_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 +#define mmDCP5_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 +#define mmDCP5_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 +#define mmDCP5_DENORM_CONTROL_DEFAULT 0x00000003 +#define mmDCP5_OUT_ROUND_CONTROL_DEFAULT 0x0000000a +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff +#define mmDCP5_KEY_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_KEY_RANGE_ALPHA_DEFAULT 0x00000000 +#define mmDCP5_KEY_RANGE_RED_DEFAULT 0x00000000 +#define mmDCP5_KEY_RANGE_GREEN_DEFAULT 0x00000000 +#define mmDCP5_KEY_RANGE_BLUE_DEFAULT 0x00000000 +#define mmDCP5_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmDCP5_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmDCP5_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmDCP5_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmDCP5_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmDCP5_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 +#define mmDCP5_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 +#define mmDCP5_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmDCP5_CUR_CONTROL_DEFAULT 0x00000810 +#define mmDCP5_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP5_CUR_SIZE_DEFAULT 0x00000000 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP5_CUR_POSITION_DEFAULT 0x00000000 +#define mmDCP5_CUR_HOT_SPOT_DEFAULT 0x00000000 +#define mmDCP5_CUR_COLOR1_DEFAULT 0x00000000 +#define mmDCP5_CUR_COLOR2_DEFAULT 0x00000000 +#define mmDCP5_CUR_UPDATE_DEFAULT 0x00000000 +#define mmDCP5_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 +#define mmDCP5_CUR_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_RW_MODE_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP5_DC_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff +#define mmDCP5_DCP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_DCP_CRC_MASK_DEFAULT 0x00000000 +#define mmDCP5_DCP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmDCP5_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmDCP5_DCP_CRC_LAST_DEFAULT 0x00000000 +#define mmDCP5_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmDCP5_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 +#define mmDCP5_DCP_GSL_CONTROL_DEFAULT 0x60000020 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 +#define mmDCP5_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 +#define mmDCP5_HW_ROTATION_DEFAULT 0x00000000 +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 +#define mmDCP5_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmDCP5_ALPHA_CONTROL_DEFAULT 0x00000002 +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 +#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 +#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 +#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 +#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_lb5_dispdec +#define mmLB5_LB_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLB5_LB_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLB5_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLB5_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLB5_LB_VLINE_START_END_DEFAULT 0x00000000 +#define mmLB5_LB_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLB5_LB_V_COUNTER_DEFAULT 0x00000000 +#define mmLB5_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLB5_LB_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLB5_LB_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLB5_LB_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLB5_LB_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLB5_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLB5_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLB5_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLB5_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLB5_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLB5_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLB5_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLB5_LB_BUFFER_STATUS_DEFAULT 0x00000002 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 +#define mmLB5_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 +#define mmLB5_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dcfe5_dispdec +#define mmDCFE5_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFE5_DCFE_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFE5_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFE5_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFE5_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFE5_DCFE_MISC_DEFAULT 0x00000001 +#define mmDCFE5_DCFE_FLUSH_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon8_dispdec +#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmif_pg5_dispdec +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIF_PG5_DPG_DVMM_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_scl5_dispdec +#define mmSCL5_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCL5_SCL_MODE_DEFAULT 0x00000000 +#define mmSCL5_SCL_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL5_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL5_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCL5_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCL5_SCL_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCL5_SCL_UPDATE_DEFAULT 0x00000000 +#define mmSCL5_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 +#define mmSCL5_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCL5_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCL5_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCL5_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCL5_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCL5_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCL5_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blnd5_dispdec +#define mmBLND5_BLND_CONTROL_DEFAULT 0xff0220ff +#define mmBLND5_BLND_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLND5_BLND_CONTROL2_DEFAULT 0x00000010 +#define mmBLND5_BLND_UPDATE_DEFAULT 0x00000000 +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLND5_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLND5_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtc5_dispdec +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTC5_CRTC_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VBI_END_DEFAULT 0x00000003 +#define mmCRTC5_CRTC_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CONTROL_DEFAULT 0x80400110 +#define mmCRTC5_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTC5_CRTC_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_GSL_CONTROL_DEFAULT 0x00020000 +#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTC5_CRTC_DRR_CONTROL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_fmt5_dispdec +#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 +#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 +#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 +#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 +#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 +#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 +#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd +#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000 +#define mmFMT5_FMT_CRC_CNTL_DEFAULT 0x01000040 +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmFMT5_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_unp0_dispdec +#define mmUNP0_UNP_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmUNP0_UNP_GRPH_CONTROL_DEFAULT 0x0a008008 +#define mmUNP0_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000 +#define mmUNP0_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PITCH_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_PITCH_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_X_START_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_X_START_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_Y_START_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_Y_START_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_X_END_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_X_END_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_Y_END_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_Y_END_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000 +#define mmUNP0_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000 +#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220 +#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020 +#define mmUNP0_UNP_FLIP_CONTROL_DEFAULT 0x00000001 +#define mmUNP0_UNP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmUNP0_UNP_CRC_MASK_DEFAULT 0x00000000 +#define mmUNP0_UNP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmUNP0_UNP_CRC_LAST_DEFAULT 0x00000000 +#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100 +#define mmUNP0_UNP_HW_ROTATION_DEFAULT 0x00000010 + + +// addressBlock: dce_dc_lbv0_dispdec +#define mmLBV0_LBV_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLBV0_LBV_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLBV0_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLBV0_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLBV0_LBV_VLINE_START_END_DEFAULT 0x00000000 +#define mmLBV0_LBV_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLBV0_LBV_V_COUNTER_DEFAULT 0x00000000 +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLBV0_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000 +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000 +#define mmLBV0_LBV_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLBV0_LBV_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLBV0_LBV_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLBV0_LBV_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLBV0_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLBV0_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLBV0_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLBV0_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLBV0_LBV_BUFFER_STATUS_DEFAULT 0x12000002 +#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_sclv0_dispdec +#define mmSCLV0_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_MODE_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCLV0_SCLV_UPDATE_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000 + + +// addressBlock: dce_dc_col_man0_dispdec +#define mmCOL_MAN0_COL_MAN_UPDATE_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000 +#define mmCOL_MAN0_PRESCALE_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_PRESCALE_VALUES_R_DEFAULT 0x20000000 +#define mmCOL_MAN0_PRESCALE_VALUES_G_DEFAULT 0x20000000 +#define mmCOL_MAN0_PRESCALE_VALUES_B_DEFAULT 0x20000000 +#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000 +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000 +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000 +#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff +#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmCOL_MAN0_PACK_FIFO_ERROR_DEFAULT 0x00000000 +#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000 +#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 + + +// addressBlock: dce_dc_dcfev0_dispdec +#define mmDCFEV0_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_L_FLUSH_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_C_FLUSH_DEFAULT 0x00000000 +#define mmDCFEV0_DCFEV_MISC_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dc_perfmon11_dispdec +#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmifv_pg0_dispdec +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 +#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 +#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 +#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 +#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 +#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 +#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blndv0_dispdec +#define mmBLNDV0_BLNDV_CONTROL_DEFAULT 0xff0220ff +#define mmBLNDV0_BLNDV_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLNDV0_BLNDV_CONTROL2_DEFAULT 0x00000010 +#define mmBLNDV0_BLNDV_UPDATE_DEFAULT 0x00000000 +#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtcv0_dispdec +#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTCV0_CRTCV_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VBI_END_DEFAULT 0x00000003 +#define mmCRTCV0_CRTCV_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CONTROL_DEFAULT 0x80400110 +#define mmCRTCV0_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTCV0_CRTCV_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTCV0_CRTCV_GSL_CONTROL_DEFAULT 0x00020000 + + +// addressBlock: dce_dc_unp1_dispdec +#define mmUNP1_UNP_GRPH_ENABLE_DEFAULT 0x00000001 +#define mmUNP1_UNP_GRPH_CONTROL_DEFAULT 0x0a008008 +#define mmUNP1_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000 +#define mmUNP1_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PITCH_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_PITCH_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_X_START_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_X_START_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_Y_START_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_Y_START_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_X_END_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_X_END_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_Y_END_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_Y_END_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_UPDATE_DEFAULT 0x00000000 +#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000 +#define mmUNP1_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000 +#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000 +#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 +#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220 +#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020 +#define mmUNP1_UNP_FLIP_CONTROL_DEFAULT 0x00000001 +#define mmUNP1_UNP_CRC_CONTROL_DEFAULT 0x00000000 +#define mmUNP1_UNP_CRC_MASK_DEFAULT 0x00000000 +#define mmUNP1_UNP_CRC_CURRENT_DEFAULT 0x00000000 +#define mmUNP1_UNP_CRC_LAST_DEFAULT 0x00000000 +#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100 +#define mmUNP1_UNP_HW_ROTATION_DEFAULT 0x00000010 + + +// addressBlock: dce_dc_lbv1_dispdec +#define mmLBV1_LBV_DATA_FORMAT_DEFAULT 0x00000000 +#define mmLBV1_LBV_MEMORY_CTRL_DEFAULT 0x000006b0 +#define mmLBV1_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 +#define mmLBV1_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000 +#define mmLBV1_LBV_VLINE_START_END_DEFAULT 0x00000000 +#define mmLBV1_LBV_VLINE2_START_END_DEFAULT 0x00000000 +#define mmLBV1_LBV_V_COUNTER_DEFAULT 0x00000000 +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 +#define mmLBV1_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000 +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000 +#define mmLBV1_LBV_INTERRUPT_MASK_DEFAULT 0x00000000 +#define mmLBV1_LBV_VLINE_STATUS_DEFAULT 0x00000000 +#define mmLBV1_LBV_VLINE2_STATUS_DEFAULT 0x00000000 +#define mmLBV1_LBV_VBLANK_STATUS_DEFAULT 0x00000000 +#define mmLBV1_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002 +#define mmLBV1_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000 +#define mmLBV1_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000 +#define mmLBV1_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 +#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 +#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 +#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 +#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 +#define mmLBV1_LBV_BUFFER_STATUS_DEFAULT 0x12000002 +#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_sclv1_dispdec +#define mmSCLV1_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_MODE_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_TAP_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_ROUND_OFFSET_DEFAULT 0x80000000 +#define mmSCLV1_SCLV_UPDATE_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_ALU_CONTROL_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VIEWPORT_START_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000 + + +// addressBlock: dce_dc_col_man1_dispdec +#define mmCOL_MAN1_COL_MAN_UPDATE_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000 +#define mmCOL_MAN1_PRESCALE_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_PRESCALE_VALUES_R_DEFAULT 0x20000000 +#define mmCOL_MAN1_PRESCALE_VALUES_G_DEFAULT 0x20000000 +#define mmCOL_MAN1_PRESCALE_VALUES_B_DEFAULT 0x20000000 +#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000 +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000 +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000 +#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff +#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 +#define mmCOL_MAN1_PACK_FIFO_ERROR_DEFAULT 0x00000000 +#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000 +#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 + + +// addressBlock: dce_dc_dcfev1_dispdec +#define mmDCFEV1_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_SOFT_RESET_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_L_FLUSH_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_C_FLUSH_DEFAULT 0x00000000 +#define mmDCFEV1_DCFEV_MISC_DEFAULT 0x00000001 + + +// addressBlock: dce_dc_dc_perfmon12_dispdec +#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dmifv_pg1_dispdec +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 +#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 +#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 +#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 +#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 +#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 +#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000 +#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_blndv1_dispdec +#define mmBLNDV1_BLNDV_CONTROL_DEFAULT 0xff0220ff +#define mmBLNDV1_BLNDV_SM_CONTROL2_DEFAULT 0x00000000 +#define mmBLNDV1_BLNDV_CONTROL2_DEFAULT 0x00000010 +#define mmBLNDV1_BLNDV_UPDATE_DEFAULT 0x00000000 +#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 +#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000 +#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_crtcv1_dispdec +#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 +#define mmCRTCV1_CRTCV_H_TOTAL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_H_SYNC_A_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_H_SYNC_B_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VBI_END_DEFAULT 0x00000003 +#define mmCRTCV1_CRTCV_V_TOTAL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_SYNC_A_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_SYNC_B_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CONTROL_DEFAULT 0x80400110 +#define mmCRTCV1_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STATUS_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_COUNT_RESET_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STEREO_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002 +#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 +#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 +#define mmCRTCV1_CRTCV_MVP_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_MASTER_EN_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 +#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_BLACK_COLOR_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC_CNTL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 +#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 +#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_GSL_WINDOW_DEFAULT 0x00000000 +#define mmCRTCV1_CRTCV_GSL_CONTROL_DEFAULT 0x00020000 + + +// addressBlock: dce_dc_hpd0_dispdec +#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hpd1_dispdec +#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hpd2_dispdec +#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hpd3_dispdec +#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hpd4_dispdec +#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hpd5_dispdec +#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000 +#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 +#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon2_dispdec +#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp_aux0_dispdec +#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp_aux1_dispdec +#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp_aux2_dispdec +#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp_aux3_dispdec +#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp_aux4_dispdec +#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp_aux5_dispdec +#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000 +#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig0_dispdec +#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp0_dispdec +#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP0_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP0_DP_VID_N_DEFAULT 0x00002000 +#define mmDP0_DP_VID_M_DEFAULT 0x00000000 +#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig1_dispdec +#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp1_dispdec +#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP1_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP1_DP_VID_N_DEFAULT 0x00002000 +#define mmDP1_DP_VID_M_DEFAULT 0x00000000 +#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig2_dispdec +#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp2_dispdec +#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP2_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP2_DP_VID_N_DEFAULT 0x00002000 +#define mmDP2_DP_VID_M_DEFAULT 0x00000000 +#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig3_dispdec +#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp3_dispdec +#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP3_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP3_DP_VID_N_DEFAULT 0x00002000 +#define mmDP3_DP_VID_M_DEFAULT 0x00000000 +#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig4_dispdec +#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp4_dispdec +#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP4_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP4_DP_VID_N_DEFAULT 0x00002000 +#define mmDP4_DP_VID_M_DEFAULT 0x00000000 +#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig5_dispdec +#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp5_dispdec +#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP5_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP5_DP_VID_N_DEFAULT 0x00002000 +#define mmDP5_DP_VID_M_DEFAULT 0x00000000 +#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dig6_dispdec +#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 +#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 +#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001 +#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000 +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 +#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 +#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GC_DEFAULT 0x00000004 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AVI_INFO0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AVI_INFO1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AVI_INFO2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AVI_INFO3_DEFAULT 0x02000000 +#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000 +#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 +#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 +#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 +#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 +#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 +#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000 +#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001 +#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000 +#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 +#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000 +#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000 +#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dp6_dispdec +#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 +#define mmDP6_DP_CONFIG_DEFAULT 0x00000000 +#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 +#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000 +#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000 +#define mmDP6_DP_VID_N_DEFAULT 0x00002000 +#define mmDP6_DP_VID_M_DEFAULT 0x00000000 +#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 +#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 +#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000 +#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 +#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 +#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 +#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200 +#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000 +#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 +#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 +#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff +#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 +#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy0_dispdec +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs0_dispdec +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs0_dispdec +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs0_dispdec +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy1_dispdec +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs1_dispdec +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs1_dispdec +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs1_dispdec +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy2_dispdec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs2_dispdec +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs2_dispdec +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs2_dispdec +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy3_dispdec +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs3_dispdec +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs3_dispdec +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs3_dispdec +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy4_dispdec +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs4_dispdec +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs4_dispdec +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs4_dispdec +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy5_dispdec +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs5_dispdec +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs5_dispdec +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs5_dispdec +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy6_dispdec +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs6_dispdec +#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs6_dispdec +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs6_dispdec +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dcio_uniphy8_dispdec +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophycmregs8_dispdec +#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 +#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 +#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_DEFAULT 0x00000007 +#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_DEFAULT 0x000000ff +#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_DEFAULT 0x00000000 +#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophytxregs8_dispdec +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 +#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 +#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_combophypllregs8_dispdec +#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_DEFAULT 0x00280000 +#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_DEFAULT 0x00e80000 +#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 +#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_DEFAULT 0x00000001 +#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_DEFAULT 0x64000000 +#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_DEFAULT 0x00000090 +#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_DEFAULT 0x00000000 +#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dsi0_dispdec +#define mmDSI0_DISP_DSI_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_STATUS_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000 +#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101 +#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e +#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900 +#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066 +#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c +#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900 +#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211 +#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02 +#define mmDSI0_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_EXT_MUX_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_EXT_RESET_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888 +#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff +#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff +#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08 +#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f +#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222 +#define mmDSI0_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001 +#define mmDSI0_DISP_DSI_TE_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000 +#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dsi1_dispdec +#define mmDSI1_DISP_DSI_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_STATUS_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000 +#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101 +#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e +#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900 +#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066 +#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c +#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900 +#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211 +#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02 +#define mmDSI1_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_EXT_MUX_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_EXT_RESET_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888 +#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff +#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff +#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08 +#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f +#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222 +#define mmDSI1_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001 +#define mmDSI1_DISP_DSI_TE_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000 +#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dprx_sd0_dispdec +#define mmDPRX_SD0_DPRX_SD_CONTROL_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA0_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA1_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA2_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA3_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA4_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA5_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA6_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA7_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA8_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_VBID_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSE_SAT_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff +#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff +#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff +#define mmDPRX_SD0_DPRX_SD_SDP_STEER_DEFAULT 0x00000001 +#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_SDP_DATA_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001 +#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000 +#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dprx_sd1_dispdec +#define mmDPRX_SD1_DPRX_SD_CONTROL_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA0_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA1_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA2_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA3_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA4_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA5_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA6_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA7_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA8_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_VBID_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSE_SAT_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff +#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff +#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff +#define mmDPRX_SD1_DPRX_SD_SDP_STEER_DEFAULT 0x00000001 +#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_SDP_DATA_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001 +#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000 +#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_perfmon10_dispdec +#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100 +#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000 +#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dc_zcalregs_dispdec +#define mmCOMP_EN_CTL_DEFAULT 0x00080000 +#define mmCOMP_EN_DFX_DEFAULT 0x00000000 +#define mmZCAL_FUSES_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR + + +// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR + + +// addressBlock: dce_dc_dispdec[948..986] + + +// addressBlock: dce_dc_azdec +#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 +#define mmCORB_READ_POINTER_DEFAULT 0x00000000 +#define mmCORB_CONTROL_DEFAULT 0x00000000 +#define mmCORB_STATUS_DEFAULT 0x00000000 +#define mmCORB_SIZE_DEFAULT 0x00000002 +#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 +#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 +#define mmRIRB_CONTROL_DEFAULT 0x00000000 +#define mmRIRB_STATUS_DEFAULT 0x00000000 +#define mmRIRB_SIZE_DEFAULT 0x00000002 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 +#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream0_azdec +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream1_azdec +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream2_azdec +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream3_azdec +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream4_azdec +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream5_azdec +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream6_azdec +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_azstream7_azdec +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: azf0stream0_streamind +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream1_streamind +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream2_streamind +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream3_streamind +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream4_streamind +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream5_streamind +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream6_streamind +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream7_streamind +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream8_streamind +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream9_streamind +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream10_streamind +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream11_streamind +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream12_streamind +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream13_streamind +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream14_streamind +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0stream15_streamind +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint0_endpointind +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint1_endpointind +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint2_endpointind +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint3_endpointind +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint4_endpointind +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint5_endpointind +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint6_endpointind +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0endpoint7_endpointind +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint0_inputendpointind +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint1_inputendpointind +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint2_inputendpointind +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint3_inputendpointind +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint4_inputendpointind +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint5_inputendpointind +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint6_inputendpointind +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: azf0inputendpoint7_inputendpointind +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 + + +// addressBlock: f2codecind +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 + + +// addressBlock: descriptorind +#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000 +#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000 + + +// addressBlock: sinkinfoind +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000 +#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000 + + +// addressBlock: azinputcrc0resultind +#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azinputcrc1resultind +#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azcrc0resultind +#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: azcrc1resultind +#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000 +#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000 + + +// addressBlock: vgaseqind +#define ixSEQ00_DEFAULT 0x00000003 +#define ixSEQ01_DEFAULT 0x00000021 +#define ixSEQ02_DEFAULT 0x00000000 +#define ixSEQ03_DEFAULT 0x00000000 +#define ixSEQ04_DEFAULT 0x00000000 + + +// addressBlock: vgacrtind +#define ixCRT00_DEFAULT 0x00000000 +#define ixCRT01_DEFAULT 0x00000000 +#define ixCRT02_DEFAULT 0x00000000 +#define ixCRT03_DEFAULT 0x00000000 +#define ixCRT04_DEFAULT 0x00000000 +#define ixCRT05_DEFAULT 0x00000000 +#define ixCRT06_DEFAULT 0x00000000 +#define ixCRT07_DEFAULT 0x00000000 +#define ixCRT08_DEFAULT 0x00000000 +#define ixCRT09_DEFAULT 0x00000000 +#define ixCRT0A_DEFAULT 0x00000000 +#define ixCRT0B_DEFAULT 0x00000000 +#define ixCRT0C_DEFAULT 0x00000000 +#define ixCRT0D_DEFAULT 0x00000000 +#define ixCRT0E_DEFAULT 0x00000000 +#define ixCRT0F_DEFAULT 0x00000000 +#define ixCRT10_DEFAULT 0x00000000 +#define ixCRT11_DEFAULT 0x00000000 +#define ixCRT12_DEFAULT 0x00000000 +#define ixCRT13_DEFAULT 0x00000000 +#define ixCRT14_DEFAULT 0x00000000 +#define ixCRT15_DEFAULT 0x00000000 +#define ixCRT16_DEFAULT 0x00000000 +#define ixCRT17_DEFAULT 0x00000000 +#define ixCRT18_DEFAULT 0x00000000 +#define ixCRT1E_DEFAULT 0x00000000 +#define ixCRT1F_DEFAULT 0x00000000 +#define ixCRT22_DEFAULT 0x00000000 + + +// addressBlock: vgagrphind +#define ixGRA00_DEFAULT 0x00000000 +#define ixGRA01_DEFAULT 0x00000000 +#define ixGRA02_DEFAULT 0x00000000 +#define ixGRA03_DEFAULT 0x00000000 +#define ixGRA04_DEFAULT 0x00000000 +#define ixGRA05_DEFAULT 0x00000000 +#define ixGRA06_DEFAULT 0x00000000 +#define ixGRA07_DEFAULT 0x00000000 +#define ixGRA08_DEFAULT 0x00000000 + + +// addressBlock: vgaattrind +#define ixATTR00_DEFAULT 0x00000000 +#define ixATTR01_DEFAULT 0x00000000 +#define ixATTR02_DEFAULT 0x00000000 +#define ixATTR03_DEFAULT 0x00000000 +#define ixATTR04_DEFAULT 0x00000000 +#define ixATTR05_DEFAULT 0x00000000 +#define ixATTR06_DEFAULT 0x00000000 +#define ixATTR07_DEFAULT 0x00000000 +#define ixATTR08_DEFAULT 0x00000000 +#define ixATTR09_DEFAULT 0x00000000 +#define ixATTR0A_DEFAULT 0x00000000 +#define ixATTR0B_DEFAULT 0x00000000 +#define ixATTR0C_DEFAULT 0x00000000 +#define ixATTR0D_DEFAULT 0x00000000 +#define ixATTR0E_DEFAULT 0x00000000 +#define ixATTR0F_DEFAULT 0x00000000 +#define ixATTR10_DEFAULT 0x00000000 +#define ixATTR11_DEFAULT 0x00000000 +#define ixATTR12_DEFAULT 0x00000000 +#define ixATTR13_DEFAULT 0x00000000 +#define ixATTR14_DEFAULT 0x00000000 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h new file mode 100644 index 000000000000..75b660d57bdf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h @@ -0,0 +1,18193 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dce_12_0_OFFSET_HEADER +#define _dce_12_0_OFFSET_HEADER + + + +// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR +// base address: 0x48 +#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012 +#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 + + +// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR +// base address: 0x4c +#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014 +#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 + + +// addressBlock: dce_dc_dc_perfmon0_dispdec +// base address: 0x0 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022 +#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL 0x0023 +#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024 +#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_HI 0x0027 +#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_LOW 0x0028 +#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon13_dispdec +// base address: 0x30 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c +#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e +#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL 0x002f +#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030 +#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_HI 0x0033 +#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_LOW 0x0034 +#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_displaypllregs_dispdec +// base address: 0x0 +#define mmPPLL_VREG_CFG 0x0038 +#define mmPPLL_VREG_CFG_BASE_IDX 2 +#define mmPPLL_MODE_CNTL 0x0039 +#define mmPPLL_MODE_CNTL_BASE_IDX 2 +#define mmPPLL_FREQ_CTRL0 0x003a +#define mmPPLL_FREQ_CTRL0_BASE_IDX 2 +#define mmPPLL_FREQ_CTRL1 0x003b +#define mmPPLL_FREQ_CTRL1_BASE_IDX 2 +#define mmPPLL_FREQ_CTRL2 0x003c +#define mmPPLL_FREQ_CTRL2_BASE_IDX 2 +#define mmPPLL_FREQ_CTRL3 0x003d +#define mmPPLL_FREQ_CTRL3_BASE_IDX 2 +#define mmPPLL_BW_CTRL_COARSE 0x003e +#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2 +#define mmPPLL_BW_CTRL_FINE 0x0040 +#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2 +#define mmPPLL_CAL_CTRL 0x0041 +#define mmPPLL_CAL_CTRL_BASE_IDX 2 +#define mmPPLL_LOOP_CTRL 0x0042 +#define mmPPLL_LOOP_CTRL_BASE_IDX 2 +#define mmPPLL_REFCLK_CNTL 0x0050 +#define mmPPLL_REFCLK_CNTL_BASE_IDX 2 +#define mmPPLL_CLKOUT_CNTL 0x0051 +#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2 +#define mmPPLL_DFT_CNTL 0x0052 +#define mmPPLL_DFT_CNTL_BASE_IDX 2 +#define mmPPLL_ANALOG_CNTL 0x0053 +#define mmPPLL_ANALOG_CNTL_BASE_IDX 2 +#define mmPPLL_POSTDIV 0x0054 +#define mmPPLL_POSTDIV_BASE_IDX 2 +#define mmPPLL_OBSERVE0 0x0059 +#define mmPPLL_OBSERVE0_BASE_IDX 2 +#define mmPPLL_OBSERVE1 0x005a +#define mmPPLL_OBSERVE1_BASE_IDX 2 +#define mmPPLL_UPDATE_CNTL 0x005c +#define mmPPLL_UPDATE_CNTL_BASE_IDX 2 +#define mmPPLL_OBSERVE0_OUT 0x005d +#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_pll0_dispdec +// base address: 0x0 +#define mmPLL_MACRO_CNTL_RESERVED0 0x0038 +#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED1 0x0039 +#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED2 0x003a +#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED3 0x003b +#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED4 0x003c +#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED5 0x003d +#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED6 0x003e +#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED7 0x003f +#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED8 0x0040 +#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED9 0x0041 +#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED10 0x0042 +#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED11 0x0043 +#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED12 0x0044 +#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED13 0x0045 +#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED14 0x0046 +#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED15 0x0047 +#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED16 0x0048 +#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED17 0x0049 +#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED18 0x004a +#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED19 0x004b +#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED20 0x004c +#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED21 0x004d +#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED22 0x004e +#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED23 0x004f +#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED24 0x0050 +#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED25 0x0051 +#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED26 0x0052 +#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED27 0x0053 +#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED28 0x0054 +#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED29 0x0055 +#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED30 0x0056 +#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED31 0x0057 +#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED32 0x0058 +#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED33 0x0059 +#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED34 0x005a +#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED35 0x005b +#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED36 0x005c +#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED37 0x005d +#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED38 0x005e +#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED39 0x005f +#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED40 0x0060 +#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED41 0x0061 +#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon1_dispdec +// base address: 0x598 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188 +#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL 0x0189 +#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a +#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_HI 0x018d +#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_LOW 0x018e +#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mcif_wb0_dispdec +// base address: 0x0 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295 +#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 + + +// addressBlock: dce_dc_mcif_wb1_dispdec +// base address: 0x100 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5 +#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 + + +// addressBlock: dce_dc_mcif_wb2_dispdec +// base address: 0x200 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5 +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff +#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315 +#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 +#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317 +#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 +#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319 +#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b +#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c +#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 + + +// addressBlock: dce_dc_cwb0_dispdec +// base address: 0x0 +#define mmCWB0_CWB_CTRL 0x0332 +#define mmCWB0_CWB_CTRL_BASE_IDX 2 +#define mmCWB0_CWB_FENCE_PAR0 0x0334 +#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2 +#define mmCWB0_CWB_FENCE_PAR1 0x0335 +#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2 +#define mmCWB0_CWB_CRC_CTRL 0x0339 +#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2 +#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a +#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2 +#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b +#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2 +#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c +#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2 +#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d +#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2 + + +// addressBlock: dce_dc_cwb1_dispdec +// base address: 0x60 +#define mmCWB1_CWB_CTRL 0x034a +#define mmCWB1_CWB_CTRL_BASE_IDX 2 +#define mmCWB1_CWB_FENCE_PAR0 0x034c +#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2 +#define mmCWB1_CWB_FENCE_PAR1 0x034d +#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2 +#define mmCWB1_CWB_CRC_CTRL 0x0351 +#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2 +#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352 +#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2 +#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353 +#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2 +#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354 +#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2 +#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355 +#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon9_dispdec +// base address: 0xd08 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364 +#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL 0x0365 +#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366 +#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_HI 0x0369 +#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_LOW 0x036a +#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dispdec +// base address: 0x0 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 +#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 +#define mmVGA_RENDER_CONTROL 0x0000 +#define mmVGA_RENDER_CONTROL_BASE_IDX 1 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define mmVGA_MODE_CONTROL 0x0002 +#define mmVGA_MODE_CONTROL_BASE_IDX 1 +#define mmVGA_SURFACE_PITCH_SELECT 0x0003 +#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 +#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define mmVGA_HDP_CONTROL 0x000a +#define mmVGA_HDP_CONTROL_BASE_IDX 1 +#define mmVGA_CACHE_CONTROL 0x000b +#define mmVGA_CACHE_CONTROL_BASE_IDX 1 +#define mmD1VGA_CONTROL 0x000c +#define mmD1VGA_CONTROL_BASE_IDX 1 +#define mmD2VGA_CONTROL 0x000e +#define mmD2VGA_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS 0x0010 +#define mmVGA_STATUS_BASE_IDX 1 +#define mmVGA_INTERRUPT_CONTROL 0x0011 +#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS_CLEAR 0x0012 +#define mmVGA_STATUS_CLEAR_BASE_IDX 1 +#define mmVGA_INTERRUPT_STATUS 0x0013 +#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define mmVGA_MAIN_CONTROL 0x0014 +#define mmVGA_MAIN_CONTROL_BASE_IDX 1 +#define mmVGA_TEST_CONTROL 0x0015 +#define mmVGA_TEST_CONTROL_BASE_IDX 1 +#define mmVGA_QOS_CTRL 0x0018 +#define mmVGA_QOS_CTRL_BASE_IDX 1 +#define mmCRTC8_IDX 0x002d +#define mmCRTC8_IDX_BASE_IDX 1 +#define mmCRTC8_DATA 0x002d +#define mmCRTC8_DATA_BASE_IDX 1 +#define mmGENFC_WT 0x002e +#define mmGENFC_WT_BASE_IDX 1 +#define mmGENS1 0x002e +#define mmGENS1_BASE_IDX 1 +#define mmATTRDW 0x0030 +#define mmATTRDW_BASE_IDX 1 +#define mmATTRX 0x0030 +#define mmATTRX_BASE_IDX 1 +#define mmATTRDR 0x0030 +#define mmATTRDR_BASE_IDX 1 +#define mmGENMO_WT 0x0030 +#define mmGENMO_WT_BASE_IDX 1 +#define mmGENS0 0x0030 +#define mmGENS0_BASE_IDX 1 +#define mmGENENB 0x0030 +#define mmGENENB_BASE_IDX 1 +#define mmSEQ8_IDX 0x0031 +#define mmSEQ8_IDX_BASE_IDX 1 +#define mmSEQ8_DATA 0x0031 +#define mmSEQ8_DATA_BASE_IDX 1 +#define mmDAC_MASK 0x0031 +#define mmDAC_MASK_BASE_IDX 1 +#define mmDAC_R_INDEX 0x0031 +#define mmDAC_R_INDEX_BASE_IDX 1 +#define mmDAC_W_INDEX 0x0032 +#define mmDAC_W_INDEX_BASE_IDX 1 +#define mmDAC_DATA 0x0032 +#define mmDAC_DATA_BASE_IDX 1 +#define mmGENFC_RD 0x0032 +#define mmGENFC_RD_BASE_IDX 1 +#define mmGENMO_RD 0x0033 +#define mmGENMO_RD_BASE_IDX 1 +#define mmGRPH8_IDX 0x0033 +#define mmGRPH8_IDX_BASE_IDX 1 +#define mmGRPH8_DATA 0x0033 +#define mmGRPH8_DATA_BASE_IDX 1 +#define mmCRTC8_IDX_1 0x0035 +#define mmCRTC8_IDX_1_BASE_IDX 1 +#define mmCRTC8_DATA_1 0x0035 +#define mmCRTC8_DATA_1_BASE_IDX 1 +#define mmGENFC_WT_1 0x0036 +#define mmGENFC_WT_1_BASE_IDX 1 +#define mmGENS1_1 0x0036 +#define mmGENS1_1_BASE_IDX 1 +#define mmD3VGA_CONTROL 0x0038 +#define mmD3VGA_CONTROL_BASE_IDX 1 +#define mmD4VGA_CONTROL 0x0039 +#define mmD4VGA_CONTROL_BASE_IDX 1 +#define mmD5VGA_CONTROL 0x003a +#define mmD5VGA_CONTROL_BASE_IDX 1 +#define mmD6VGA_CONTROL 0x003b +#define mmD6VGA_CONTROL_BASE_IDX 1 +#define mmVGA_SOURCE_SELECT 0x003c +#define mmVGA_SOURCE_SELECT_BASE_IDX 1 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044 +#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045 +#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046 +#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047 +#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmREFCLK_CNTL 0x0049 +#define mmREFCLK_CNTL_BASE_IDX 1 +#define mmMIPI_CLK_CNTL 0x004a +#define mmMIPI_CLK_CNTL_BASE_IDX 1 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL2 0x004e +#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f +#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_CBUS_WRCMD_DELAY 0x0050 +#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1 +#define mmDCCG_DS_DTO_INCR 0x0053 +#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 +#define mmDCCG_DS_DTO_MODULO 0x0054 +#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_DS_CNTL 0x0055 +#define mmDCCG_DS_CNTL_BASE_IDX 1 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define mmSYMCLKG_CLOCK_ENABLE 0x0057 +#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1 +#define mmDPREFCLK_CNTL 0x0058 +#define mmDPREFCLK_CNTL_BASE_IDX 1 +#define mmAOMCLK0_CNTL 0x0059 +#define mmAOMCLK0_CNTL_BASE_IDX 1 +#define mmAOMCLK1_CNTL 0x005a +#define mmAOMCLK1_CNTL_BASE_IDX 1 +#define mmAOMCLK2_CNTL 0x005b +#define mmAOMCLK2_CNTL_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO2_PHASE 0x005c +#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO2_MODULO 0x005d +#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1 +#define mmDCE_VERSION 0x005e +#define mmDCE_VERSION_BASE_IDX 1 +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_GTC_CNTL 0x0060 +#define mmDCCG_GTC_CNTL_BASE_IDX 1 +#define mmDCCG_GTC_DTO_INCR 0x0061 +#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define mmDCCG_GTC_DTO_MODULO 0x0062 +#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_GTC_CURRENT 0x0063 +#define mmDCCG_GTC_CURRENT_BASE_IDX 1 +#define mmDENTIST_DISPCLK_CNTL 0x0064 +#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 +#define mmMIPI_DTO_CNTL 0x0065 +#define mmMIPI_DTO_CNTL_BASE_IDX 1 +#define mmMIPI_DTO_PHASE 0x0066 +#define mmMIPI_DTO_PHASE_BASE_IDX 1 +#define mmMIPI_DTO_MODULO 0x0067 +#define mmMIPI_DTO_MODULO_BASE_IDX 1 +#define mmDAC_CLK_ENABLE 0x0068 +#define mmDAC_CLK_ENABLE_BASE_IDX 1 +#define mmDVO_CLK_ENABLE 0x0069 +#define mmDVO_CLK_ENABLE_BASE_IDX 1 +#define mmAVSYNC_COUNTER_WRITE 0x006a +#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1 +#define mmAVSYNC_COUNTER_CONTROL 0x006b +#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c +#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1 +#define mmSMU_CONTROL 0x006d +#define mmSMU_CONTROL_BASE_IDX 1 +#define mmSMU_INTERRUPT_CONTROL 0x006e +#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1 +#define mmAVSYNC_COUNTER_READ 0x006f +#define mmAVSYNC_COUNTER_READ_BASE_IDX 1 +#define mmMILLISECOND_TIME_BASE_DIV 0x0070 +#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL 0x0073 +#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL 0x0074 +#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076 +#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_CAC_STATUS 0x0077 +#define mmDCCG_CAC_STATUS_BASE_IDX 1 +#define mmPIXCLK1_RESYNC_CNTL 0x0078 +#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1 +#define mmPIXCLK2_RESYNC_CNTL 0x0079 +#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1 +#define mmPIXCLK0_RESYNC_CNTL 0x007a +#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1 +#define mmMICROSECOND_TIME_BASE_DIV 0x007b +#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL2 0x007c +#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e +#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_DISP_CNTL_REG 0x007f +#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define mmCRTC0_PIXEL_RATE_CNTL 0x0080 +#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO0_PHASE 0x0081 +#define mmDP_DTO0_PHASE_BASE_IDX 1 +#define mmDP_DTO0_MODULO 0x0082 +#define mmDP_DTO0_MODULO_BASE_IDX 1 +#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmCRTC1_PIXEL_RATE_CNTL 0x0084 +#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO1_PHASE 0x0085 +#define mmDP_DTO1_PHASE_BASE_IDX 1 +#define mmDP_DTO1_MODULO 0x0086 +#define mmDP_DTO1_MODULO_BASE_IDX 1 +#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmCRTC2_PIXEL_RATE_CNTL 0x0088 +#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO2_PHASE 0x0089 +#define mmDP_DTO2_PHASE_BASE_IDX 1 +#define mmDP_DTO2_MODULO 0x008a +#define mmDP_DTO2_MODULO_BASE_IDX 1 +#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmCRTC3_PIXEL_RATE_CNTL 0x008c +#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO3_PHASE 0x008d +#define mmDP_DTO3_PHASE_BASE_IDX 1 +#define mmDP_DTO3_MODULO 0x008e +#define mmDP_DTO3_MODULO_BASE_IDX 1 +#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmCRTC4_PIXEL_RATE_CNTL 0x0090 +#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO4_PHASE 0x0091 +#define mmDP_DTO4_PHASE_BASE_IDX 1 +#define mmDP_DTO4_MODULO 0x0092 +#define mmDP_DTO4_MODULO_BASE_IDX 1 +#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093 +#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmCRTC5_PIXEL_RATE_CNTL 0x0094 +#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO5_PHASE 0x0095 +#define mmDP_DTO5_PHASE_BASE_IDX 1 +#define mmDP_DTO5_MODULO 0x0096 +#define mmDP_DTO5_MODULO_BASE_IDX 1 +#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097 +#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDCCG_SOFT_RESET 0x009f +#define mmDCCG_SOFT_RESET_BASE_IDX 1 +#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 +#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 +#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKC_CLOCK_ENABLE 0x00a2 +#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKD_CLOCK_ENABLE 0x00a3 +#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKE_CLOCK_ENABLE 0x00a4 +#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKF_CLOCK_ENABLE 0x00a5 +#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 +#define mmDVOACLKD_CNTL 0x00a8 +#define mmDVOACLKD_CNTL_BASE_IDX 1 +#define mmDVOACLKC_MVP_CNTL 0x00a9 +#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1 +#define mmDVOACLKC_CNTL 0x00aa +#define mmDVOACLKC_CNTL_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab +#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac +#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad +#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae +#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_MODULE 0x00af +#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define mmDCCG_TEST_CLK_SEL 0x00be +#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1 +#define mmFBC_CNTL 0x0062 +#define mmFBC_CNTL_BASE_IDX 2 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064 +#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2 +#define mmFBC_START_STOP_DELAY 0x0065 +#define mmFBC_START_STOP_DELAY_BASE_IDX 2 +#define mmFBC_COMP_CNTL 0x0066 +#define mmFBC_COMP_CNTL_BASE_IDX 2 +#define mmFBC_COMP_MODE 0x0067 +#define mmFBC_COMP_MODE_BASE_IDX 2 +#define mmFBC_IND_LUT0 0x006b +#define mmFBC_IND_LUT0_BASE_IDX 2 +#define mmFBC_IND_LUT1 0x006c +#define mmFBC_IND_LUT1_BASE_IDX 2 +#define mmFBC_IND_LUT2 0x006d +#define mmFBC_IND_LUT2_BASE_IDX 2 +#define mmFBC_IND_LUT3 0x006e +#define mmFBC_IND_LUT3_BASE_IDX 2 +#define mmFBC_IND_LUT4 0x006f +#define mmFBC_IND_LUT4_BASE_IDX 2 +#define mmFBC_IND_LUT5 0x0070 +#define mmFBC_IND_LUT5_BASE_IDX 2 +#define mmFBC_IND_LUT6 0x0071 +#define mmFBC_IND_LUT6_BASE_IDX 2 +#define mmFBC_IND_LUT7 0x0072 +#define mmFBC_IND_LUT7_BASE_IDX 2 +#define mmFBC_IND_LUT8 0x0073 +#define mmFBC_IND_LUT8_BASE_IDX 2 +#define mmFBC_IND_LUT9 0x0074 +#define mmFBC_IND_LUT9_BASE_IDX 2 +#define mmFBC_IND_LUT10 0x0075 +#define mmFBC_IND_LUT10_BASE_IDX 2 +#define mmFBC_IND_LUT11 0x0076 +#define mmFBC_IND_LUT11_BASE_IDX 2 +#define mmFBC_IND_LUT12 0x0077 +#define mmFBC_IND_LUT12_BASE_IDX 2 +#define mmFBC_IND_LUT13 0x0078 +#define mmFBC_IND_LUT13_BASE_IDX 2 +#define mmFBC_IND_LUT14 0x0079 +#define mmFBC_IND_LUT14_BASE_IDX 2 +#define mmFBC_IND_LUT15 0x007a +#define mmFBC_IND_LUT15_BASE_IDX 2 +#define mmFBC_CSM_REGION_OFFSET_01 0x007b +#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2 +#define mmFBC_CSM_REGION_OFFSET_23 0x007c +#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2 +#define mmFBC_CLIENT_REGION_MASK 0x007d +#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2 +#define mmFBC_DEBUG_COMP 0x007e +#define mmFBC_DEBUG_COMP_BASE_IDX 2 +#define mmFBC_MISC 0x0084 +#define mmFBC_MISC_BASE_IDX 2 +#define mmFBC_STATUS 0x0085 +#define mmFBC_STATUS_BASE_IDX 2 +#define mmFBC_ALPHA_CNTL 0x0088 +#define mmFBC_ALPHA_CNTL_BASE_IDX 2 +#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089 +#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2 +#define mmPIPE0_PG_CONFIG 0x008e +#define mmPIPE0_PG_CONFIG_BASE_IDX 2 +#define mmPIPE0_PG_ENABLE 0x008f +#define mmPIPE0_PG_ENABLE_BASE_IDX 2 +#define mmPIPE0_PG_STATUS 0x0090 +#define mmPIPE0_PG_STATUS_BASE_IDX 2 +#define mmPIPE1_PG_CONFIG 0x0091 +#define mmPIPE1_PG_CONFIG_BASE_IDX 2 +#define mmPIPE1_PG_ENABLE 0x0092 +#define mmPIPE1_PG_ENABLE_BASE_IDX 2 +#define mmPIPE1_PG_STATUS 0x0093 +#define mmPIPE1_PG_STATUS_BASE_IDX 2 +#define mmPIPE2_PG_CONFIG 0x0094 +#define mmPIPE2_PG_CONFIG_BASE_IDX 2 +#define mmPIPE2_PG_ENABLE 0x0095 +#define mmPIPE2_PG_ENABLE_BASE_IDX 2 +#define mmPIPE2_PG_STATUS 0x0096 +#define mmPIPE2_PG_STATUS_BASE_IDX 2 +#define mmPIPE3_PG_CONFIG 0x0097 +#define mmPIPE3_PG_CONFIG_BASE_IDX 2 +#define mmPIPE3_PG_ENABLE 0x0098 +#define mmPIPE3_PG_ENABLE_BASE_IDX 2 +#define mmPIPE3_PG_STATUS 0x0099 +#define mmPIPE3_PG_STATUS_BASE_IDX 2 +#define mmPIPE4_PG_CONFIG 0x009a +#define mmPIPE4_PG_CONFIG_BASE_IDX 2 +#define mmPIPE4_PG_ENABLE 0x009b +#define mmPIPE4_PG_ENABLE_BASE_IDX 2 +#define mmPIPE4_PG_STATUS 0x009c +#define mmPIPE4_PG_STATUS_BASE_IDX 2 +#define mmPIPE5_PG_CONFIG 0x009d +#define mmPIPE5_PG_CONFIG_BASE_IDX 2 +#define mmPIPE5_PG_ENABLE 0x009e +#define mmPIPE5_PG_ENABLE_BASE_IDX 2 +#define mmPIPE5_PG_STATUS 0x009f +#define mmPIPE5_PG_STATUS_BASE_IDX 2 +#define mmDSI_PG_CONFIG 0x00a0 +#define mmDSI_PG_CONFIG_BASE_IDX 2 +#define mmDSI_PG_ENABLE 0x00a1 +#define mmDSI_PG_ENABLE_BASE_IDX 2 +#define mmDSI_PG_STATUS 0x00a2 +#define mmDSI_PG_STATUS_BASE_IDX 2 +#define mmDCFEV0_PG_CONFIG 0x00a3 +#define mmDCFEV0_PG_CONFIG_BASE_IDX 2 +#define mmDCFEV0_PG_ENABLE 0x00a4 +#define mmDCFEV0_PG_ENABLE_BASE_IDX 2 +#define mmDCFEV0_PG_STATUS 0x00a5 +#define mmDCFEV0_PG_STATUS_BASE_IDX 2 +#define mmDCPG_INTERRUPT_STATUS 0x00a6 +#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL 0x00a7 +#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL2 0x00a8 +#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2 +#define mmDCFEV1_PG_CONFIG 0x00a9 +#define mmDCFEV1_PG_CONFIG_BASE_IDX 2 +#define mmDCFEV1_PG_ENABLE 0x00aa +#define mmDCFEV1_PG_ENABLE_BASE_IDX 2 +#define mmDCFEV1_PG_STATUS 0x00ab +#define mmDCFEV1_PG_STATUS_BASE_IDX 2 +#define mmDC_IP_REQUEST_CNTL 0x00ac +#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 +#define mmDC_PGCNTL_STATUS_REG 0x00ad +#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2 +#define mmDMIFV_STATUS 0x00c3 +#define mmDMIFV_STATUS_BASE_IDX 2 +#define mmDMIF_CONTROL 0x00c4 +#define mmDMIF_CONTROL_BASE_IDX 2 +#define mmDMIF_STATUS 0x00c5 +#define mmDMIF_STATUS_BASE_IDX 2 +#define mmDMIF_ARBITRATION_CONTROL 0x00c7 +#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8 +#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9 +#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca +#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb +#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc +#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd +#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmDMIF_P_VMID 0x00ce +#define mmDMIF_P_VMID_BASE_IDX 2 +#define mmDMIF_ADDR_CALC 0x00d1 +#define mmDMIF_ADDR_CALC_BASE_IDX 2 +#define mmDMIF_STATUS2 0x00d2 +#define mmDMIF_STATUS2_BASE_IDX 2 +#define mmPIPE0_MAX_REQUESTS 0x00d3 +#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2 +#define mmPIPE1_MAX_REQUESTS 0x00d4 +#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2 +#define mmPIPE2_MAX_REQUESTS 0x00d5 +#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2 +#define mmPIPE3_MAX_REQUESTS 0x00d6 +#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2 +#define mmPIPE4_MAX_REQUESTS 0x00d7 +#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2 +#define mmPIPE5_MAX_REQUESTS 0x00d8 +#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2 +#define mmLOW_POWER_TILING_CONTROL 0x00d9 +#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2 +#define mmMCIF_CONTROL 0x00da +#define mmMCIF_CONTROL_BASE_IDX 2 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db +#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmCC_DC_PIPE_DIS 0x00e0 +#define mmCC_DC_PIPE_DIS_BASE_IDX 2 +#define mmSMU_WM_CONTROL 0x00e1 +#define mmSMU_WM_CONTROL_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT 0x00e2 +#define mmRBBMIF_TIMEOUT_BASE_IDX 2 +#define mmRBBMIF_STATUS 0x00e3 +#define mmRBBMIF_STATUS_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT_DIS 0x00e4 +#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define mmDCI_MEM_PWR_STATUS 0x00e5 +#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCI_MEM_PWR_STATUS2 0x00e6 +#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmDCI_CLK_CNTL 0x00e7 +#define mmDCI_CLK_CNTL_BASE_IDX 2 +#define mmDCI_CLK_CNTL2 0x00e8 +#define mmDCI_CLK_CNTL2_BASE_IDX 2 +#define mmDCI_MEM_PWR_CNTL 0x00e9 +#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2 +#define mmDCI_MEM_PWR_CNTL2 0x00ea +#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2 +#define mmDCI_MEM_PWR_CNTL3 0x00eb +#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2 +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef +#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2 +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0 +#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2 +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1 +#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2 +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2 +#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2 +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3 +#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2 +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4 +#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2 +#define mmRBBMIF_STATUS_FLAG 0x00f5 +#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 +#define mmDCI_SOFT_RESET 0x00f6 +#define mmDCI_SOFT_RESET_BASE_IDX 2 +#define mmDMIF_URG_OVERRIDE 0x00f7 +#define mmDMIF_URG_OVERRIDE_BASE_IDX 2 +#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8 +#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9 +#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2 +#define mmPIPE6_MAX_REQUESTS 0x00fa +#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2 +#define mmPIPE7_MAX_REQUESTS 0x00fb +#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2 +#define mmDVMM_REG_RD_STATUS 0x00fc +#define mmDVMM_REG_RD_STATUS_BASE_IDX 2 +#define mmDVMM_REG_RD_DATA 0x00fd +#define mmDVMM_REG_RD_DATA_BASE_IDX 2 +#define mmDVMM_PTE_REQ 0x00fe +#define mmDVMM_PTE_REQ_BASE_IDX 2 +#define mmDVMM_CNTL 0x00ff +#define mmDVMM_CNTL_BASE_IDX 2 +#define mmDVMM_FAULT_STATUS 0x0100 +#define mmDVMM_FAULT_STATUS_BASE_IDX 2 +#define mmDVMM_FAULT_ADDR 0x0101 +#define mmDVMM_FAULT_ADDR_BASE_IDX 2 +#define mmFMON_CTRL 0x0102 +#define mmFMON_CTRL_BASE_IDX 2 +#define mmDVMM_PTE_PGMEM_CONTROL 0x0103 +#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2 +#define mmDVMM_PTE_PGMEM_STATE 0x0104 +#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107 +#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108 +#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmDCI_MEM_PWR_CNTL4 0x0109 +#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2 +#define mmMCIF_WB_MISC_CTRL 0x010a +#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2 +#define mmDCI_MEM_PWR_STATUS3 0x010b +#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2 +#define mmDMIF_CURSOR_CONTROL 0x010c +#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2 +#define mmDMIF_CURSOR_MEM_CONTROL 0x010d +#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2 +#define mmDCHUB_FB_LOCATION 0x0126 +#define mmDCHUB_FB_LOCATION_BASE_IDX 2 +#define mmDCHUB_FB_OFFSET 0x0127 +#define mmDCHUB_FB_OFFSET_BASE_IDX 2 +#define mmDCHUB_AGP_BASE 0x0128 +#define mmDCHUB_AGP_BASE_BASE_IDX 2 +#define mmDCHUB_AGP_BOT 0x0129 +#define mmDCHUB_AGP_BOT_BASE_IDX 2 +#define mmDCHUB_AGP_TOP 0x012a +#define mmDCHUB_AGP_TOP_BASE_IDX 2 +#define mmDCHUB_DRAM_APER_BASE 0x012b +#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2 +#define mmDCHUB_DRAM_APER_DEF 0x012c +#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2 +#define mmDCHUB_DRAM_APER_TOP 0x012d +#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2 +#define mmDCHUB_CONTROL_STATUS 0x012e +#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2 +#define mmWB_ENABLE 0x0212 +#define mmWB_ENABLE_BASE_IDX 2 +#define mmWB_EC_CONFIG 0x0213 +#define mmWB_EC_CONFIG_BASE_IDX 2 +#define mmCNV_MODE 0x0214 +#define mmCNV_MODE_BASE_IDX 2 +#define mmCNV_WINDOW_START 0x0215 +#define mmCNV_WINDOW_START_BASE_IDX 2 +#define mmCNV_WINDOW_SIZE 0x0216 +#define mmCNV_WINDOW_SIZE_BASE_IDX 2 +#define mmCNV_UPDATE 0x0217 +#define mmCNV_UPDATE_BASE_IDX 2 +#define mmCNV_SOURCE_SIZE 0x0218 +#define mmCNV_SOURCE_SIZE_BASE_IDX 2 +#define mmCNV_CSC_CONTROL 0x0219 +#define mmCNV_CSC_CONTROL_BASE_IDX 2 +#define mmCNV_CSC_C11_C12 0x021a +#define mmCNV_CSC_C11_C12_BASE_IDX 2 +#define mmCNV_CSC_C13_C14 0x021b +#define mmCNV_CSC_C13_C14_BASE_IDX 2 +#define mmCNV_CSC_C21_C22 0x021c +#define mmCNV_CSC_C21_C22_BASE_IDX 2 +#define mmCNV_CSC_C23_C24 0x021d +#define mmCNV_CSC_C23_C24_BASE_IDX 2 +#define mmCNV_CSC_C31_C32 0x021e +#define mmCNV_CSC_C31_C32_BASE_IDX 2 +#define mmCNV_CSC_C33_C34 0x021f +#define mmCNV_CSC_C33_C34_BASE_IDX 2 +#define mmCNV_CSC_ROUND_OFFSET_R 0x0220 +#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 +#define mmCNV_CSC_ROUND_OFFSET_G 0x0221 +#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 +#define mmCNV_CSC_ROUND_OFFSET_B 0x0222 +#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 +#define mmCNV_CSC_CLAMP_R 0x0223 +#define mmCNV_CSC_CLAMP_R_BASE_IDX 2 +#define mmCNV_CSC_CLAMP_G 0x0224 +#define mmCNV_CSC_CLAMP_G_BASE_IDX 2 +#define mmCNV_CSC_CLAMP_B 0x0225 +#define mmCNV_CSC_CLAMP_B_BASE_IDX 2 +#define mmCNV_TEST_CNTL 0x0226 +#define mmCNV_TEST_CNTL_BASE_IDX 2 +#define mmCNV_TEST_CRC_RED 0x0227 +#define mmCNV_TEST_CRC_RED_BASE_IDX 2 +#define mmCNV_TEST_CRC_GREEN 0x0228 +#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2 +#define mmCNV_TEST_CRC_BLUE 0x0229 +#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2 +#define mmCNV_INPUT_SELECT 0x022d +#define mmCNV_INPUT_SELECT_BASE_IDX 2 +#define mmWB_SOFT_RESET 0x0230 +#define mmWB_SOFT_RESET_BASE_IDX 2 +#define mmWB_WARM_UP_MODE_CTL1 0x0231 +#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2 +#define mmWB_WARM_UP_MODE_CTL2 0x0232 +#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2 +#define mmWBSCL_COEF_RAM_SELECT 0x0242 +#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243 +#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmWBSCL_MODE 0x0244 +#define mmWBSCL_MODE_BASE_IDX 2 +#define mmWBSCL_TAP_CONTROL 0x0245 +#define mmWBSCL_TAP_CONTROL_BASE_IDX 2 +#define mmWBSCL_DEST_SIZE 0x0246 +#define mmWBSCL_DEST_SIZE_BASE_IDX 2 +#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247 +#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248 +#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249 +#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a +#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b +#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c +#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL_ROUND_OFFSET 0x024d +#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2 +#define mmWBSCL_CLAMP 0x024e +#define mmWBSCL_CLAMP_BASE_IDX 2 +#define mmWBSCL_OVERFLOW_STATUS 0x024f +#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2 +#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250 +#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 +#define mmWBSCL_TEST_CNTL 0x0252 +#define mmWBSCL_TEST_CNTL_BASE_IDX 2 +#define mmWBSCL_TEST_CRC_RED 0x0253 +#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2 +#define mmWBSCL_TEST_CRC_GREEN 0x0254 +#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2 +#define mmWBSCL_TEST_CRC_BLUE 0x0255 +#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2 +#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256 +#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257 +#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 +#define mmWBSCL_RAM_SHUTDOWN 0x025a +#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2 +#define mmDMCU_CTRL 0x03b6 +#define mmDMCU_CTRL_BASE_IDX 2 +#define mmDMCU_STATUS 0x03b7 +#define mmDMCU_STATUS_BASE_IDX 2 +#define mmDMCU_PC_START_ADDR 0x03b8 +#define mmDMCU_PC_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_START_ADDR 0x03b9 +#define mmDMCU_FW_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_END_ADDR 0x03ba +#define mmDMCU_FW_END_ADDR_BASE_IDX 2 +#define mmDMCU_FW_ISR_START_ADDR 0x03bb +#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_CS_HI 0x03bc +#define mmDMCU_FW_CS_HI_BASE_IDX 2 +#define mmDMCU_FW_CS_LO 0x03bd +#define mmDMCU_FW_CS_LO_BASE_IDX 2 +#define mmDMCU_RAM_ACCESS_CTRL 0x03be +#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_CTRL 0x03bf +#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_DATA 0x03c0 +#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_ERAM_RD_CTRL 0x03c1 +#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_RD_DATA 0x03c2 +#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_WR_CTRL 0x03c3 +#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_WR_DATA 0x03c4 +#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_RD_CTRL 0x03c5 +#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_RD_DATA 0x03c6 +#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_EVENT_TRIGGER 0x03c7 +#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8 +#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS 0x03ca +#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 +#define mmDC_DMCU_SCRATCH 0x03ce +#define mmDC_DMCU_SCRATCH_BASE_IDX 2 +#define mmDMCU_INT_CNT 0x03cf +#define mmDMCU_INT_CNT_BASE_IDX 2 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 +#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1 +#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG1 0x03d2 +#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG2 0x03d3 +#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG3 0x03d4 +#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 +#define mmMASTER_COMM_CMD_REG 0x03d5 +#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 +#define mmMASTER_COMM_CNTL_REG 0x03d6 +#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG1 0x03d7 +#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG2 0x03d8 +#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG3 0x03d9 +#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 +#define mmSLAVE_COMM_CMD_REG 0x03da +#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 +#define mmSLAVE_COMM_CNTL_REG 0x03db +#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_USER_LEVEL 0x03df +#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0 +#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1 +#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2 +#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 +#define mmBL1_PWM_ABM_CNTL 0x03e4 +#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 +#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6 +#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_1 0x03e9 +#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea +#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDC_ABM1_CNTL 0x03ee +#define mmDC_ABM1_CNTL_BASE_IDX 2 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef +#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 +#define mmDC_ABM1_ACE_THRES_12 0x03f5 +#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2 +#define mmDC_ABM1_ACE_THRES_34 0x03f6 +#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2 +#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7 +#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa +#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb +#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc +#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd +#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 +#define mmDC_ABM1_HG_MISC_CTRL 0x0401 +#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2 +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402 +#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403 +#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 +#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405 +#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406 +#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a +#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 +#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b +#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_1 0x0411 +#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_2 0x0412 +#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_3 0x0413 +#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_4 0x0414 +#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_5 0x0415 +#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_6 0x0416 +#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_7 0x0417 +#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_8 0x0418 +#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_9 0x0419 +#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_10 0x041a +#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_11 0x041b +#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_12 0x041c +#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_13 0x041d +#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_14 0x041e +#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_15 0x041f +#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_16 0x0420 +#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_17 0x0421 +#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_18 0x0422 +#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_19 0x0423 +#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_20 0x0424 +#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_21 0x0425 +#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_22 0x0426 +#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_23 0x0427 +#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_24 0x0428 +#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2 +#define mmDC_ABM1_BL_MASTER_LOCK 0x0452 +#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc +#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO 0x04bd +#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be +#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define mmAZALIA_SOCCLK_CONTROL 0x04bf +#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define mmAZALIA_DATA_DMA_CONTROL 0x04c1 +#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_BDL_DMA_CONTROL 0x04c2 +#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3 +#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define mmAZALIA_CORB_DMA_CONTROL 0x04c4 +#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc +#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd +#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3 +#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4 +#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5 +#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6 +#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7 +#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8 +#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9 +#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da +#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db +#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc +#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL0 0x04dd +#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL1 0x04de +#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL2 0x04df +#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL3 0x04e0 +#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC0_RESULT 0x04e1 +#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL0 0x04e2 +#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL1 0x04e3 +#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL2 0x04e4 +#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL3 0x04e5 +#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC1_RESULT 0x04e6 +#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_CTRL 0x04e8 +#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_STATUS 0x04e9 +#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f +#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmDAC_ENABLE 0x155a +#define mmDAC_ENABLE_BASE_IDX 2 +#define mmDAC_SOURCE_SELECT 0x155b +#define mmDAC_SOURCE_SELECT_BASE_IDX 2 +#define mmDAC_CRC_EN 0x155c +#define mmDAC_CRC_EN_BASE_IDX 2 +#define mmDAC_CRC_CONTROL 0x155d +#define mmDAC_CRC_CONTROL_BASE_IDX 2 +#define mmDAC_CRC_SIG_RGB_MASK 0x155e +#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2 +#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f +#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2 +#define mmDAC_CRC_SIG_RGB 0x1560 +#define mmDAC_CRC_SIG_RGB_BASE_IDX 2 +#define mmDAC_CRC_SIG_CONTROL 0x1561 +#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2 +#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562 +#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2 +#define mmDAC_STEREOSYNC_SELECT 0x1563 +#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2 +#define mmDAC_AUTODETECT_CONTROL 0x1564 +#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2 +#define mmDAC_AUTODETECT_CONTROL2 0x1565 +#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2 +#define mmDAC_AUTODETECT_CONTROL3 0x1566 +#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2 +#define mmDAC_AUTODETECT_STATUS 0x1567 +#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2 +#define mmDAC_AUTODETECT_INT_CONTROL 0x1568 +#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2 +#define mmDAC_FORCE_OUTPUT_CNTL 0x1569 +#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2 +#define mmDAC_FORCE_DATA 0x156a +#define mmDAC_FORCE_DATA_BASE_IDX 2 +#define mmDAC_POWERDOWN 0x156b +#define mmDAC_POWERDOWN_BASE_IDX 2 +#define mmDAC_CONTROL 0x156c +#define mmDAC_CONTROL_BASE_IDX 2 +#define mmDAC_COMPARATOR_ENABLE 0x156d +#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2 +#define mmDAC_COMPARATOR_OUTPUT 0x156e +#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2 +#define mmDAC_PWR_CNTL 0x156f +#define mmDAC_PWR_CNTL_BASE_IDX 2 +#define mmDAC_DFT_CONFIG 0x1570 +#define mmDAC_DFT_CONFIG_BASE_IDX 2 +#define mmDAC_FIFO_STATUS 0x1571 +#define mmDAC_FIFO_STATUS_BASE_IDX 2 +#define mmDC_I2C_CONTROL 0x1584 +#define mmDC_I2C_CONTROL_BASE_IDX 2 +#define mmDC_I2C_ARBITRATION 0x1585 +#define mmDC_I2C_ARBITRATION_BASE_IDX 2 +#define mmDC_I2C_INTERRUPT_CONTROL 0x1586 +#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDC_I2C_SW_STATUS 0x1587 +#define mmDC_I2C_SW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_HW_STATUS 0x1588 +#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC2_HW_STATUS 0x1589 +#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC3_HW_STATUS 0x158a +#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC4_HW_STATUS 0x158b +#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC5_HW_STATUS 0x158c +#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC6_HW_STATUS 0x158d +#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_SPEED 0x158e +#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC1_SETUP 0x158f +#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC2_SPEED 0x1590 +#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC2_SETUP 0x1591 +#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC3_SPEED 0x1592 +#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC3_SETUP 0x1593 +#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC4_SPEED 0x1594 +#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC4_SETUP 0x1595 +#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC5_SPEED 0x1596 +#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC5_SETUP 0x1597 +#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC6_SPEED 0x1598 +#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC6_SETUP 0x1599 +#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION0 0x159a +#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION1 0x159b +#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION2 0x159c +#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION3 0x159d +#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 +#define mmDC_I2C_DATA 0x159e +#define mmDC_I2C_DATA_BASE_IDX 2 +#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f +#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDCVGA_SPEED 0x15a0 +#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDCVGA_SETUP 0x15a1 +#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2 +#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2 +#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3 +#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 +#define mmGENERIC_I2C_CONTROL 0x15a4 +#define mmGENERIC_I2C_CONTROL_BASE_IDX 2 +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5 +#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmGENERIC_I2C_STATUS 0x15a6 +#define mmGENERIC_I2C_STATUS_BASE_IDX 2 +#define mmGENERIC_I2C_SPEED 0x15a7 +#define mmGENERIC_I2C_SPEED_BASE_IDX 2 +#define mmGENERIC_I2C_SETUP 0x15a8 +#define mmGENERIC_I2C_SETUP_BASE_IDX 2 +#define mmGENERIC_I2C_TRANSACTION 0x15a9 +#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2 +#define mmGENERIC_I2C_DATA 0x15aa +#define mmGENERIC_I2C_DATA_BASE_IDX 2 +#define mmGENERIC_I2C_PIN_SELECTION 0x15ab +#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2 +#define mmDCO_SCRATCH0 0x15b6 +#define mmDCO_SCRATCH0_BASE_IDX 2 +#define mmDCO_SCRATCH1 0x15b7 +#define mmDCO_SCRATCH1_BASE_IDX 2 +#define mmDCO_SCRATCH2 0x15b8 +#define mmDCO_SCRATCH2_BASE_IDX 2 +#define mmDCO_SCRATCH3 0x15b9 +#define mmDCO_SCRATCH3_BASE_IDX 2 +#define mmDCO_SCRATCH4 0x15ba +#define mmDCO_SCRATCH4_BASE_IDX 2 +#define mmDCO_SCRATCH5 0x15bb +#define mmDCO_SCRATCH5_BASE_IDX 2 +#define mmDCO_SCRATCH6 0x15bc +#define mmDCO_SCRATCH6_BASE_IDX 2 +#define mmDCO_SCRATCH7 0x15bd +#define mmDCO_SCRATCH7_BASE_IDX 2 +#define mmDCE_VCE_CONTROL 0x15be +#define mmDCE_VCE_CONTROL_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS 0x15bf +#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0 +#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define mmDCO_MEM_PWR_STATUS 0x15c9 +#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCO_MEM_PWR_CTRL 0x15ca +#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCO_MEM_PWR_CTRL2 0x15cb +#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCO_CLK_CNTL 0x15cc +#define mmDCO_CLK_CNTL_BASE_IDX 2 +#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0 +#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define mmDIG_SOFT_RESET_2 0x15d2 +#define mmDIG_SOFT_RESET_2_BASE_IDX 2 +#define mmDCO_STEREOSYNC_SEL 0x15d6 +#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2 +#define mmDCO_SOFT_RESET 0x15d9 +#define mmDCO_SOFT_RESET_BASE_IDX 2 +#define mmDIG_SOFT_RESET 0x15da +#define mmDIG_SOFT_RESET_BASE_IDX 2 +#define mmDCO_MEM_PWR_STATUS1 0x15dc +#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd +#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define mmDCO_CLK_CNTL2 0x15de +#define mmDCO_CLK_CNTL2_BASE_IDX 2 +#define mmDCO_CLK_CNTL3 0x15df +#define mmDCO_CLK_CNTL3_BASE_IDX 2 +#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb +#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec +#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed +#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 +#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee +#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 +#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef +#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 +#define mmFMT_MEMORY0_CONTROL 0x15f0 +#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2 +#define mmFMT_MEMORY1_CONTROL 0x15f1 +#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2 +#define mmFMT_MEMORY2_CONTROL 0x15f2 +#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2 +#define mmFMT_MEMORY3_CONTROL 0x15f3 +#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2 +#define mmFMT_MEMORY4_CONTROL 0x15f4 +#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2 +#define mmFMT_MEMORY5_CONTROL 0x15f5 +#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define mmDC_GENERICA 0x207e +#define mmDC_GENERICA_BASE_IDX 2 +#define mmDC_GENERICB 0x207f +#define mmDC_GENERICB_BASE_IDX 2 +#define mmDC_PAD_EXTERN_SIG 0x2080 +#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2 +#define mmDC_REF_CLK_CNTL 0x2081 +#define mmDC_REF_CLK_CNTL_BASE_IDX 2 +#define mmDC_GPIO_DEBUG 0x2082 +#define mmDC_GPIO_DEBUG_BASE_IDX 2 +#define mmUNIPHYA_LINK_CNTL 0x2083 +#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYB_LINK_CNTL 0x2085 +#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYC_LINK_CNTL 0x2087 +#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYD_LINK_CNTL 0x2089 +#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a +#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYE_LINK_CNTL 0x208b +#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c +#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYF_LINK_CNTL 0x208d +#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e +#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYG_LINK_CNTL 0x208f +#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmDCIO_WRCMD_DELAY 0x2094 +#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 +#define mmDC_DVODATA_CONFIG 0x2098 +#define mmDC_DVODATA_CONFIG_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_CNTL 0x2099 +#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_STATE 0x209a +#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_REF_DIV 0x209b +#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY1 0x209c +#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY2 0x209d +#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 +#define mmBL_PWM_CNTL 0x209e +#define mmBL_PWM_CNTL_BASE_IDX 2 +#define mmBL_PWM_CNTL2 0x209f +#define mmBL_PWM_CNTL2_BASE_IDX 2 +#define mmBL_PWM_PERIOD_CNTL 0x20a0 +#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define mmBL_PWM_GRP1_REG_LOCK 0x20a1 +#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2 +#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_GSL0_CNTL 0x20a4 +#define mmDCIO_GSL0_CNTL_BASE_IDX 2 +#define mmDCIO_GSL1_CNTL 0x20a5 +#define mmDCIO_GSL1_CNTL_BASE_IDX 2 +#define mmDCIO_GSL2_CNTL 0x20a6 +#define mmDCIO_GSL2_CNTL_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ 0x20a9 +#define mmDC_GPU_TIMER_READ_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ_CNTL 0x20aa +#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define mmDCIO_CLOCK_CNTL 0x20ab +#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 +#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae +#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2 +#define mmDCIO_SOFT_RESET 0x20b4 +#define mmDCIO_SOFT_RESET_BASE_IDX 2 +#define mmDCIO_DPHY_SEL 0x20b5 +#define mmDCIO_DPHY_SEL_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKA 0x20b6 +#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKB 0x20b7 +#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PERIOD 0x20b8 +#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2 +#define mmAUXP_IMPCAL 0x20b9 +#define mmAUXP_IMPCAL_BASE_IDX 2 +#define mmAUXN_IMPCAL 0x20ba +#define mmAUXN_IMPCAL_BASE_IDX 2 +#define mmDCIO_IMPCAL_CNTL 0x20bb +#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc +#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKC 0x20bd +#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKD 0x20be +#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2 +#define mmDCIO_IMPCAL_CNTL_CD 0x20bf +#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0 +#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKE 0x20c1 +#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_LINKF 0x20c2 +#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2 +#define mmDCIO_IMPCAL_CNTL_EF 0x20c3 +#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2 +#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4 +#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2 +#define mmUNIPHYLPA_LINK_CNTL 0x20c5 +#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYLPB_LINK_CNTL 0x20c6 +#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7 +#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8 +#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9 +#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2 +#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca +#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2 +#define mmDCIO_SEMAPHORE0 0x20cb +#define mmDCIO_SEMAPHORE0_BASE_IDX 2 +#define mmDCIO_SEMAPHORE1 0x20cc +#define mmDCIO_SEMAPHORE1_BASE_IDX 2 +#define mmDCIO_SEMAPHORE2 0x20cd +#define mmDCIO_SEMAPHORE2_BASE_IDX 2 +#define mmDCIO_SEMAPHORE3 0x20ce +#define mmDCIO_SEMAPHORE3_BASE_IDX 2 +#define mmDCIO_SEMAPHORE4 0x20cf +#define mmDCIO_SEMAPHORE4_BASE_IDX 2 +#define mmDCIO_SEMAPHORE5 0x20d0 +#define mmDCIO_SEMAPHORE5_BASE_IDX 2 +#define mmDCIO_SEMAPHORE6 0x20d1 +#define mmDCIO_SEMAPHORE6_BASE_IDX 2 +#define mmDCIO_SEMAPHORE7 0x20d2 +#define mmDCIO_SEMAPHORE7_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_MASK 0x20de +#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_A 0x20df +#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_EN 0x20e0 +#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_Y 0x20e1 +#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_MASK 0x20e2 +#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_A 0x20e3 +#define mmDC_GPIO_DVODATA_A_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_EN 0x20e4 +#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2 +#define mmDC_GPIO_DVODATA_Y 0x20e5 +#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC1_MASK 0x20e6 +#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC1_A 0x20e7 +#define mmDC_GPIO_DDC1_A_BASE_IDX 2 +#define mmDC_GPIO_DDC1_EN 0x20e8 +#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC1_Y 0x20e9 +#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC2_MASK 0x20ea +#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC2_A 0x20eb +#define mmDC_GPIO_DDC2_A_BASE_IDX 2 +#define mmDC_GPIO_DDC2_EN 0x20ec +#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC2_Y 0x20ed +#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC3_MASK 0x20ee +#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC3_A 0x20ef +#define mmDC_GPIO_DDC3_A_BASE_IDX 2 +#define mmDC_GPIO_DDC3_EN 0x20f0 +#define mmDC_GPIO_DDC3_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC3_Y 0x20f1 +#define mmDC_GPIO_DDC3_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC4_MASK 0x20f2 +#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC4_A 0x20f3 +#define mmDC_GPIO_DDC4_A_BASE_IDX 2 +#define mmDC_GPIO_DDC4_EN 0x20f4 +#define mmDC_GPIO_DDC4_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC4_Y 0x20f5 +#define mmDC_GPIO_DDC4_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC5_MASK 0x20f6 +#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC5_A 0x20f7 +#define mmDC_GPIO_DDC5_A_BASE_IDX 2 +#define mmDC_GPIO_DDC5_EN 0x20f8 +#define mmDC_GPIO_DDC5_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC5_Y 0x20f9 +#define mmDC_GPIO_DDC5_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC6_MASK 0x20fa +#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC6_A 0x20fb +#define mmDC_GPIO_DDC6_A_BASE_IDX 2 +#define mmDC_GPIO_DDC6_EN 0x20fc +#define mmDC_GPIO_DDC6_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC6_Y 0x20fd +#define mmDC_GPIO_DDC6_Y_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_MASK 0x20fe +#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_A 0x20ff +#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_EN 0x2100 +#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_Y 0x2101 +#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_MASK 0x2102 +#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_A 0x2103 +#define mmDC_GPIO_SYNCA_A_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_EN 0x2104 +#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2 +#define mmDC_GPIO_SYNCA_Y 0x2105 +#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2 +#define mmDC_GPIO_GENLK_MASK 0x2106 +#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENLK_A 0x2107 +#define mmDC_GPIO_GENLK_A_BASE_IDX 2 +#define mmDC_GPIO_GENLK_EN 0x2108 +#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 +#define mmDC_GPIO_GENLK_Y 0x2109 +#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 +#define mmDC_GPIO_HPD_MASK 0x210a +#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 +#define mmDC_GPIO_HPD_A 0x210b +#define mmDC_GPIO_HPD_A_BASE_IDX 2 +#define mmDC_GPIO_HPD_EN 0x210c +#define mmDC_GPIO_HPD_EN_BASE_IDX 2 +#define mmDC_GPIO_HPD_Y 0x210d +#define mmDC_GPIO_HPD_Y_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_MASK 0x210e +#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_A 0x210f +#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_EN 0x2110 +#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_Y 0x2111 +#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_1 0x2112 +#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_2 0x2113 +#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define mmPHY_AUX_CNTL 0x2115 +#define mmPHY_AUX_CNTL_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_MASK 0x2116 +#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_A 0x2117 +#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_EN 0x2118 +#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_Y 0x2119 +#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a +#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2 +#define mmDVO_STRENGTH_CONTROL 0x211b +#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2 +#define mmDVO_VREF_CONTROL 0x211c +#define mmDVO_VREF_CONTROL_BASE_IDX 2 +#define mmDVO_SKEW_ADJUST 0x211d +#define mmDVO_SKEW_ADJUST_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126 +#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_A 0x2127 +#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_EN 0x2128 +#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_Y 0x2129 +#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2 +#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a +#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2 +#define mmDC_GPIO_TX12_EN 0x212b +#define mmDC_GPIO_TX12_EN_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_0 0x212c +#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_1 0x212d +#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_2 0x212e +#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define mmDC_GPIO_RXEN 0x212f +#define mmDC_GPIO_RXEN_BASE_IDX 2 +#define mmBPHYC_DAC_MACRO_CNTL 0x2136 +#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED0 0x2136 +#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED1 0x2137 +#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED2 0x2138 +#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDAC_MACRO_CNTL_RESERVED3 0x2139 +#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDISP_DSI_DUAL_CTRL 0x277e +#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e +#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f +#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840 +#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841 +#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842 +#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843 +#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844 +#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845 +#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846 +#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847 +#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848 +#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849 +#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a +#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b +#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c +#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d +#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e +#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f +#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850 +#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851 +#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852 +#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853 +#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854 +#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855 +#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856 +#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857 +#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858 +#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859 +#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a +#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b +#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c +#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d +#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e +#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f +#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860 +#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861 +#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862 +#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863 +#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864 +#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865 +#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866 +#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867 +#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868 +#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869 +#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a +#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b +#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c +#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d +#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e +#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f +#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870 +#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871 +#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872 +#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873 +#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874 +#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875 +#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876 +#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877 +#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878 +#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879 +#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a +#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b +#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c +#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d +#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e +#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2 +#define mmDPRX_AUX_CONTROL 0x2a7f +#define mmDPRX_AUX_CONTROL_BASE_IDX 2 +#define mmDPRX_AUX_HPD_CONTROL1 0x2a80 +#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2 +#define mmDPRX_AUX_HPD_CONTROL2 0x2a81 +#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2 +#define mmDPRX_AUX_RX_STATUS 0x2a82 +#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2 +#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83 +#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2 +#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84 +#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85 +#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86 +#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87 +#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88 +#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89 +#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a +#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2 +#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b +#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2 +#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c +#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2 +#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d +#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2 +#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e +#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2 +#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f +#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2 +#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90 +#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2 +#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91 +#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2 +#define mmDPRX_AUX_EDID_INDEX 0x2a92 +#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2 +#define mmDPRX_AUX_EDID_DATA 0x2a93 +#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2 +#define mmDPRX_AUX_DPCD_INDEX1 0x2a94 +#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2 +#define mmDPRX_AUX_DPCD_DATA1 0x2a95 +#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2 +#define mmDPRX_AUX_DPCD_INDEX2 0x2a96 +#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2 +#define mmDPRX_AUX_DPCD_DATA2 0x2a97 +#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2 +#define mmDPRX_AUX_MSG_INDEX1 0x2a98 +#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2 +#define mmDPRX_AUX_MSG_DATA1 0x2a99 +#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2 +#define mmDPRX_AUX_MSG_INDEX2 0x2a9a +#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2 +#define mmDPRX_AUX_MSG_DATA2 0x2a9b +#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2 +#define mmDPRX_AUX_KSV_INDEX1 0x2a9c +#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2 +#define mmDPRX_AUX_KSV_DATA1 0x2a9d +#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2 +#define mmDPRX_AUX_KSV_INDEX2 0x2a9e +#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2 +#define mmDPRX_AUX_KSV_DATA2 0x2a9f +#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2 +#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0 +#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2 +#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1 +#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2 +#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2 +#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2 +#define mmDPRX_AUX_SCRATCH1 0x2aa3 +#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2 +#define mmDPRX_AUX_SCRATCH2 0x2aa4 +#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2 +#define mmDPRX_AUX_MSG1_PENDING 0x2aa5 +#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2 +#define mmDPRX_AUX_MSG2_PENDING 0x2aa6 +#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2 +#define mmDPRX_AUX_MSG3_PENDING 0x2aa7 +#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2 +#define mmDPRX_AUX_MSG4_PENDING 0x2aa8 +#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe +#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff +#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00 +#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08 +#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_READY 0x2b09 +#define mmDPRX_DPHY_READY_BASE_IDX 2 +#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b +#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c +#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2 +#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d +#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e +#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20 +#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21 +#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22 +#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2 +#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24 +#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2 +#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25 +#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2 +#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27 +#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2 +#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28 +#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2 +#define mmDPRX_DPHY_LANESETUP0 0x2b2d +#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2 +#define mmDPRX_DPHY_LANESETUP1 0x2b2e +#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2 +#define mmDPRX_DPHY_LFSRADV 0x2b31 +#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2 +#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32 +#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2 +#define mmDPRX_DPHY_SET_ENABLE 0x2b33 +#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2 +#define mmDPRX_DPHY_ECF_LSB 0x2b34 +#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2 +#define mmDPRX_DPHY_ECF_MSB 0x2b35 +#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2 +#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36 +#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2 +#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c +#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2 +#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d +#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2 +#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e +#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2 +#define mmDPRX_DPHY_BYPASS 0x2b3f +#define mmDPRX_DPHY_BYPASS_BASE_IDX 2 +#define mmDPRX_DPHY_INT_RESET 0x2b40 +#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2 +#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41 +#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43 +#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44 +#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46 +#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48 +#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49 +#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a +#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b +#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c +#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2 +#define mmDPRX_DPHY_SPARE 0x2b4d +#define mmDPRX_DPHY_SPARE_BASE_IDX 2 +#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e +#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2 +#define mmDCRX_SOFT_RESET 0x2b6f +#define mmDCRX_SOFT_RESET_BASE_IDX 2 +#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70 +#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2 +#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73 +#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2 +#define mmDCRX_CLK_CNTL 0x2b74 +#define mmDCRX_CLK_CNTL_BASE_IDX 2 +#define mmDCRX_TEST_CLK_CNTL 0x2b75 +#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce +#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda +#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde +#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced +#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff +#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2 +#define mmI2S0_CNTL 0x2d82 +#define mmI2S0_CNTL_BASE_IDX 2 +#define mmSPDIF0_CNTL 0x2d83 +#define mmSPDIF0_CNTL_BASE_IDX 2 +#define mmI2S1_CNTL 0x2d84 +#define mmI2S1_CNTL_BASE_IDX 2 +#define mmSPDIF1_CNTL 0x2d85 +#define mmSPDIF1_CNTL_BASE_IDX 2 +#define mmI2S0_STATUS 0x2d86 +#define mmI2S0_STATUS_BASE_IDX 2 +#define mmI2S1_STATUS 0x2d87 +#define mmI2S1_STATUS_BASE_IDX 2 +#define mmI2S0_CRC_TEST_CNTL 0x2d8a +#define mmI2S0_CRC_TEST_CNTL_BASE_IDX 2 +#define mmI2S0_CRC_TEST_DATA_01 0x2d8b +#define mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2 +#define mmI2S0_CRC_TEST_DATA_23 0x2d8c +#define mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2 +#define mmI2S1_CRC_TEST_CNTL 0x2d8d +#define mmI2S1_CRC_TEST_CNTL_BASE_IDX 2 +#define mmI2S1_CRC_TEST_DATA_0 0x2d8e +#define mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2 +#define mmSPDIF0_CRC_TEST_CNTL 0x2d8f +#define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2 +#define mmSPDIF0_CRC_TEST_DATA_0 0x2d90 +#define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2 +#define mmSPDIF1_CRC_TEST_CNTL 0x2d91 +#define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2 +#define mmSPDIF1_CRC_TEST_DATA 0x2d92 +#define mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2 +#define mmCRC_I2S_CONT_REPEAT_NUM 0x2d93 +#define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2 +#define mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94 +#define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED0 0x2d96 +#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED1 0x2d97 +#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED2 0x2d98 +#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED3 0x2d99 +#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a +#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream0_dispdec +// base address: 0x0 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream1_dispdec +// base address: 0x8 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b +#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream2_dispdec +// base address: 0x10 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d +#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream3_dispdec +// base address: 0x18 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f +#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream4_dispdec +// base address: 0x20 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream5_dispdec +// base address: 0x28 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream6_dispdec +// base address: 0x30 +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464 +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream7_dispdec +// base address: 0x38 +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466 +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint0_dispdec +// base address: 0x0 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint1_dispdec +// base address: 0x18 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint2_dispdec +// base address: 0x30 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint3_dispdec +// base address: 0x48 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint4_dispdec +// base address: 0x60 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint5_dispdec +// base address: 0x78 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint6_dispdec +// base address: 0x90 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0endpoint7_dispdec +// base address: 0xa8 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream8_dispdec +// base address: 0x320 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream9_dispdec +// base address: 0x328 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream10_dispdec +// base address: 0x330 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream11_dispdec +// base address: 0x338 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream12_dispdec +// base address: 0x340 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream13_dispdec +// base address: 0x348 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b +#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream14_dispdec +// base address: 0x350 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d +#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0stream15_dispdec +// base address: 0x358 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f +#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint0_dispdec +// base address: 0x0 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint1_dispdec +// base address: 0x10 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint2_dispdec +// base address: 0x20 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint3_dispdec +// base address: 0x30 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint4_dispdec +// base address: 0x40 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint5_dispdec +// base address: 0x50 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint6_dispdec +// base address: 0x60 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_azf0inputendpoint7_dispdec +// base address: 0x70 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcp0_dispdec +// base address: 0x0 +#define mmDCP0_GRPH_ENABLE 0x055a +#define mmDCP0_GRPH_ENABLE_BASE_IDX 2 +#define mmDCP0_GRPH_CONTROL 0x055b +#define mmDCP0_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c +#define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 +#define mmDCP0_GRPH_SWAP_CNTL 0x055d +#define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP0_GRPH_PITCH 0x0560 +#define mmDCP0_GRPH_PITCH_BASE_IDX 2 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563 +#define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 +#define mmDCP0_GRPH_X_START 0x0565 +#define mmDCP0_GRPH_X_START_BASE_IDX 2 +#define mmDCP0_GRPH_Y_START 0x0566 +#define mmDCP0_GRPH_Y_START_BASE_IDX 2 +#define mmDCP0_GRPH_X_END 0x0567 +#define mmDCP0_GRPH_X_END_BASE_IDX 2 +#define mmDCP0_GRPH_Y_END 0x0568 +#define mmDCP0_GRPH_Y_END_BASE_IDX 2 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x0569 +#define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_UPDATE 0x056a +#define mmDCP0_GRPH_UPDATE_BASE_IDX 2 +#define mmDCP0_GRPH_FLIP_CONTROL 0x056b +#define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 +#define mmDCP0_GRPH_DFQ_CONTROL 0x056d +#define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_DFQ_STATUS 0x056e +#define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x056f +#define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570 +#define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP0_GRPH_COMPRESS_PITCH 0x0573 +#define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575 +#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x0576 +#define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577 +#define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578 +#define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579 +#define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_CONTROL 0x057a +#define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_C11_C12 0x057b +#define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_C13_C14 0x057c +#define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_C21_C22 0x057d +#define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_C23_C24 0x057e +#define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_C31_C32 0x057f +#define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP0_INPUT_CSC_C33_C34 0x0580 +#define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_CONTROL 0x0581 +#define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_C11_C12 0x0582 +#define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_C13_C14 0x0583 +#define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_C21_C22 0x0584 +#define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_C23_C24 0x0585 +#define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x0586 +#define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x0587 +#define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590 +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591 +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592 +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593 +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP0_DENORM_CONTROL 0x0594 +#define mmDCP0_DENORM_CONTROL_BASE_IDX 2 +#define mmDCP0_OUT_ROUND_CONTROL 0x0595 +#define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2 +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596 +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597 +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598 +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 +#define mmDCP0_KEY_CONTROL 0x0599 +#define mmDCP0_KEY_CONTROL_BASE_IDX 2 +#define mmDCP0_KEY_RANGE_ALPHA 0x059a +#define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2 +#define mmDCP0_KEY_RANGE_RED 0x059b +#define mmDCP0_KEY_RANGE_RED_BASE_IDX 2 +#define mmDCP0_KEY_RANGE_GREEN 0x059c +#define mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2 +#define mmDCP0_KEY_RANGE_BLUE 0x059d +#define mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2 +#define mmDCP0_DEGAMMA_CONTROL 0x059e +#define mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_CONTROL 0x059f +#define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_C11_C12 0x05a0 +#define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_C13_C14 0x05a1 +#define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_C21_C22 0x05a2 +#define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_C23_C24 0x05a3 +#define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_C31_C32 0x05a4 +#define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmDCP0_GAMUT_REMAP_C33_C34 0x05a5 +#define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 +#define mmDCP0_DCP_RANDOM_SEEDS 0x05a7 +#define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8 +#define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmDCP0_CUR_CONTROL 0x05a9 +#define mmDCP0_CUR_CONTROL_BASE_IDX 2 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x05aa +#define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP0_CUR_SIZE 0x05ab +#define mmDCP0_CUR_SIZE_BASE_IDX 2 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP0_CUR_POSITION 0x05ad +#define mmDCP0_CUR_POSITION_BASE_IDX 2 +#define mmDCP0_CUR_HOT_SPOT 0x05ae +#define mmDCP0_CUR_HOT_SPOT_BASE_IDX 2 +#define mmDCP0_CUR_COLOR1 0x05af +#define mmDCP0_CUR_COLOR1_BASE_IDX 2 +#define mmDCP0_CUR_COLOR2 0x05b0 +#define mmDCP0_CUR_COLOR2_BASE_IDX 2 +#define mmDCP0_CUR_UPDATE 0x05b1 +#define mmDCP0_CUR_UPDATE_BASE_IDX 2 +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb +#define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 +#define mmDCP0_CUR_STEREO_CONTROL 0x05bc +#define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2 +#define mmDCP0_DC_LUT_RW_MODE 0x05be +#define mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2 +#define mmDCP0_DC_LUT_RW_INDEX 0x05bf +#define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2 +#define mmDCP0_DC_LUT_SEQ_COLOR 0x05c0 +#define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmDCP0_DC_LUT_PWL_DATA 0x05c1 +#define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2 +#define mmDCP0_DC_LUT_30_COLOR 0x05c2 +#define mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2 +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3 +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4 +#define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP0_DC_LUT_AUTOFILL 0x05c5 +#define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2 +#define mmDCP0_DC_LUT_CONTROL 0x05c6 +#define mmDCP0_DC_LUT_CONTROL_BASE_IDX 2 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 +#define mmDCP0_DCP_CRC_CONTROL 0x05cd +#define mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2 +#define mmDCP0_DCP_CRC_MASK 0x05ce +#define mmDCP0_DCP_CRC_MASK_BASE_IDX 2 +#define mmDCP0_DCP_CRC_CURRENT 0x05cf +#define mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2 +#define mmDCP0_DVMM_PTE_CONTROL 0x05d0 +#define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmDCP0_DCP_CRC_LAST 0x05d1 +#define mmDCP0_DCP_CRC_LAST_BASE_IDX 2 +#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2 +#define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4 +#define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 +#define mmDCP0_DCP_GSL_CONTROL 0x05d5 +#define mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc +#define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmDCP0_HW_ROTATION 0x05de +#define mmDCP0_HW_ROTATION_BASE_IDX 2 +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 +#define mmDCP0_REGAMMA_CONTROL 0x05e0 +#define mmDCP0_REGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP0_REGAMMA_LUT_INDEX 0x05e1 +#define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmDCP0_REGAMMA_LUT_DATA 0x05e2 +#define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmDCP0_ALPHA_CONTROL 0x05fc +#define mmDCP0_ALPHA_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 +#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600 +#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 +#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601 +#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 +#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602 +#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 +#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603 +#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 + + +// addressBlock: dce_dc_lb0_dispdec +// base address: 0x0 +#define mmLB0_LB_DATA_FORMAT 0x061a +#define mmLB0_LB_DATA_FORMAT_BASE_IDX 2 +#define mmLB0_LB_MEMORY_CTRL 0x061b +#define mmLB0_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmLB0_LB_MEMORY_SIZE_STATUS 0x061c +#define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLB0_LB_DESKTOP_HEIGHT 0x061d +#define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLB0_LB_VLINE_START_END 0x061e +#define mmLB0_LB_VLINE_START_END_BASE_IDX 2 +#define mmLB0_LB_VLINE2_START_END 0x061f +#define mmLB0_LB_VLINE2_START_END_BASE_IDX 2 +#define mmLB0_LB_V_COUNTER 0x0620 +#define mmLB0_LB_V_COUNTER_BASE_IDX 2 +#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621 +#define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLB0_LB_INTERRUPT_MASK 0x0622 +#define mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2 +#define mmLB0_LB_VLINE_STATUS 0x0623 +#define mmLB0_LB_VLINE_STATUS_BASE_IDX 2 +#define mmLB0_LB_VLINE2_STATUS 0x0624 +#define mmLB0_LB_VLINE2_STATUS_BASE_IDX 2 +#define mmLB0_LB_VBLANK_STATUS 0x0625 +#define mmLB0_LB_VBLANK_STATUS_BASE_IDX 2 +#define mmLB0_LB_SYNC_RESET_SEL 0x0626 +#define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLB0_LB_BLACK_KEYER_R_CR 0x0627 +#define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLB0_LB_BLACK_KEYER_G_Y 0x0628 +#define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLB0_LB_BLACK_KEYER_B_CB 0x0629 +#define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_CTRL 0x062a +#define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_R_CR 0x062b +#define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_G_Y 0x062c +#define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_B_CB 0x062d +#define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e +#define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f +#define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631 +#define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632 +#define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633 +#define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLB0_LB_BUFFER_STATUS 0x0634 +#define mmLB0_LB_BUFFER_STATUS_BASE_IDX 2 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 +#define mmLB0_MVP_AFR_FLIP_MODE 0x0636 +#define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 +#define mmLB0_DC_MVP_LB_CONTROL 0x0639 +#define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfe0_dispdec +// base address: 0x0 +#define mmDCFE0_DCFE_CLOCK_CONTROL 0x065a +#define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFE0_DCFE_SOFT_RESET 0x065b +#define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2 +#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d +#define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e +#define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f +#define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFE0_DCFE_MISC 0x0660 +#define mmDCFE0_DCFE_MISC_BASE_IDX 2 +#define mmDCFE0_DCFE_FLUSH 0x0661 +#define mmDCFE0_DCFE_FLUSH_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon3_dispdec +// base address: 0x1938 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e +#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670 +#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL 0x0671 +#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL2 0x0672 +#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_HI 0x0675 +#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_LOW 0x0676 +#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmif_pg0_dispdec +// base address: 0x0 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e +#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681 +#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682 +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686 +#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIF_PG0_DPG_DVMM_STATUS 0x0687 +#define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_scl0_dispdec +// base address: 0x0 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x069a +#define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b +#define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCL0_SCL_MODE 0x069c +#define mmSCL0_SCL_MODE_BASE_IDX 2 +#define mmSCL0_SCL_TAP_CONTROL 0x069d +#define mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_CONTROL 0x069e +#define mmSCL0_SCL_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_BYPASS_CONTROL 0x069f +#define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4 +#define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5 +#define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL0_SCL_VERT_FILTER_INIT 0x06a7 +#define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCL0_SCL_ROUND_OFFSET 0x06a9 +#define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2 +#define mmSCL0_SCL_UPDATE 0x06aa +#define mmSCL0_SCL_UPDATE_BASE_IDX 2 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x06ab +#define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_ALU_CONTROL 0x06ac +#define mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmSCL0_VIEWPORT_START_SECONDARY 0x06ae +#define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCL0_VIEWPORT_START 0x06af +#define mmSCL0_VIEWPORT_START_BASE_IDX 2 +#define mmSCL0_VIEWPORT_SIZE 0x06b0 +#define mmSCL0_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2 +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3 +#define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4 +#define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5 +#define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6 +#define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2 + + +// addressBlock: dce_dc_blnd0_dispdec +// base address: 0x0 +#define mmBLND0_BLND_CONTROL 0x06c7 +#define mmBLND0_BLND_CONTROL_BASE_IDX 2 +#define mmBLND0_BLND_SM_CONTROL2 0x06c8 +#define mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2 +#define mmBLND0_BLND_CONTROL2 0x06c9 +#define mmBLND0_BLND_CONTROL2_BASE_IDX 2 +#define mmBLND0_BLND_UPDATE 0x06ca +#define mmBLND0_BLND_UPDATE_BASE_IDX 2 +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLND0_BLND_V_UPDATE_LOCK 0x06cc +#define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd +#define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtc0_dispdec +// base address: 0x0 +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2 +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTC0_CRTC_H_TOTAL 0x06d3 +#define mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2 +#define mmCRTC0_CRTC_H_BLANK_START_END 0x06d4 +#define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTC0_CRTC_H_SYNC_A 0x06d5 +#define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_H_SYNC_B 0x06d7 +#define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_VBI_END 0x06d9 +#define mmCRTC0_CRTC_VBI_END_BASE_IDX 2 +#define mmCRTC0_CRTC_V_TOTAL 0x06da +#define mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x06db +#define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc +#define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd +#define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_V_BLANK_START_END 0x06e0 +#define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTC0_CRTC_V_SYNC_A 0x06e1 +#define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2 +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2 +#define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_V_SYNC_B 0x06e3 +#define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5 +#define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_TRIGA_CNTL 0x06e7 +#define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x06e9 +#define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x06ec +#define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee +#define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTC0_CRTC_CONTROL 0x06ef +#define mmCRTC0_CRTC_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_BLANK_CONTROL 0x06f0 +#define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1 +#define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2 +#define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTC0_CRTC_STATUS 0x06f6 +#define mmCRTC0_CRTC_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_STATUS_POSITION 0x06f7 +#define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8 +#define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa +#define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb +#define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTC0_CRTC_COUNT_CONTROL 0x06fc +#define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_COUNT_RESET 0x06fd +#define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2 +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_STEREO_STATUS 0x0700 +#define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_STEREO_CONTROL 0x0701 +#define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x0706 +#define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x0708 +#define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e +#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f +#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTC0_CRTC_MVP_STATUS 0x0712 +#define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_MASTER_EN 0x0713 +#define mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719 +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTC0_CRTC_BLACK_COLOR 0x071b +#define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2 +#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c +#define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC_CNTL 0x0723 +#define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC0_DATA_RG 0x0728 +#define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC0_DATA_B 0x0729 +#define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC1_DATA_RG 0x072e +#define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTC0_CRTC_CRC1_DATA_B 0x072f +#define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTC0_CRTC_GSL_WINDOW 0x0739 +#define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2 +#define mmCRTC0_CRTC_GSL_CONTROL 0x073a +#define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2 +#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d +#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmCRTC0_CRTC_DRR_CONTROL 0x073e +#define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_fmt0_dispdec +// base address: 0x0 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742 +#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743 +#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744 +#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_CONTROL 0x0746 +#define mmFMT0_FMT_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748 +#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749 +#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a +#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_CNTL 0x074e +#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_CRC_CNTL 0x074f +#define mmFMT0_FMT_CRC_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750 +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751 +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752 +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753 +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755 +#define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 + + +// addressBlock: dce_dc_dcp1_dispdec +// base address: 0x800 +#define mmDCP1_GRPH_ENABLE 0x075a +#define mmDCP1_GRPH_ENABLE_BASE_IDX 2 +#define mmDCP1_GRPH_CONTROL 0x075b +#define mmDCP1_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c +#define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 +#define mmDCP1_GRPH_SWAP_CNTL 0x075d +#define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP1_GRPH_PITCH 0x0760 +#define mmDCP1_GRPH_PITCH_BASE_IDX 2 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763 +#define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 +#define mmDCP1_GRPH_X_START 0x0765 +#define mmDCP1_GRPH_X_START_BASE_IDX 2 +#define mmDCP1_GRPH_Y_START 0x0766 +#define mmDCP1_GRPH_Y_START_BASE_IDX 2 +#define mmDCP1_GRPH_X_END 0x0767 +#define mmDCP1_GRPH_X_END_BASE_IDX 2 +#define mmDCP1_GRPH_Y_END 0x0768 +#define mmDCP1_GRPH_Y_END_BASE_IDX 2 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x0769 +#define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_UPDATE 0x076a +#define mmDCP1_GRPH_UPDATE_BASE_IDX 2 +#define mmDCP1_GRPH_FLIP_CONTROL 0x076b +#define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 +#define mmDCP1_GRPH_DFQ_CONTROL 0x076d +#define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_DFQ_STATUS 0x076e +#define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x076f +#define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770 +#define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP1_GRPH_COMPRESS_PITCH 0x0773 +#define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775 +#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x0776 +#define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777 +#define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778 +#define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779 +#define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_CONTROL 0x077a +#define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_C11_C12 0x077b +#define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_C13_C14 0x077c +#define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_C21_C22 0x077d +#define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_C23_C24 0x077e +#define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_C31_C32 0x077f +#define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP1_INPUT_CSC_C33_C34 0x0780 +#define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_CONTROL 0x0781 +#define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_C11_C12 0x0782 +#define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_C13_C14 0x0783 +#define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_C21_C22 0x0784 +#define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_C23_C24 0x0785 +#define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x0786 +#define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x0787 +#define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790 +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791 +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792 +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793 +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP1_DENORM_CONTROL 0x0794 +#define mmDCP1_DENORM_CONTROL_BASE_IDX 2 +#define mmDCP1_OUT_ROUND_CONTROL 0x0795 +#define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2 +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796 +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797 +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798 +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 +#define mmDCP1_KEY_CONTROL 0x0799 +#define mmDCP1_KEY_CONTROL_BASE_IDX 2 +#define mmDCP1_KEY_RANGE_ALPHA 0x079a +#define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2 +#define mmDCP1_KEY_RANGE_RED 0x079b +#define mmDCP1_KEY_RANGE_RED_BASE_IDX 2 +#define mmDCP1_KEY_RANGE_GREEN 0x079c +#define mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2 +#define mmDCP1_KEY_RANGE_BLUE 0x079d +#define mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2 +#define mmDCP1_DEGAMMA_CONTROL 0x079e +#define mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_CONTROL 0x079f +#define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_C11_C12 0x07a0 +#define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_C13_C14 0x07a1 +#define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_C21_C22 0x07a2 +#define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_C23_C24 0x07a3 +#define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_C31_C32 0x07a4 +#define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmDCP1_GAMUT_REMAP_C33_C34 0x07a5 +#define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 +#define mmDCP1_DCP_RANDOM_SEEDS 0x07a7 +#define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8 +#define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmDCP1_CUR_CONTROL 0x07a9 +#define mmDCP1_CUR_CONTROL_BASE_IDX 2 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x07aa +#define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP1_CUR_SIZE 0x07ab +#define mmDCP1_CUR_SIZE_BASE_IDX 2 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP1_CUR_POSITION 0x07ad +#define mmDCP1_CUR_POSITION_BASE_IDX 2 +#define mmDCP1_CUR_HOT_SPOT 0x07ae +#define mmDCP1_CUR_HOT_SPOT_BASE_IDX 2 +#define mmDCP1_CUR_COLOR1 0x07af +#define mmDCP1_CUR_COLOR1_BASE_IDX 2 +#define mmDCP1_CUR_COLOR2 0x07b0 +#define mmDCP1_CUR_COLOR2_BASE_IDX 2 +#define mmDCP1_CUR_UPDATE 0x07b1 +#define mmDCP1_CUR_UPDATE_BASE_IDX 2 +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb +#define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 +#define mmDCP1_CUR_STEREO_CONTROL 0x07bc +#define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2 +#define mmDCP1_DC_LUT_RW_MODE 0x07be +#define mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2 +#define mmDCP1_DC_LUT_RW_INDEX 0x07bf +#define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2 +#define mmDCP1_DC_LUT_SEQ_COLOR 0x07c0 +#define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmDCP1_DC_LUT_PWL_DATA 0x07c1 +#define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2 +#define mmDCP1_DC_LUT_30_COLOR 0x07c2 +#define mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2 +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3 +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4 +#define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP1_DC_LUT_AUTOFILL 0x07c5 +#define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2 +#define mmDCP1_DC_LUT_CONTROL 0x07c6 +#define mmDCP1_DC_LUT_CONTROL_BASE_IDX 2 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 +#define mmDCP1_DCP_CRC_CONTROL 0x07cd +#define mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2 +#define mmDCP1_DCP_CRC_MASK 0x07ce +#define mmDCP1_DCP_CRC_MASK_BASE_IDX 2 +#define mmDCP1_DCP_CRC_CURRENT 0x07cf +#define mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2 +#define mmDCP1_DVMM_PTE_CONTROL 0x07d0 +#define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmDCP1_DCP_CRC_LAST 0x07d1 +#define mmDCP1_DCP_CRC_LAST_BASE_IDX 2 +#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2 +#define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4 +#define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 +#define mmDCP1_DCP_GSL_CONTROL 0x07d5 +#define mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc +#define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmDCP1_HW_ROTATION 0x07de +#define mmDCP1_HW_ROTATION_BASE_IDX 2 +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 +#define mmDCP1_REGAMMA_CONTROL 0x07e0 +#define mmDCP1_REGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP1_REGAMMA_LUT_INDEX 0x07e1 +#define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmDCP1_REGAMMA_LUT_DATA 0x07e2 +#define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmDCP1_ALPHA_CONTROL 0x07fc +#define mmDCP1_ALPHA_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 +#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800 +#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 +#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801 +#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 +#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802 +#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 +#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803 +#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 + + +// addressBlock: dce_dc_lb1_dispdec +// base address: 0x800 +#define mmLB1_LB_DATA_FORMAT 0x081a +#define mmLB1_LB_DATA_FORMAT_BASE_IDX 2 +#define mmLB1_LB_MEMORY_CTRL 0x081b +#define mmLB1_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmLB1_LB_MEMORY_SIZE_STATUS 0x081c +#define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLB1_LB_DESKTOP_HEIGHT 0x081d +#define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLB1_LB_VLINE_START_END 0x081e +#define mmLB1_LB_VLINE_START_END_BASE_IDX 2 +#define mmLB1_LB_VLINE2_START_END 0x081f +#define mmLB1_LB_VLINE2_START_END_BASE_IDX 2 +#define mmLB1_LB_V_COUNTER 0x0820 +#define mmLB1_LB_V_COUNTER_BASE_IDX 2 +#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821 +#define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLB1_LB_INTERRUPT_MASK 0x0822 +#define mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2 +#define mmLB1_LB_VLINE_STATUS 0x0823 +#define mmLB1_LB_VLINE_STATUS_BASE_IDX 2 +#define mmLB1_LB_VLINE2_STATUS 0x0824 +#define mmLB1_LB_VLINE2_STATUS_BASE_IDX 2 +#define mmLB1_LB_VBLANK_STATUS 0x0825 +#define mmLB1_LB_VBLANK_STATUS_BASE_IDX 2 +#define mmLB1_LB_SYNC_RESET_SEL 0x0826 +#define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLB1_LB_BLACK_KEYER_R_CR 0x0827 +#define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLB1_LB_BLACK_KEYER_G_Y 0x0828 +#define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLB1_LB_BLACK_KEYER_B_CB 0x0829 +#define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_CTRL 0x082a +#define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_R_CR 0x082b +#define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_G_Y 0x082c +#define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_B_CB 0x082d +#define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e +#define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f +#define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831 +#define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832 +#define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833 +#define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLB1_LB_BUFFER_STATUS 0x0834 +#define mmLB1_LB_BUFFER_STATUS_BASE_IDX 2 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 +#define mmLB1_MVP_AFR_FLIP_MODE 0x0836 +#define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 +#define mmLB1_DC_MVP_LB_CONTROL 0x0839 +#define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfe1_dispdec +// base address: 0x800 +#define mmDCFE1_DCFE_CLOCK_CONTROL 0x085a +#define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFE1_DCFE_SOFT_RESET 0x085b +#define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2 +#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d +#define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e +#define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f +#define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFE1_DCFE_MISC 0x0860 +#define mmDCFE1_DCFE_MISC_BASE_IDX 2 +#define mmDCFE1_DCFE_FLUSH 0x0861 +#define mmDCFE1_DCFE_FLUSH_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon4_dispdec +// base address: 0x2138 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e +#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870 +#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL 0x0871 +#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL2 0x0872 +#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_HI 0x0875 +#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_LOW 0x0876 +#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmif_pg1_dispdec +// base address: 0x800 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e +#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881 +#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882 +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886 +#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIF_PG1_DPG_DVMM_STATUS 0x0887 +#define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_scl1_dispdec +// base address: 0x800 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x089a +#define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b +#define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCL1_SCL_MODE 0x089c +#define mmSCL1_SCL_MODE_BASE_IDX 2 +#define mmSCL1_SCL_TAP_CONTROL 0x089d +#define mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_CONTROL 0x089e +#define mmSCL1_SCL_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_BYPASS_CONTROL 0x089f +#define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4 +#define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5 +#define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL1_SCL_VERT_FILTER_INIT 0x08a7 +#define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCL1_SCL_ROUND_OFFSET 0x08a9 +#define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2 +#define mmSCL1_SCL_UPDATE 0x08aa +#define mmSCL1_SCL_UPDATE_BASE_IDX 2 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x08ab +#define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_ALU_CONTROL 0x08ac +#define mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmSCL1_VIEWPORT_START_SECONDARY 0x08ae +#define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCL1_VIEWPORT_START 0x08af +#define mmSCL1_VIEWPORT_START_BASE_IDX 2 +#define mmSCL1_VIEWPORT_SIZE 0x08b0 +#define mmSCL1_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1 +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2 +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3 +#define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4 +#define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5 +#define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6 +#define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2 + + +// addressBlock: dce_dc_blnd1_dispdec +// base address: 0x800 +#define mmBLND1_BLND_CONTROL 0x08c7 +#define mmBLND1_BLND_CONTROL_BASE_IDX 2 +#define mmBLND1_BLND_SM_CONTROL2 0x08c8 +#define mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2 +#define mmBLND1_BLND_CONTROL2 0x08c9 +#define mmBLND1_BLND_CONTROL2_BASE_IDX 2 +#define mmBLND1_BLND_UPDATE 0x08ca +#define mmBLND1_BLND_UPDATE_BASE_IDX 2 +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLND1_BLND_V_UPDATE_LOCK 0x08cc +#define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd +#define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtc1_dispdec +// base address: 0x800 +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2 +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTC1_CRTC_H_TOTAL 0x08d3 +#define mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2 +#define mmCRTC1_CRTC_H_BLANK_START_END 0x08d4 +#define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTC1_CRTC_H_SYNC_A 0x08d5 +#define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_H_SYNC_B 0x08d7 +#define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_VBI_END 0x08d9 +#define mmCRTC1_CRTC_VBI_END_BASE_IDX 2 +#define mmCRTC1_CRTC_V_TOTAL 0x08da +#define mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x08db +#define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc +#define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd +#define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_V_BLANK_START_END 0x08e0 +#define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTC1_CRTC_V_SYNC_A 0x08e1 +#define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2 +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2 +#define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_V_SYNC_B 0x08e3 +#define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5 +#define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_TRIGA_CNTL 0x08e7 +#define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x08e9 +#define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x08ec +#define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee +#define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTC1_CRTC_CONTROL 0x08ef +#define mmCRTC1_CRTC_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_BLANK_CONTROL 0x08f0 +#define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1 +#define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2 +#define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTC1_CRTC_STATUS 0x08f6 +#define mmCRTC1_CRTC_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_STATUS_POSITION 0x08f7 +#define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8 +#define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa +#define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb +#define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTC1_CRTC_COUNT_CONTROL 0x08fc +#define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_COUNT_RESET 0x08fd +#define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2 +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_STEREO_STATUS 0x0900 +#define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_STEREO_CONTROL 0x0901 +#define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x0906 +#define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x0908 +#define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e +#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f +#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTC1_CRTC_MVP_STATUS 0x0912 +#define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_MASTER_EN 0x0913 +#define mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919 +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTC1_CRTC_BLACK_COLOR 0x091b +#define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2 +#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c +#define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC_CNTL 0x0923 +#define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC0_DATA_RG 0x0928 +#define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC0_DATA_B 0x0929 +#define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC1_DATA_RG 0x092e +#define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTC1_CRTC_CRC1_DATA_B 0x092f +#define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTC1_CRTC_GSL_WINDOW 0x0939 +#define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2 +#define mmCRTC1_CRTC_GSL_CONTROL 0x093a +#define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2 +#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d +#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmCRTC1_CRTC_DRR_CONTROL 0x093e +#define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_fmt1_dispdec +// base address: 0x800 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942 +#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943 +#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944 +#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_CONTROL 0x0946 +#define mmFMT1_FMT_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948 +#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949 +#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a +#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_CNTL 0x094e +#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_CRC_CNTL 0x094f +#define mmFMT1_FMT_CRC_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950 +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951 +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952 +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953 +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955 +#define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 + + +// addressBlock: dce_dc_dcp2_dispdec +// base address: 0x1000 +#define mmDCP2_GRPH_ENABLE 0x095a +#define mmDCP2_GRPH_ENABLE_BASE_IDX 2 +#define mmDCP2_GRPH_CONTROL 0x095b +#define mmDCP2_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c +#define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 +#define mmDCP2_GRPH_SWAP_CNTL 0x095d +#define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP2_GRPH_PITCH 0x0960 +#define mmDCP2_GRPH_PITCH_BASE_IDX 2 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963 +#define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 +#define mmDCP2_GRPH_X_START 0x0965 +#define mmDCP2_GRPH_X_START_BASE_IDX 2 +#define mmDCP2_GRPH_Y_START 0x0966 +#define mmDCP2_GRPH_Y_START_BASE_IDX 2 +#define mmDCP2_GRPH_X_END 0x0967 +#define mmDCP2_GRPH_X_END_BASE_IDX 2 +#define mmDCP2_GRPH_Y_END 0x0968 +#define mmDCP2_GRPH_Y_END_BASE_IDX 2 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x0969 +#define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_UPDATE 0x096a +#define mmDCP2_GRPH_UPDATE_BASE_IDX 2 +#define mmDCP2_GRPH_FLIP_CONTROL 0x096b +#define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 +#define mmDCP2_GRPH_DFQ_CONTROL 0x096d +#define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_DFQ_STATUS 0x096e +#define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x096f +#define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970 +#define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP2_GRPH_COMPRESS_PITCH 0x0973 +#define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975 +#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x0976 +#define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977 +#define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978 +#define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979 +#define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_CONTROL 0x097a +#define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_C11_C12 0x097b +#define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_C13_C14 0x097c +#define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_C21_C22 0x097d +#define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_C23_C24 0x097e +#define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_C31_C32 0x097f +#define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP2_INPUT_CSC_C33_C34 0x0980 +#define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_CONTROL 0x0981 +#define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_C11_C12 0x0982 +#define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_C13_C14 0x0983 +#define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_C21_C22 0x0984 +#define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_C23_C24 0x0985 +#define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x0986 +#define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x0987 +#define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990 +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991 +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992 +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993 +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP2_DENORM_CONTROL 0x0994 +#define mmDCP2_DENORM_CONTROL_BASE_IDX 2 +#define mmDCP2_OUT_ROUND_CONTROL 0x0995 +#define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2 +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996 +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997 +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998 +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 +#define mmDCP2_KEY_CONTROL 0x0999 +#define mmDCP2_KEY_CONTROL_BASE_IDX 2 +#define mmDCP2_KEY_RANGE_ALPHA 0x099a +#define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2 +#define mmDCP2_KEY_RANGE_RED 0x099b +#define mmDCP2_KEY_RANGE_RED_BASE_IDX 2 +#define mmDCP2_KEY_RANGE_GREEN 0x099c +#define mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2 +#define mmDCP2_KEY_RANGE_BLUE 0x099d +#define mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2 +#define mmDCP2_DEGAMMA_CONTROL 0x099e +#define mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_CONTROL 0x099f +#define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_C11_C12 0x09a0 +#define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_C13_C14 0x09a1 +#define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_C21_C22 0x09a2 +#define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_C23_C24 0x09a3 +#define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_C31_C32 0x09a4 +#define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmDCP2_GAMUT_REMAP_C33_C34 0x09a5 +#define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 +#define mmDCP2_DCP_RANDOM_SEEDS 0x09a7 +#define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8 +#define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmDCP2_CUR_CONTROL 0x09a9 +#define mmDCP2_CUR_CONTROL_BASE_IDX 2 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x09aa +#define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP2_CUR_SIZE 0x09ab +#define mmDCP2_CUR_SIZE_BASE_IDX 2 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP2_CUR_POSITION 0x09ad +#define mmDCP2_CUR_POSITION_BASE_IDX 2 +#define mmDCP2_CUR_HOT_SPOT 0x09ae +#define mmDCP2_CUR_HOT_SPOT_BASE_IDX 2 +#define mmDCP2_CUR_COLOR1 0x09af +#define mmDCP2_CUR_COLOR1_BASE_IDX 2 +#define mmDCP2_CUR_COLOR2 0x09b0 +#define mmDCP2_CUR_COLOR2_BASE_IDX 2 +#define mmDCP2_CUR_UPDATE 0x09b1 +#define mmDCP2_CUR_UPDATE_BASE_IDX 2 +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb +#define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 +#define mmDCP2_CUR_STEREO_CONTROL 0x09bc +#define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2 +#define mmDCP2_DC_LUT_RW_MODE 0x09be +#define mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2 +#define mmDCP2_DC_LUT_RW_INDEX 0x09bf +#define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2 +#define mmDCP2_DC_LUT_SEQ_COLOR 0x09c0 +#define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmDCP2_DC_LUT_PWL_DATA 0x09c1 +#define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2 +#define mmDCP2_DC_LUT_30_COLOR 0x09c2 +#define mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2 +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3 +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4 +#define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP2_DC_LUT_AUTOFILL 0x09c5 +#define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2 +#define mmDCP2_DC_LUT_CONTROL 0x09c6 +#define mmDCP2_DC_LUT_CONTROL_BASE_IDX 2 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 +#define mmDCP2_DCP_CRC_CONTROL 0x09cd +#define mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2 +#define mmDCP2_DCP_CRC_MASK 0x09ce +#define mmDCP2_DCP_CRC_MASK_BASE_IDX 2 +#define mmDCP2_DCP_CRC_CURRENT 0x09cf +#define mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2 +#define mmDCP2_DVMM_PTE_CONTROL 0x09d0 +#define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmDCP2_DCP_CRC_LAST 0x09d1 +#define mmDCP2_DCP_CRC_LAST_BASE_IDX 2 +#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2 +#define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4 +#define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 +#define mmDCP2_DCP_GSL_CONTROL 0x09d5 +#define mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc +#define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmDCP2_HW_ROTATION 0x09de +#define mmDCP2_HW_ROTATION_BASE_IDX 2 +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 +#define mmDCP2_REGAMMA_CONTROL 0x09e0 +#define mmDCP2_REGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP2_REGAMMA_LUT_INDEX 0x09e1 +#define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmDCP2_REGAMMA_LUT_DATA 0x09e2 +#define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmDCP2_ALPHA_CONTROL 0x09fc +#define mmDCP2_ALPHA_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 +#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00 +#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 +#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01 +#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 +#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02 +#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 +#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03 +#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 + + +// addressBlock: dce_dc_lb2_dispdec +// base address: 0x1000 +#define mmLB2_LB_DATA_FORMAT 0x0a1a +#define mmLB2_LB_DATA_FORMAT_BASE_IDX 2 +#define mmLB2_LB_MEMORY_CTRL 0x0a1b +#define mmLB2_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c +#define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLB2_LB_DESKTOP_HEIGHT 0x0a1d +#define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLB2_LB_VLINE_START_END 0x0a1e +#define mmLB2_LB_VLINE_START_END_BASE_IDX 2 +#define mmLB2_LB_VLINE2_START_END 0x0a1f +#define mmLB2_LB_VLINE2_START_END_BASE_IDX 2 +#define mmLB2_LB_V_COUNTER 0x0a20 +#define mmLB2_LB_V_COUNTER_BASE_IDX 2 +#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21 +#define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLB2_LB_INTERRUPT_MASK 0x0a22 +#define mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2 +#define mmLB2_LB_VLINE_STATUS 0x0a23 +#define mmLB2_LB_VLINE_STATUS_BASE_IDX 2 +#define mmLB2_LB_VLINE2_STATUS 0x0a24 +#define mmLB2_LB_VLINE2_STATUS_BASE_IDX 2 +#define mmLB2_LB_VBLANK_STATUS 0x0a25 +#define mmLB2_LB_VBLANK_STATUS_BASE_IDX 2 +#define mmLB2_LB_SYNC_RESET_SEL 0x0a26 +#define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLB2_LB_BLACK_KEYER_R_CR 0x0a27 +#define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLB2_LB_BLACK_KEYER_G_Y 0x0a28 +#define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLB2_LB_BLACK_KEYER_B_CB 0x0a29 +#define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a +#define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b +#define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c +#define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d +#define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e +#define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f +#define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31 +#define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32 +#define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33 +#define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLB2_LB_BUFFER_STATUS 0x0a34 +#define mmLB2_LB_BUFFER_STATUS_BASE_IDX 2 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 +#define mmLB2_MVP_AFR_FLIP_MODE 0x0a36 +#define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 +#define mmLB2_DC_MVP_LB_CONTROL 0x0a39 +#define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfe2_dispdec +// base address: 0x1000 +#define mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a +#define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFE2_DCFE_SOFT_RESET 0x0a5b +#define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2 +#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d +#define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e +#define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f +#define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFE2_DCFE_MISC 0x0a60 +#define mmDCFE2_DCFE_MISC_BASE_IDX 2 +#define mmDCFE2_DCFE_FLUSH 0x0a61 +#define mmDCFE2_DCFE_FLUSH_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon5_dispdec +// base address: 0x2938 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e +#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70 +#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL 0x0a71 +#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL2 0x0a72 +#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_HI 0x0a75 +#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_LOW 0x0a76 +#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmif_pg2_dispdec +// base address: 0x1000 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e +#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81 +#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82 +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86 +#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87 +#define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_scl2_dispdec +// base address: 0x1000 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a +#define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b +#define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCL2_SCL_MODE 0x0a9c +#define mmSCL2_SCL_MODE_BASE_IDX 2 +#define mmSCL2_SCL_TAP_CONTROL 0x0a9d +#define mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_CONTROL 0x0a9e +#define mmSCL2_SCL_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_BYPASS_CONTROL 0x0a9f +#define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4 +#define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5 +#define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7 +#define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCL2_SCL_ROUND_OFFSET 0x0aa9 +#define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2 +#define mmSCL2_SCL_UPDATE 0x0aaa +#define mmSCL2_SCL_UPDATE_BASE_IDX 2 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x0aab +#define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_ALU_CONTROL 0x0aac +#define mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmSCL2_VIEWPORT_START_SECONDARY 0x0aae +#define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCL2_VIEWPORT_START 0x0aaf +#define mmSCL2_VIEWPORT_START_BASE_IDX 2 +#define mmSCL2_VIEWPORT_SIZE 0x0ab0 +#define mmSCL2_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1 +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2 +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3 +#define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4 +#define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5 +#define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6 +#define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2 + + +// addressBlock: dce_dc_blnd2_dispdec +// base address: 0x1000 +#define mmBLND2_BLND_CONTROL 0x0ac7 +#define mmBLND2_BLND_CONTROL_BASE_IDX 2 +#define mmBLND2_BLND_SM_CONTROL2 0x0ac8 +#define mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2 +#define mmBLND2_BLND_CONTROL2 0x0ac9 +#define mmBLND2_BLND_CONTROL2_BASE_IDX 2 +#define mmBLND2_BLND_UPDATE 0x0aca +#define mmBLND2_BLND_UPDATE_BASE_IDX 2 +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLND2_BLND_V_UPDATE_LOCK 0x0acc +#define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd +#define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtc2_dispdec +// base address: 0x1000 +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2 +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTC2_CRTC_H_TOTAL 0x0ad3 +#define mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2 +#define mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4 +#define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTC2_CRTC_H_SYNC_A 0x0ad5 +#define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_H_SYNC_B 0x0ad7 +#define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_VBI_END 0x0ad9 +#define mmCRTC2_CRTC_VBI_END_BASE_IDX 2 +#define mmCRTC2_CRTC_V_TOTAL 0x0ada +#define mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb +#define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc +#define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add +#define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0 +#define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTC2_CRTC_V_SYNC_A 0x0ae1 +#define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2 +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2 +#define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_V_SYNC_B 0x0ae3 +#define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5 +#define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7 +#define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9 +#define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x0aec +#define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee +#define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTC2_CRTC_CONTROL 0x0aef +#define mmCRTC2_CRTC_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_BLANK_CONTROL 0x0af0 +#define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1 +#define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2 +#define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTC2_CRTC_STATUS 0x0af6 +#define mmCRTC2_CRTC_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_STATUS_POSITION 0x0af7 +#define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8 +#define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa +#define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb +#define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTC2_CRTC_COUNT_CONTROL 0x0afc +#define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_COUNT_RESET 0x0afd +#define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2 +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_STEREO_STATUS 0x0b00 +#define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_STEREO_CONTROL 0x0b01 +#define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06 +#define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x0b08 +#define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e +#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f +#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTC2_CRTC_MVP_STATUS 0x0b12 +#define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_MASTER_EN 0x0b13 +#define mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19 +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTC2_CRTC_BLACK_COLOR 0x0b1b +#define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2 +#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c +#define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC_CNTL 0x0b23 +#define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28 +#define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC0_DATA_B 0x0b29 +#define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e +#define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f +#define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTC2_CRTC_GSL_WINDOW 0x0b39 +#define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2 +#define mmCRTC2_CRTC_GSL_CONTROL 0x0b3a +#define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2 +#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d +#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmCRTC2_CRTC_DRR_CONTROL 0x0b3e +#define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_fmt2_dispdec +// base address: 0x1000 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42 +#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43 +#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44 +#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_CONTROL 0x0b46 +#define mmFMT2_FMT_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48 +#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49 +#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a +#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_CNTL 0x0b4e +#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_CRC_CNTL 0x0b4f +#define mmFMT2_FMT_CRC_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50 +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51 +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52 +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53 +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55 +#define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 + + +// addressBlock: dce_dc_dcp3_dispdec +// base address: 0x1800 +#define mmDCP3_GRPH_ENABLE 0x0b5a +#define mmDCP3_GRPH_ENABLE_BASE_IDX 2 +#define mmDCP3_GRPH_CONTROL 0x0b5b +#define mmDCP3_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c +#define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 +#define mmDCP3_GRPH_SWAP_CNTL 0x0b5d +#define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP3_GRPH_PITCH 0x0b60 +#define mmDCP3_GRPH_PITCH_BASE_IDX 2 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63 +#define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 +#define mmDCP3_GRPH_X_START 0x0b65 +#define mmDCP3_GRPH_X_START_BASE_IDX 2 +#define mmDCP3_GRPH_Y_START 0x0b66 +#define mmDCP3_GRPH_Y_START_BASE_IDX 2 +#define mmDCP3_GRPH_X_END 0x0b67 +#define mmDCP3_GRPH_X_END_BASE_IDX 2 +#define mmDCP3_GRPH_Y_END 0x0b68 +#define mmDCP3_GRPH_Y_END_BASE_IDX 2 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x0b69 +#define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_UPDATE 0x0b6a +#define mmDCP3_GRPH_UPDATE_BASE_IDX 2 +#define mmDCP3_GRPH_FLIP_CONTROL 0x0b6b +#define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 +#define mmDCP3_GRPH_DFQ_CONTROL 0x0b6d +#define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_DFQ_STATUS 0x0b6e +#define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f +#define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70 +#define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP3_GRPH_COMPRESS_PITCH 0x0b73 +#define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75 +#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76 +#define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77 +#define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78 +#define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79 +#define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_CONTROL 0x0b7a +#define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_C11_C12 0x0b7b +#define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_C13_C14 0x0b7c +#define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_C21_C22 0x0b7d +#define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_C23_C24 0x0b7e +#define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_C31_C32 0x0b7f +#define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP3_INPUT_CSC_C33_C34 0x0b80 +#define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_CONTROL 0x0b81 +#define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_C11_C12 0x0b82 +#define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_C13_C14 0x0b83 +#define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_C21_C22 0x0b84 +#define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_C23_C24 0x0b85 +#define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x0b86 +#define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x0b87 +#define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90 +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91 +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92 +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93 +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP3_DENORM_CONTROL 0x0b94 +#define mmDCP3_DENORM_CONTROL_BASE_IDX 2 +#define mmDCP3_OUT_ROUND_CONTROL 0x0b95 +#define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2 +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96 +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97 +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98 +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 +#define mmDCP3_KEY_CONTROL 0x0b99 +#define mmDCP3_KEY_CONTROL_BASE_IDX 2 +#define mmDCP3_KEY_RANGE_ALPHA 0x0b9a +#define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2 +#define mmDCP3_KEY_RANGE_RED 0x0b9b +#define mmDCP3_KEY_RANGE_RED_BASE_IDX 2 +#define mmDCP3_KEY_RANGE_GREEN 0x0b9c +#define mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2 +#define mmDCP3_KEY_RANGE_BLUE 0x0b9d +#define mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2 +#define mmDCP3_DEGAMMA_CONTROL 0x0b9e +#define mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f +#define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0 +#define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1 +#define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2 +#define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3 +#define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4 +#define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5 +#define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 +#define mmDCP3_DCP_RANDOM_SEEDS 0x0ba7 +#define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8 +#define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmDCP3_CUR_CONTROL 0x0ba9 +#define mmDCP3_CUR_CONTROL_BASE_IDX 2 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x0baa +#define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP3_CUR_SIZE 0x0bab +#define mmDCP3_CUR_SIZE_BASE_IDX 2 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP3_CUR_POSITION 0x0bad +#define mmDCP3_CUR_POSITION_BASE_IDX 2 +#define mmDCP3_CUR_HOT_SPOT 0x0bae +#define mmDCP3_CUR_HOT_SPOT_BASE_IDX 2 +#define mmDCP3_CUR_COLOR1 0x0baf +#define mmDCP3_CUR_COLOR1_BASE_IDX 2 +#define mmDCP3_CUR_COLOR2 0x0bb0 +#define mmDCP3_CUR_COLOR2_BASE_IDX 2 +#define mmDCP3_CUR_UPDATE 0x0bb1 +#define mmDCP3_CUR_UPDATE_BASE_IDX 2 +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb +#define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 +#define mmDCP3_CUR_STEREO_CONTROL 0x0bbc +#define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2 +#define mmDCP3_DC_LUT_RW_MODE 0x0bbe +#define mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2 +#define mmDCP3_DC_LUT_RW_INDEX 0x0bbf +#define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2 +#define mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0 +#define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmDCP3_DC_LUT_PWL_DATA 0x0bc1 +#define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2 +#define mmDCP3_DC_LUT_30_COLOR 0x0bc2 +#define mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2 +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3 +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4 +#define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP3_DC_LUT_AUTOFILL 0x0bc5 +#define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2 +#define mmDCP3_DC_LUT_CONTROL 0x0bc6 +#define mmDCP3_DC_LUT_CONTROL_BASE_IDX 2 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 +#define mmDCP3_DCP_CRC_CONTROL 0x0bcd +#define mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2 +#define mmDCP3_DCP_CRC_MASK 0x0bce +#define mmDCP3_DCP_CRC_MASK_BASE_IDX 2 +#define mmDCP3_DCP_CRC_CURRENT 0x0bcf +#define mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2 +#define mmDCP3_DVMM_PTE_CONTROL 0x0bd0 +#define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmDCP3_DCP_CRC_LAST 0x0bd1 +#define mmDCP3_DCP_CRC_LAST_BASE_IDX 2 +#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2 +#define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4 +#define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 +#define mmDCP3_DCP_GSL_CONTROL 0x0bd5 +#define mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc +#define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmDCP3_HW_ROTATION 0x0bde +#define mmDCP3_HW_ROTATION_BASE_IDX 2 +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 +#define mmDCP3_REGAMMA_CONTROL 0x0be0 +#define mmDCP3_REGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP3_REGAMMA_LUT_INDEX 0x0be1 +#define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmDCP3_REGAMMA_LUT_DATA 0x0be2 +#define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmDCP3_ALPHA_CONTROL 0x0bfc +#define mmDCP3_ALPHA_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 +#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00 +#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 +#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01 +#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 +#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02 +#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 +#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03 +#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 + + +// addressBlock: dce_dc_lb3_dispdec +// base address: 0x1800 +#define mmLB3_LB_DATA_FORMAT 0x0c1a +#define mmLB3_LB_DATA_FORMAT_BASE_IDX 2 +#define mmLB3_LB_MEMORY_CTRL 0x0c1b +#define mmLB3_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c +#define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLB3_LB_DESKTOP_HEIGHT 0x0c1d +#define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLB3_LB_VLINE_START_END 0x0c1e +#define mmLB3_LB_VLINE_START_END_BASE_IDX 2 +#define mmLB3_LB_VLINE2_START_END 0x0c1f +#define mmLB3_LB_VLINE2_START_END_BASE_IDX 2 +#define mmLB3_LB_V_COUNTER 0x0c20 +#define mmLB3_LB_V_COUNTER_BASE_IDX 2 +#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21 +#define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLB3_LB_INTERRUPT_MASK 0x0c22 +#define mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2 +#define mmLB3_LB_VLINE_STATUS 0x0c23 +#define mmLB3_LB_VLINE_STATUS_BASE_IDX 2 +#define mmLB3_LB_VLINE2_STATUS 0x0c24 +#define mmLB3_LB_VLINE2_STATUS_BASE_IDX 2 +#define mmLB3_LB_VBLANK_STATUS 0x0c25 +#define mmLB3_LB_VBLANK_STATUS_BASE_IDX 2 +#define mmLB3_LB_SYNC_RESET_SEL 0x0c26 +#define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLB3_LB_BLACK_KEYER_R_CR 0x0c27 +#define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLB3_LB_BLACK_KEYER_G_Y 0x0c28 +#define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLB3_LB_BLACK_KEYER_B_CB 0x0c29 +#define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a +#define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b +#define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c +#define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d +#define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e +#define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f +#define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31 +#define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32 +#define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33 +#define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLB3_LB_BUFFER_STATUS 0x0c34 +#define mmLB3_LB_BUFFER_STATUS_BASE_IDX 2 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 +#define mmLB3_MVP_AFR_FLIP_MODE 0x0c36 +#define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 +#define mmLB3_DC_MVP_LB_CONTROL 0x0c39 +#define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfe3_dispdec +// base address: 0x1800 +#define mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a +#define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFE3_DCFE_SOFT_RESET 0x0c5b +#define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2 +#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d +#define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e +#define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f +#define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFE3_DCFE_MISC 0x0c60 +#define mmDCFE3_DCFE_MISC_BASE_IDX 2 +#define mmDCFE3_DCFE_FLUSH 0x0c61 +#define mmDCFE3_DCFE_FLUSH_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon6_dispdec +// base address: 0x3138 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e +#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70 +#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL 0x0c71 +#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL2 0x0c72 +#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_HI 0x0c75 +#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_LOW 0x0c76 +#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmif_pg3_dispdec +// base address: 0x1800 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e +#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81 +#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82 +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86 +#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87 +#define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_scl3_dispdec +// base address: 0x1800 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a +#define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b +#define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCL3_SCL_MODE 0x0c9c +#define mmSCL3_SCL_MODE_BASE_IDX 2 +#define mmSCL3_SCL_TAP_CONTROL 0x0c9d +#define mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_CONTROL 0x0c9e +#define mmSCL3_SCL_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_BYPASS_CONTROL 0x0c9f +#define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4 +#define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5 +#define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7 +#define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCL3_SCL_ROUND_OFFSET 0x0ca9 +#define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2 +#define mmSCL3_SCL_UPDATE 0x0caa +#define mmSCL3_SCL_UPDATE_BASE_IDX 2 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x0cab +#define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_ALU_CONTROL 0x0cac +#define mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmSCL3_VIEWPORT_START_SECONDARY 0x0cae +#define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCL3_VIEWPORT_START 0x0caf +#define mmSCL3_VIEWPORT_START_BASE_IDX 2 +#define mmSCL3_VIEWPORT_SIZE 0x0cb0 +#define mmSCL3_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1 +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2 +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3 +#define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4 +#define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5 +#define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6 +#define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2 + + +// addressBlock: dce_dc_blnd3_dispdec +// base address: 0x1800 +#define mmBLND3_BLND_CONTROL 0x0cc7 +#define mmBLND3_BLND_CONTROL_BASE_IDX 2 +#define mmBLND3_BLND_SM_CONTROL2 0x0cc8 +#define mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2 +#define mmBLND3_BLND_CONTROL2 0x0cc9 +#define mmBLND3_BLND_CONTROL2_BASE_IDX 2 +#define mmBLND3_BLND_UPDATE 0x0cca +#define mmBLND3_BLND_UPDATE_BASE_IDX 2 +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc +#define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd +#define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtc3_dispdec +// base address: 0x1800 +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2 +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTC3_CRTC_H_TOTAL 0x0cd3 +#define mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2 +#define mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4 +#define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTC3_CRTC_H_SYNC_A 0x0cd5 +#define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_H_SYNC_B 0x0cd7 +#define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_VBI_END 0x0cd9 +#define mmCRTC3_CRTC_VBI_END_BASE_IDX 2 +#define mmCRTC3_CRTC_V_TOTAL 0x0cda +#define mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb +#define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc +#define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd +#define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0 +#define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTC3_CRTC_V_SYNC_A 0x0ce1 +#define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2 +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2 +#define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_V_SYNC_B 0x0ce3 +#define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5 +#define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7 +#define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9 +#define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x0cec +#define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee +#define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTC3_CRTC_CONTROL 0x0cef +#define mmCRTC3_CRTC_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0 +#define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1 +#define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2 +#define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTC3_CRTC_STATUS 0x0cf6 +#define mmCRTC3_CRTC_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_STATUS_POSITION 0x0cf7 +#define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8 +#define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa +#define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb +#define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc +#define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_COUNT_RESET 0x0cfd +#define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2 +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_STEREO_STATUS 0x0d00 +#define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_STEREO_CONTROL 0x0d01 +#define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06 +#define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x0d08 +#define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e +#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f +#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTC3_CRTC_MVP_STATUS 0x0d12 +#define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_MASTER_EN 0x0d13 +#define mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19 +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTC3_CRTC_BLACK_COLOR 0x0d1b +#define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2 +#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c +#define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC_CNTL 0x0d23 +#define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28 +#define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC0_DATA_B 0x0d29 +#define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e +#define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f +#define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTC3_CRTC_GSL_WINDOW 0x0d39 +#define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2 +#define mmCRTC3_CRTC_GSL_CONTROL 0x0d3a +#define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2 +#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d +#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmCRTC3_CRTC_DRR_CONTROL 0x0d3e +#define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_fmt3_dispdec +// base address: 0x1800 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42 +#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43 +#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44 +#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_CONTROL 0x0d46 +#define mmFMT3_FMT_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48 +#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49 +#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a +#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_CNTL 0x0d4e +#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_CRC_CNTL 0x0d4f +#define mmFMT3_FMT_CRC_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50 +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51 +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52 +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53 +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55 +#define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 + + +// addressBlock: dce_dc_dcp4_dispdec +// base address: 0x2000 +#define mmDCP4_GRPH_ENABLE 0x0d5a +#define mmDCP4_GRPH_ENABLE_BASE_IDX 2 +#define mmDCP4_GRPH_CONTROL 0x0d5b +#define mmDCP4_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c +#define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 +#define mmDCP4_GRPH_SWAP_CNTL 0x0d5d +#define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP4_GRPH_PITCH 0x0d60 +#define mmDCP4_GRPH_PITCH_BASE_IDX 2 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63 +#define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 +#define mmDCP4_GRPH_X_START 0x0d65 +#define mmDCP4_GRPH_X_START_BASE_IDX 2 +#define mmDCP4_GRPH_Y_START 0x0d66 +#define mmDCP4_GRPH_Y_START_BASE_IDX 2 +#define mmDCP4_GRPH_X_END 0x0d67 +#define mmDCP4_GRPH_X_END_BASE_IDX 2 +#define mmDCP4_GRPH_Y_END 0x0d68 +#define mmDCP4_GRPH_Y_END_BASE_IDX 2 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x0d69 +#define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_UPDATE 0x0d6a +#define mmDCP4_GRPH_UPDATE_BASE_IDX 2 +#define mmDCP4_GRPH_FLIP_CONTROL 0x0d6b +#define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 +#define mmDCP4_GRPH_DFQ_CONTROL 0x0d6d +#define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_DFQ_STATUS 0x0d6e +#define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f +#define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70 +#define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP4_GRPH_COMPRESS_PITCH 0x0d73 +#define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75 +#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76 +#define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77 +#define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78 +#define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79 +#define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_CONTROL 0x0d7a +#define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_C11_C12 0x0d7b +#define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_C13_C14 0x0d7c +#define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_C21_C22 0x0d7d +#define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_C23_C24 0x0d7e +#define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_C31_C32 0x0d7f +#define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP4_INPUT_CSC_C33_C34 0x0d80 +#define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_CONTROL 0x0d81 +#define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_C11_C12 0x0d82 +#define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_C13_C14 0x0d83 +#define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_C21_C22 0x0d84 +#define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_C23_C24 0x0d85 +#define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x0d86 +#define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x0d87 +#define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90 +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91 +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92 +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93 +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP4_DENORM_CONTROL 0x0d94 +#define mmDCP4_DENORM_CONTROL_BASE_IDX 2 +#define mmDCP4_OUT_ROUND_CONTROL 0x0d95 +#define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2 +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96 +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97 +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98 +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 +#define mmDCP4_KEY_CONTROL 0x0d99 +#define mmDCP4_KEY_CONTROL_BASE_IDX 2 +#define mmDCP4_KEY_RANGE_ALPHA 0x0d9a +#define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2 +#define mmDCP4_KEY_RANGE_RED 0x0d9b +#define mmDCP4_KEY_RANGE_RED_BASE_IDX 2 +#define mmDCP4_KEY_RANGE_GREEN 0x0d9c +#define mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2 +#define mmDCP4_KEY_RANGE_BLUE 0x0d9d +#define mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2 +#define mmDCP4_DEGAMMA_CONTROL 0x0d9e +#define mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f +#define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_C11_C12 0x0da0 +#define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_C13_C14 0x0da1 +#define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_C21_C22 0x0da2 +#define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_C23_C24 0x0da3 +#define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_C31_C32 0x0da4 +#define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmDCP4_GAMUT_REMAP_C33_C34 0x0da5 +#define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 +#define mmDCP4_DCP_RANDOM_SEEDS 0x0da7 +#define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8 +#define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmDCP4_CUR_CONTROL 0x0da9 +#define mmDCP4_CUR_CONTROL_BASE_IDX 2 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x0daa +#define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP4_CUR_SIZE 0x0dab +#define mmDCP4_CUR_SIZE_BASE_IDX 2 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP4_CUR_POSITION 0x0dad +#define mmDCP4_CUR_POSITION_BASE_IDX 2 +#define mmDCP4_CUR_HOT_SPOT 0x0dae +#define mmDCP4_CUR_HOT_SPOT_BASE_IDX 2 +#define mmDCP4_CUR_COLOR1 0x0daf +#define mmDCP4_CUR_COLOR1_BASE_IDX 2 +#define mmDCP4_CUR_COLOR2 0x0db0 +#define mmDCP4_CUR_COLOR2_BASE_IDX 2 +#define mmDCP4_CUR_UPDATE 0x0db1 +#define mmDCP4_CUR_UPDATE_BASE_IDX 2 +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb +#define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 +#define mmDCP4_CUR_STEREO_CONTROL 0x0dbc +#define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2 +#define mmDCP4_DC_LUT_RW_MODE 0x0dbe +#define mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2 +#define mmDCP4_DC_LUT_RW_INDEX 0x0dbf +#define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2 +#define mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0 +#define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmDCP4_DC_LUT_PWL_DATA 0x0dc1 +#define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2 +#define mmDCP4_DC_LUT_30_COLOR 0x0dc2 +#define mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2 +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3 +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4 +#define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP4_DC_LUT_AUTOFILL 0x0dc5 +#define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2 +#define mmDCP4_DC_LUT_CONTROL 0x0dc6 +#define mmDCP4_DC_LUT_CONTROL_BASE_IDX 2 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 +#define mmDCP4_DCP_CRC_CONTROL 0x0dcd +#define mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2 +#define mmDCP4_DCP_CRC_MASK 0x0dce +#define mmDCP4_DCP_CRC_MASK_BASE_IDX 2 +#define mmDCP4_DCP_CRC_CURRENT 0x0dcf +#define mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2 +#define mmDCP4_DVMM_PTE_CONTROL 0x0dd0 +#define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmDCP4_DCP_CRC_LAST 0x0dd1 +#define mmDCP4_DCP_CRC_LAST_BASE_IDX 2 +#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2 +#define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4 +#define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 +#define mmDCP4_DCP_GSL_CONTROL 0x0dd5 +#define mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc +#define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmDCP4_HW_ROTATION 0x0dde +#define mmDCP4_HW_ROTATION_BASE_IDX 2 +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 +#define mmDCP4_REGAMMA_CONTROL 0x0de0 +#define mmDCP4_REGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP4_REGAMMA_LUT_INDEX 0x0de1 +#define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmDCP4_REGAMMA_LUT_DATA 0x0de2 +#define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmDCP4_ALPHA_CONTROL 0x0dfc +#define mmDCP4_ALPHA_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 +#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00 +#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 +#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01 +#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 +#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02 +#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 +#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03 +#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 + + +// addressBlock: dce_dc_lb4_dispdec +// base address: 0x2000 +#define mmLB4_LB_DATA_FORMAT 0x0e1a +#define mmLB4_LB_DATA_FORMAT_BASE_IDX 2 +#define mmLB4_LB_MEMORY_CTRL 0x0e1b +#define mmLB4_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c +#define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLB4_LB_DESKTOP_HEIGHT 0x0e1d +#define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLB4_LB_VLINE_START_END 0x0e1e +#define mmLB4_LB_VLINE_START_END_BASE_IDX 2 +#define mmLB4_LB_VLINE2_START_END 0x0e1f +#define mmLB4_LB_VLINE2_START_END_BASE_IDX 2 +#define mmLB4_LB_V_COUNTER 0x0e20 +#define mmLB4_LB_V_COUNTER_BASE_IDX 2 +#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21 +#define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLB4_LB_INTERRUPT_MASK 0x0e22 +#define mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2 +#define mmLB4_LB_VLINE_STATUS 0x0e23 +#define mmLB4_LB_VLINE_STATUS_BASE_IDX 2 +#define mmLB4_LB_VLINE2_STATUS 0x0e24 +#define mmLB4_LB_VLINE2_STATUS_BASE_IDX 2 +#define mmLB4_LB_VBLANK_STATUS 0x0e25 +#define mmLB4_LB_VBLANK_STATUS_BASE_IDX 2 +#define mmLB4_LB_SYNC_RESET_SEL 0x0e26 +#define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLB4_LB_BLACK_KEYER_R_CR 0x0e27 +#define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLB4_LB_BLACK_KEYER_G_Y 0x0e28 +#define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLB4_LB_BLACK_KEYER_B_CB 0x0e29 +#define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a +#define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b +#define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c +#define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d +#define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e +#define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f +#define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31 +#define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32 +#define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33 +#define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLB4_LB_BUFFER_STATUS 0x0e34 +#define mmLB4_LB_BUFFER_STATUS_BASE_IDX 2 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 +#define mmLB4_MVP_AFR_FLIP_MODE 0x0e36 +#define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 +#define mmLB4_DC_MVP_LB_CONTROL 0x0e39 +#define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfe4_dispdec +// base address: 0x2000 +#define mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a +#define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFE4_DCFE_SOFT_RESET 0x0e5b +#define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2 +#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d +#define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e +#define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f +#define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFE4_DCFE_MISC 0x0e60 +#define mmDCFE4_DCFE_MISC_BASE_IDX 2 +#define mmDCFE4_DCFE_FLUSH 0x0e61 +#define mmDCFE4_DCFE_FLUSH_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon7_dispdec +// base address: 0x3938 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e +#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70 +#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL 0x0e71 +#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e72 +#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_HI 0x0e75 +#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_LOW 0x0e76 +#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmif_pg4_dispdec +// base address: 0x2000 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e +#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81 +#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82 +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86 +#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87 +#define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_scl4_dispdec +// base address: 0x2000 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a +#define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b +#define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCL4_SCL_MODE 0x0e9c +#define mmSCL4_SCL_MODE_BASE_IDX 2 +#define mmSCL4_SCL_TAP_CONTROL 0x0e9d +#define mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_CONTROL 0x0e9e +#define mmSCL4_SCL_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_BYPASS_CONTROL 0x0e9f +#define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4 +#define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5 +#define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7 +#define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCL4_SCL_ROUND_OFFSET 0x0ea9 +#define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2 +#define mmSCL4_SCL_UPDATE 0x0eaa +#define mmSCL4_SCL_UPDATE_BASE_IDX 2 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x0eab +#define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_ALU_CONTROL 0x0eac +#define mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmSCL4_VIEWPORT_START_SECONDARY 0x0eae +#define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCL4_VIEWPORT_START 0x0eaf +#define mmSCL4_VIEWPORT_START_BASE_IDX 2 +#define mmSCL4_VIEWPORT_SIZE 0x0eb0 +#define mmSCL4_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1 +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2 +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3 +#define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4 +#define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5 +#define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6 +#define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2 + + +// addressBlock: dce_dc_blnd4_dispdec +// base address: 0x2000 +#define mmBLND4_BLND_CONTROL 0x0ec7 +#define mmBLND4_BLND_CONTROL_BASE_IDX 2 +#define mmBLND4_BLND_SM_CONTROL2 0x0ec8 +#define mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2 +#define mmBLND4_BLND_CONTROL2 0x0ec9 +#define mmBLND4_BLND_CONTROL2_BASE_IDX 2 +#define mmBLND4_BLND_UPDATE 0x0eca +#define mmBLND4_BLND_UPDATE_BASE_IDX 2 +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc +#define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd +#define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtc4_dispdec +// base address: 0x2000 +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2 +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTC4_CRTC_H_TOTAL 0x0ed3 +#define mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2 +#define mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4 +#define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTC4_CRTC_H_SYNC_A 0x0ed5 +#define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_H_SYNC_B 0x0ed7 +#define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_VBI_END 0x0ed9 +#define mmCRTC4_CRTC_VBI_END_BASE_IDX 2 +#define mmCRTC4_CRTC_V_TOTAL 0x0eda +#define mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb +#define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc +#define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd +#define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0 +#define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTC4_CRTC_V_SYNC_A 0x0ee1 +#define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2 +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2 +#define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_V_SYNC_B 0x0ee3 +#define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5 +#define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7 +#define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9 +#define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x0eec +#define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee +#define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTC4_CRTC_CONTROL 0x0eef +#define mmCRTC4_CRTC_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0 +#define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1 +#define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2 +#define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTC4_CRTC_STATUS 0x0ef6 +#define mmCRTC4_CRTC_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_STATUS_POSITION 0x0ef7 +#define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8 +#define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa +#define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb +#define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTC4_CRTC_COUNT_CONTROL 0x0efc +#define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_COUNT_RESET 0x0efd +#define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2 +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_STEREO_STATUS 0x0f00 +#define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_STEREO_CONTROL 0x0f01 +#define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06 +#define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x0f08 +#define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e +#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f +#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTC4_CRTC_MVP_STATUS 0x0f12 +#define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_MASTER_EN 0x0f13 +#define mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19 +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTC4_CRTC_BLACK_COLOR 0x0f1b +#define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2 +#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c +#define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC_CNTL 0x0f23 +#define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28 +#define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC0_DATA_B 0x0f29 +#define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e +#define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f +#define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTC4_CRTC_GSL_WINDOW 0x0f39 +#define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2 +#define mmCRTC4_CRTC_GSL_CONTROL 0x0f3a +#define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2 +#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d +#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e +#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_fmt4_dispdec +// base address: 0x2000 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42 +#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43 +#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44 +#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_CONTROL 0x0f46 +#define mmFMT4_FMT_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48 +#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49 +#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a +#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_CNTL 0x0f4e +#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_CRC_CNTL 0x0f4f +#define mmFMT4_FMT_CRC_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50 +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51 +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52 +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53 +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55 +#define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 + + +// addressBlock: dce_dc_dcp5_dispdec +// base address: 0x2800 +#define mmDCP5_GRPH_ENABLE 0x0f5a +#define mmDCP5_GRPH_ENABLE_BASE_IDX 2 +#define mmDCP5_GRPH_CONTROL 0x0f5b +#define mmDCP5_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c +#define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2 +#define mmDCP5_GRPH_SWAP_CNTL 0x0f5d +#define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP5_GRPH_PITCH 0x0f60 +#define mmDCP5_GRPH_PITCH_BASE_IDX 2 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63 +#define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2 +#define mmDCP5_GRPH_X_START 0x0f65 +#define mmDCP5_GRPH_X_START_BASE_IDX 2 +#define mmDCP5_GRPH_Y_START 0x0f66 +#define mmDCP5_GRPH_Y_START_BASE_IDX 2 +#define mmDCP5_GRPH_X_END 0x0f67 +#define mmDCP5_GRPH_X_END_BASE_IDX 2 +#define mmDCP5_GRPH_Y_END 0x0f68 +#define mmDCP5_GRPH_Y_END_BASE_IDX 2 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x0f69 +#define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_UPDATE 0x0f6a +#define mmDCP5_GRPH_UPDATE_BASE_IDX 2 +#define mmDCP5_GRPH_FLIP_CONTROL 0x0f6b +#define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2 +#define mmDCP5_GRPH_DFQ_CONTROL 0x0f6d +#define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_DFQ_STATUS 0x0f6e +#define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f +#define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70 +#define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP5_GRPH_COMPRESS_PITCH 0x0f73 +#define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75 +#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76 +#define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2 +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77 +#define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2 +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78 +#define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79 +#define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_CONTROL 0x0f7a +#define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_C11_C12 0x0f7b +#define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_C13_C14 0x0f7c +#define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_C21_C22 0x0f7d +#define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_C23_C24 0x0f7e +#define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_C31_C32 0x0f7f +#define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP5_INPUT_CSC_C33_C34 0x0f80 +#define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_CONTROL 0x0f81 +#define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_C11_C12 0x0f82 +#define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_C13_C14 0x0f83 +#define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_C21_C22 0x0f84 +#define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_C23_C24 0x0f85 +#define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x0f86 +#define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x0f87 +#define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90 +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91 +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92 +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2 +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93 +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2 +#define mmDCP5_DENORM_CONTROL 0x0f94 +#define mmDCP5_DENORM_CONTROL_BASE_IDX 2 +#define mmDCP5_OUT_ROUND_CONTROL 0x0f95 +#define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2 +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96 +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2 +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97 +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2 +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98 +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2 +#define mmDCP5_KEY_CONTROL 0x0f99 +#define mmDCP5_KEY_CONTROL_BASE_IDX 2 +#define mmDCP5_KEY_RANGE_ALPHA 0x0f9a +#define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2 +#define mmDCP5_KEY_RANGE_RED 0x0f9b +#define mmDCP5_KEY_RANGE_RED_BASE_IDX 2 +#define mmDCP5_KEY_RANGE_GREEN 0x0f9c +#define mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2 +#define mmDCP5_KEY_RANGE_BLUE 0x0f9d +#define mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2 +#define mmDCP5_DEGAMMA_CONTROL 0x0f9e +#define mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f +#define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0 +#define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1 +#define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2 +#define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3 +#define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4 +#define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5 +#define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2 +#define mmDCP5_DCP_RANDOM_SEEDS 0x0fa7 +#define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8 +#define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmDCP5_CUR_CONTROL 0x0fa9 +#define mmDCP5_CUR_CONTROL_BASE_IDX 2 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x0faa +#define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP5_CUR_SIZE 0x0fab +#define mmDCP5_CUR_SIZE_BASE_IDX 2 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP5_CUR_POSITION 0x0fad +#define mmDCP5_CUR_POSITION_BASE_IDX 2 +#define mmDCP5_CUR_HOT_SPOT 0x0fae +#define mmDCP5_CUR_HOT_SPOT_BASE_IDX 2 +#define mmDCP5_CUR_COLOR1 0x0faf +#define mmDCP5_CUR_COLOR1_BASE_IDX 2 +#define mmDCP5_CUR_COLOR2 0x0fb0 +#define mmDCP5_CUR_COLOR2_BASE_IDX 2 +#define mmDCP5_CUR_UPDATE 0x0fb1 +#define mmDCP5_CUR_UPDATE_BASE_IDX 2 +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb +#define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2 +#define mmDCP5_CUR_STEREO_CONTROL 0x0fbc +#define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2 +#define mmDCP5_DC_LUT_RW_MODE 0x0fbe +#define mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2 +#define mmDCP5_DC_LUT_RW_INDEX 0x0fbf +#define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2 +#define mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0 +#define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmDCP5_DC_LUT_PWL_DATA 0x0fc1 +#define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2 +#define mmDCP5_DC_LUT_30_COLOR 0x0fc2 +#define mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2 +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3 +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2 +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4 +#define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP5_DC_LUT_AUTOFILL 0x0fc5 +#define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2 +#define mmDCP5_DC_LUT_CONTROL 0x0fc6 +#define mmDCP5_DC_LUT_CONTROL_BASE_IDX 2 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2 +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2 +#define mmDCP5_DCP_CRC_CONTROL 0x0fcd +#define mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2 +#define mmDCP5_DCP_CRC_MASK 0x0fce +#define mmDCP5_DCP_CRC_MASK_BASE_IDX 2 +#define mmDCP5_DCP_CRC_CURRENT 0x0fcf +#define mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2 +#define mmDCP5_DVMM_PTE_CONTROL 0x0fd0 +#define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmDCP5_DCP_CRC_LAST 0x0fd1 +#define mmDCP5_DCP_CRC_LAST_BASE_IDX 2 +#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2 +#define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4 +#define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2 +#define mmDCP5_DCP_GSL_CONTROL 0x0fd5 +#define mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc +#define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmDCP5_HW_ROTATION 0x0fde +#define mmDCP5_HW_ROTATION_BASE_IDX 2 +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2 +#define mmDCP5_REGAMMA_CONTROL 0x0fe0 +#define mmDCP5_REGAMMA_CONTROL_BASE_IDX 2 +#define mmDCP5_REGAMMA_LUT_INDEX 0x0fe1 +#define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmDCP5_REGAMMA_LUT_DATA 0x0fe2 +#define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmDCP5_ALPHA_CONTROL 0x0ffc +#define mmDCP5_ALPHA_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2 +#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000 +#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2 +#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001 +#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2 +#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002 +#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2 +#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003 +#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2 + + +// addressBlock: dce_dc_lb5_dispdec +// base address: 0x2800 +#define mmLB5_LB_DATA_FORMAT 0x101a +#define mmLB5_LB_DATA_FORMAT_BASE_IDX 2 +#define mmLB5_LB_MEMORY_CTRL 0x101b +#define mmLB5_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmLB5_LB_MEMORY_SIZE_STATUS 0x101c +#define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLB5_LB_DESKTOP_HEIGHT 0x101d +#define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLB5_LB_VLINE_START_END 0x101e +#define mmLB5_LB_VLINE_START_END_BASE_IDX 2 +#define mmLB5_LB_VLINE2_START_END 0x101f +#define mmLB5_LB_VLINE2_START_END_BASE_IDX 2 +#define mmLB5_LB_V_COUNTER 0x1020 +#define mmLB5_LB_V_COUNTER_BASE_IDX 2 +#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021 +#define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLB5_LB_INTERRUPT_MASK 0x1022 +#define mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2 +#define mmLB5_LB_VLINE_STATUS 0x1023 +#define mmLB5_LB_VLINE_STATUS_BASE_IDX 2 +#define mmLB5_LB_VLINE2_STATUS 0x1024 +#define mmLB5_LB_VLINE2_STATUS_BASE_IDX 2 +#define mmLB5_LB_VBLANK_STATUS 0x1025 +#define mmLB5_LB_VBLANK_STATUS_BASE_IDX 2 +#define mmLB5_LB_SYNC_RESET_SEL 0x1026 +#define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLB5_LB_BLACK_KEYER_R_CR 0x1027 +#define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLB5_LB_BLACK_KEYER_G_Y 0x1028 +#define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLB5_LB_BLACK_KEYER_B_CB 0x1029 +#define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_CTRL 0x102a +#define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_R_CR 0x102b +#define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_G_Y 0x102c +#define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_B_CB 0x102d +#define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e +#define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f +#define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031 +#define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032 +#define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033 +#define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLB5_LB_BUFFER_STATUS 0x1034 +#define mmLB5_LB_BUFFER_STATUS_BASE_IDX 2 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 +#define mmLB5_MVP_AFR_FLIP_MODE 0x1036 +#define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2 +#define mmLB5_DC_MVP_LB_CONTROL 0x1039 +#define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfe5_dispdec +// base address: 0x2800 +#define mmDCFE5_DCFE_CLOCK_CONTROL 0x105a +#define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFE5_DCFE_SOFT_RESET 0x105b +#define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2 +#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d +#define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e +#define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f +#define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFE5_DCFE_MISC 0x1060 +#define mmDCFE5_DCFE_MISC_BASE_IDX 2 +#define mmDCFE5_DCFE_FLUSH 0x1061 +#define mmDCFE5_DCFE_FLUSH_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon8_dispdec +// base address: 0x4138 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e +#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070 +#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL 0x1071 +#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL2 0x1072 +#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_HI 0x1075 +#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_LOW 0x1076 +#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmif_pg5_dispdec +// base address: 0x2800 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e +#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2 +#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081 +#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2 +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082 +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086 +#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIF_PG5_DPG_DVMM_STATUS 0x1087 +#define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_scl5_dispdec +// base address: 0x2800 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x109a +#define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b +#define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCL5_SCL_MODE 0x109c +#define mmSCL5_SCL_MODE_BASE_IDX 2 +#define mmSCL5_SCL_TAP_CONTROL 0x109d +#define mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_CONTROL 0x109e +#define mmSCL5_SCL_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_BYPASS_CONTROL 0x109f +#define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4 +#define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5 +#define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCL5_SCL_VERT_FILTER_INIT 0x10a7 +#define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCL5_SCL_ROUND_OFFSET 0x10a9 +#define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2 +#define mmSCL5_SCL_UPDATE 0x10aa +#define mmSCL5_SCL_UPDATE_BASE_IDX 2 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x10ab +#define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_ALU_CONTROL 0x10ac +#define mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmSCL5_VIEWPORT_START_SECONDARY 0x10ae +#define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCL5_VIEWPORT_START 0x10af +#define mmSCL5_VIEWPORT_START_BASE_IDX 2 +#define mmSCL5_VIEWPORT_SIZE 0x10b0 +#define mmSCL5_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1 +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2 +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3 +#define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4 +#define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5 +#define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6 +#define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2 + + +// addressBlock: dce_dc_blnd5_dispdec +// base address: 0x2800 +#define mmBLND5_BLND_CONTROL 0x10c7 +#define mmBLND5_BLND_CONTROL_BASE_IDX 2 +#define mmBLND5_BLND_SM_CONTROL2 0x10c8 +#define mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2 +#define mmBLND5_BLND_CONTROL2 0x10c9 +#define mmBLND5_BLND_CONTROL2_BASE_IDX 2 +#define mmBLND5_BLND_UPDATE 0x10ca +#define mmBLND5_BLND_UPDATE_BASE_IDX 2 +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLND5_BLND_V_UPDATE_LOCK 0x10cc +#define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd +#define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtc5_dispdec +// base address: 0x2800 +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2 +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTC5_CRTC_H_TOTAL 0x10d3 +#define mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2 +#define mmCRTC5_CRTC_H_BLANK_START_END 0x10d4 +#define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTC5_CRTC_H_SYNC_A 0x10d5 +#define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_H_SYNC_B 0x10d7 +#define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_VBI_END 0x10d9 +#define mmCRTC5_CRTC_VBI_END_BASE_IDX 2 +#define mmCRTC5_CRTC_V_TOTAL 0x10da +#define mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x10db +#define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc +#define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd +#define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_V_BLANK_START_END 0x10e0 +#define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTC5_CRTC_V_SYNC_A 0x10e1 +#define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2 +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2 +#define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_V_SYNC_B 0x10e3 +#define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5 +#define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_TRIGA_CNTL 0x10e7 +#define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x10e9 +#define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x10ec +#define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee +#define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTC5_CRTC_CONTROL 0x10ef +#define mmCRTC5_CRTC_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_BLANK_CONTROL 0x10f0 +#define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1 +#define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2 +#define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTC5_CRTC_STATUS 0x10f6 +#define mmCRTC5_CRTC_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_STATUS_POSITION 0x10f7 +#define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8 +#define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa +#define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb +#define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTC5_CRTC_COUNT_CONTROL 0x10fc +#define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_COUNT_RESET 0x10fd +#define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2 +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_STEREO_STATUS 0x1100 +#define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_STEREO_CONTROL 0x1101 +#define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x1106 +#define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x1108 +#define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e +#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f +#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTC5_CRTC_MVP_STATUS 0x1112 +#define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_MASTER_EN 0x1113 +#define mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119 +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTC5_CRTC_BLACK_COLOR 0x111b +#define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2 +#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c +#define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC_CNTL 0x1123 +#define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC0_DATA_RG 0x1128 +#define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC0_DATA_B 0x1129 +#define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC1_DATA_RG 0x112e +#define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTC5_CRTC_CRC1_DATA_B 0x112f +#define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTC5_CRTC_GSL_WINDOW 0x1139 +#define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2 +#define mmCRTC5_CRTC_GSL_CONTROL 0x113a +#define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2 +#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d +#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmCRTC5_CRTC_DRR_CONTROL 0x113e +#define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_fmt5_dispdec +// base address: 0x2800 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142 +#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143 +#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144 +#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_CONTROL 0x1146 +#define mmFMT5_FMT_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148 +#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149 +#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a +#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_CNTL 0x114e +#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_CRC_CNTL 0x114f +#define mmFMT5_FMT_CRC_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150 +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151 +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152 +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2 +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153 +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155 +#define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2 + + +// addressBlock: dce_dc_unp0_dispdec +// base address: 0x0 +#define mmUNP0_UNP_GRPH_ENABLE 0x115a +#define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_CONTROL 0x115b +#define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_CONTROL_C 0x115c +#define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d +#define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e +#define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162 +#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166 +#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a +#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e +#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PITCH_L 0x116f +#define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_PITCH_C 0x1170 +#define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174 +#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_X_START_L 0x1175 +#define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_X_START_C 0x1176 +#define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_Y_START_L 0x1177 +#define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_Y_START_C 0x1178 +#define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_X_END_L 0x1179 +#define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_X_END_C 0x117a +#define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_Y_END_L 0x117b +#define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_Y_END_C 0x117c +#define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_UPDATE 0x117d +#define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2 +#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e +#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182 +#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2 +#define mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183 +#define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184 +#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2 +#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185 +#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186 +#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187 +#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188 +#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189 +#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmUNP0_UNP_FLIP_CONTROL 0x118a +#define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2 +#define mmUNP0_UNP_CRC_CONTROL 0x118b +#define mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2 +#define mmUNP0_UNP_CRC_MASK 0x118c +#define mmUNP0_UNP_CRC_MASK_BASE_IDX 2 +#define mmUNP0_UNP_CRC_CURRENT 0x118d +#define mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2 +#define mmUNP0_UNP_CRC_LAST 0x118e +#define mmUNP0_UNP_CRC_LAST_BASE_IDX 2 +#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f +#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmUNP0_UNP_HW_ROTATION 0x1190 +#define mmUNP0_UNP_HW_ROTATION_BASE_IDX 2 + + +// addressBlock: dce_dc_lbv0_dispdec +// base address: 0x0 +#define mmLBV0_LBV_DATA_FORMAT 0x1196 +#define mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2 +#define mmLBV0_LBV_MEMORY_CTRL 0x1197 +#define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2 +#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198 +#define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_DESKTOP_HEIGHT 0x1199 +#define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLBV0_LBV_VLINE_START_END 0x119a +#define mmLBV0_LBV_VLINE_START_END_BASE_IDX 2 +#define mmLBV0_LBV_VLINE2_START_END 0x119b +#define mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2 +#define mmLBV0_LBV_V_COUNTER 0x119c +#define mmLBV0_LBV_V_COUNTER_BASE_IDX 2 +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLBV0_LBV_V_COUNTER_CHROMA 0x119e +#define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2 +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f +#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2 +#define mmLBV0_LBV_INTERRUPT_MASK 0x11a0 +#define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2 +#define mmLBV0_LBV_VLINE_STATUS 0x11a1 +#define mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_VLINE2_STATUS 0x11a2 +#define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_VBLANK_STATUS 0x11a3 +#define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_SYNC_RESET_SEL 0x11a4 +#define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5 +#define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6 +#define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7 +#define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8 +#define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9 +#define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa +#define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab +#define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac +#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad +#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae +#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af +#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0 +#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1 +#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_BUFFER_STATUS 0x11b2 +#define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2 +#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3 +#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_sclv0_dispdec +// base address: 0x0 +#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca +#define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb +#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCLV0_SCLV_MODE 0x11cc +#define mmSCLV0_SCLV_MODE_BASE_IDX 2 +#define mmSCLV0_SCLV_TAP_CONTROL 0x11cd +#define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_CONTROL 0x11ce +#define mmSCLV0_SCLV_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf +#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0 +#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1 +#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4 +#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6 +#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7 +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da +#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db +#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc +#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmSCLV0_SCLV_ROUND_OFFSET 0x11dd +#define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2 +#define mmSCLV0_SCLV_UPDATE 0x11de +#define mmSCLV0_SCLV_UPDATE_BASE_IDX 2 +#define mmSCLV0_SCLV_ALU_CONTROL 0x11df +#define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2 +#define mmSCLV0_SCLV_VIEWPORT_START 0x11e0 +#define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2 +#define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3 +#define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4 +#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2 +#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5 +#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2 +#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6 +#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7 +#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8 +#define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9 +#define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea +#define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb +#define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed +#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2 + + +// addressBlock: dce_dc_col_man0_dispdec +// base address: 0x0 +#define mmCOL_MAN0_COL_MAN_UPDATE 0x11fe +#define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff +#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204 +#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205 +#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206 +#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207 +#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208 +#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209 +#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a +#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b +#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2 +#define mmCOL_MAN0_PRESCALE_CONTROL 0x120c +#define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_PRESCALE_VALUES_R 0x120d +#define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2 +#define mmCOL_MAN0_PRESCALE_VALUES_G 0x120e +#define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2 +#define mmCOL_MAN0_PRESCALE_VALUES_B 0x120f +#define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210 +#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214 +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215 +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216 +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217 +#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218 +#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219 +#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a +#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b +#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c +#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2 +#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d +#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220 +#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221 +#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225 +#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d +#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmCOL_MAN0_PACK_FIFO_ERROR 0x123e +#define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2 +#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f +#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244 +#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245 +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246 +#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249 +#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a +#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251 +#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfev0_dispdec +// base address: 0x0 +#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e +#define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFEV0_DCFEV_SOFT_RESET 0x127f +#define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2 +#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280 +#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283 +#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284 +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285 +#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286 +#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFEV0_DCFEV_L_FLUSH 0x1287 +#define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2 +#define mmDCFEV0_DCFEV_C_FLUSH 0x1288 +#define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2 +#define mmDCFEV0_DCFEV_MISC 0x128a +#define mmDCFEV0_DCFEV_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon11_dispdec +// base address: 0x49c8 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294 +#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL 0x1295 +#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL2 0x1296 +#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_HI 0x1299 +#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_LOW 0x129a +#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmifv_pg0_dispdec +// base address: 0x0 +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f +#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0 +#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1 +#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2 +#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4 +#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5 +#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6 +#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa +#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac +#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad +#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae +#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af +#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1 +#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2 +#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3 +#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7 +#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_blndv0_dispdec +// base address: 0x0 +#define mmBLNDV0_BLNDV_CONTROL 0x12db +#define mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2 +#define mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc +#define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2 +#define mmBLNDV0_BLNDV_CONTROL2 0x12dd +#define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2 +#define mmBLNDV0_BLNDV_UPDATE 0x12de +#define mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2 +#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df +#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0 +#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1 +#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtcv0_dispdec +// base address: 0x0 +#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6 +#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTCV0_CRTCV_H_TOTAL 0x12e7 +#define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8 +#define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTCV0_CRTCV_H_SYNC_A 0x12e9 +#define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2 +#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea +#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_H_SYNC_B 0x12eb +#define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2 +#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec +#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VBI_END 0x12ed +#define mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_TOTAL 0x12ee +#define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef +#define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0 +#define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1 +#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2 +#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3 +#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4 +#define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_SYNC_A 0x12f5 +#define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6 +#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_SYNC_B 0x12f7 +#define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8 +#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9 +#define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa +#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb +#define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc +#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd +#define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe +#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff +#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300 +#define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301 +#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302 +#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CONTROL 0x1303 +#define mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304 +#define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305 +#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306 +#define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307 +#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308 +#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309 +#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STATUS 0x130a +#define mmCRTCV0_CRTCV_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STATUS_POSITION 0x130b +#define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c +#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d +#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e +#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f +#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310 +#define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_COUNT_RESET 0x1311 +#define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312 +#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313 +#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STEREO_STATUS 0x1314 +#define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315 +#define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316 +#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317 +#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318 +#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319 +#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a +#define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b +#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c +#define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d +#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e +#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f +#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320 +#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321 +#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322 +#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323 +#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324 +#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325 +#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MVP_STATUS 0x1326 +#define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_MASTER_EN 0x1327 +#define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2 +#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328 +#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329 +#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c +#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d +#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e +#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_BLACK_COLOR 0x132f +#define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2 +#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330 +#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336 +#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC_CNTL 0x1337 +#define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339 +#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b +#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c +#define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d +#define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f +#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340 +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341 +#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342 +#define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343 +#define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349 +#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a +#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b +#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c +#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTCV0_CRTCV_GSL_WINDOW 0x134d +#define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2 +#define mmCRTCV0_CRTCV_GSL_CONTROL 0x134e +#define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_unp1_dispdec +// base address: 0x800 +#define mmUNP1_UNP_GRPH_ENABLE 0x135a +#define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_CONTROL 0x135b +#define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_CONTROL_C 0x135c +#define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d +#define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e +#define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362 +#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366 +#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a +#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e +#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PITCH_L 0x136f +#define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_PITCH_C 0x1370 +#define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374 +#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_X_START_L 0x1375 +#define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_X_START_C 0x1376 +#define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_Y_START_L 0x1377 +#define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_Y_START_C 0x1378 +#define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_X_END_L 0x1379 +#define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_X_END_C 0x137a +#define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_Y_END_L 0x137b +#define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_Y_END_C 0x137c +#define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_UPDATE 0x137d +#define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2 +#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e +#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382 +#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2 +#define mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383 +#define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2 +#define mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384 +#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2 +#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385 +#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2 +#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386 +#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387 +#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388 +#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389 +#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2 +#define mmUNP1_UNP_FLIP_CONTROL 0x138a +#define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2 +#define mmUNP1_UNP_CRC_CONTROL 0x138b +#define mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2 +#define mmUNP1_UNP_CRC_MASK 0x138c +#define mmUNP1_UNP_CRC_MASK_BASE_IDX 2 +#define mmUNP1_UNP_CRC_CURRENT 0x138d +#define mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2 +#define mmUNP1_UNP_CRC_LAST 0x138e +#define mmUNP1_UNP_CRC_LAST_BASE_IDX 2 +#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f +#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2 +#define mmUNP1_UNP_HW_ROTATION 0x1390 +#define mmUNP1_UNP_HW_ROTATION_BASE_IDX 2 + + +// addressBlock: dce_dc_lbv1_dispdec +// base address: 0x800 +#define mmLBV1_LBV_DATA_FORMAT 0x1396 +#define mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2 +#define mmLBV1_LBV_MEMORY_CTRL 0x1397 +#define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2 +#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398 +#define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_DESKTOP_HEIGHT 0x1399 +#define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2 +#define mmLBV1_LBV_VLINE_START_END 0x139a +#define mmLBV1_LBV_VLINE_START_END_BASE_IDX 2 +#define mmLBV1_LBV_VLINE2_START_END 0x139b +#define mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2 +#define mmLBV1_LBV_V_COUNTER 0x139c +#define mmLBV1_LBV_V_COUNTER_BASE_IDX 2 +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2 +#define mmLBV1_LBV_V_COUNTER_CHROMA 0x139e +#define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2 +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f +#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2 +#define mmLBV1_LBV_INTERRUPT_MASK 0x13a0 +#define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2 +#define mmLBV1_LBV_VLINE_STATUS 0x13a1 +#define mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_VLINE2_STATUS 0x13a2 +#define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_VBLANK_STATUS 0x13a3 +#define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_SYNC_RESET_SEL 0x13a4 +#define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2 +#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5 +#define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2 +#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6 +#define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2 +#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7 +#define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8 +#define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9 +#define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa +#define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab +#define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac +#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad +#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2 +#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae +#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2 +#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af +#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0 +#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2 +#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1 +#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_BUFFER_STATUS 0x13b2 +#define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2 +#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3 +#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_sclv1_dispdec +// base address: 0x800 +#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca +#define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2 +#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb +#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmSCLV1_SCLV_MODE 0x13cc +#define mmSCLV1_SCLV_MODE_BASE_IDX 2 +#define mmSCLV1_SCLV_TAP_CONTROL 0x13cd +#define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_CONTROL 0x13ce +#define mmSCLV1_SCLV_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf +#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0 +#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1 +#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4 +#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6 +#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7 +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da +#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db +#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc +#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmSCLV1_SCLV_ROUND_OFFSET 0x13dd +#define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2 +#define mmSCLV1_SCLV_UPDATE 0x13de +#define mmSCLV1_SCLV_UPDATE_BASE_IDX 2 +#define mmSCLV1_SCLV_ALU_CONTROL 0x13df +#define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2 +#define mmSCLV1_SCLV_VIEWPORT_START 0x13e0 +#define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2 +#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2 +#define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2 +#define mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3 +#define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4 +#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2 +#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5 +#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2 +#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6 +#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7 +#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8 +#define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2 +#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9 +#define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2 +#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea +#define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2 +#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb +#define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2 +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed +#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2 + + +// addressBlock: dce_dc_col_man1_dispdec +// base address: 0x800 +#define mmCOL_MAN1_COL_MAN_UPDATE 0x13fe +#define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff +#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404 +#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405 +#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406 +#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407 +#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408 +#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409 +#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a +#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b +#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2 +#define mmCOL_MAN1_PRESCALE_CONTROL 0x140c +#define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_PRESCALE_VALUES_R 0x140d +#define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2 +#define mmCOL_MAN1_PRESCALE_VALUES_G 0x140e +#define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2 +#define mmCOL_MAN1_PRESCALE_VALUES_B 0x140f +#define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410 +#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414 +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415 +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416 +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417 +#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418 +#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419 +#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a +#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b +#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c +#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2 +#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d +#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420 +#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421 +#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425 +#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d +#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2 +#define mmCOL_MAN1_PACK_FIFO_ERROR 0x143e +#define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2 +#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f +#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444 +#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445 +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446 +#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449 +#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a +#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451 +#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2 + + +// addressBlock: dce_dc_dcfev1_dispdec +// base address: 0x800 +#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e +#define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFEV1_DCFEV_SOFT_RESET 0x147f +#define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2 +#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480 +#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483 +#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484 +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485 +#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486 +#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCFEV1_DCFEV_L_FLUSH 0x1487 +#define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2 +#define mmDCFEV1_DCFEV_C_FLUSH 0x1488 +#define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2 +#define mmDCFEV1_DCFEV_MISC 0x148a +#define mmDCFEV1_DCFEV_MISC_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon12_dispdec +// base address: 0x51c8 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494 +#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL 0x1495 +#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL2 0x1496 +#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_HI 0x1499 +#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_LOW 0x149a +#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmifv_pg1_dispdec +// base address: 0x800 +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f +#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0 +#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1 +#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2 +#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4 +#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5 +#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6 +#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa +#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac +#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad +#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae +#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af +#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1 +#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2 +#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3 +#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2 +#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7 +#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_blndv1_dispdec +// base address: 0x800 +#define mmBLNDV1_BLNDV_CONTROL 0x14db +#define mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2 +#define mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc +#define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2 +#define mmBLNDV1_BLNDV_CONTROL2 0x14dd +#define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2 +#define mmBLNDV1_BLNDV_UPDATE 0x14de +#define mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2 +#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df +#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2 +#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0 +#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2 +#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1 +#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_crtcv1_dispdec +// base address: 0x800 +#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6 +#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2 +#define mmCRTCV1_CRTCV_H_TOTAL 0x14e7 +#define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8 +#define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2 +#define mmCRTCV1_CRTCV_H_SYNC_A 0x14e9 +#define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2 +#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea +#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_H_SYNC_B 0x14eb +#define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2 +#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec +#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VBI_END 0x14ed +#define mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_TOTAL 0x14ee +#define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef +#define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0 +#define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1 +#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2 +#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3 +#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4 +#define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_SYNC_A 0x14f5 +#define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6 +#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_SYNC_B 0x14f7 +#define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8 +#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9 +#define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa +#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb +#define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc +#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd +#define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe +#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff +#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500 +#define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501 +#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502 +#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CONTROL 0x1503 +#define mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504 +#define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505 +#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506 +#define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507 +#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508 +#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509 +#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STATUS 0x150a +#define mmCRTCV1_CRTCV_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STATUS_POSITION 0x150b +#define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c +#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d +#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e +#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f +#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510 +#define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_COUNT_RESET 0x1511 +#define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512 +#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513 +#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STEREO_STATUS 0x1514 +#define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515 +#define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516 +#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517 +#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518 +#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519 +#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a +#define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b +#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c +#define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d +#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e +#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f +#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520 +#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521 +#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522 +#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523 +#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524 +#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525 +#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MVP_STATUS 0x1526 +#define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_MASTER_EN 0x1527 +#define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2 +#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528 +#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529 +#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2 +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2 +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c +#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d +#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e +#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_BLACK_COLOR 0x152f +#define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2 +#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530 +#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536 +#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC_CNTL 0x1537 +#define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539 +#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b +#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c +#define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d +#define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f +#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540 +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541 +#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542 +#define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2 +#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543 +#define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549 +#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a +#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b +#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c +#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmCRTCV1_CRTCV_GSL_WINDOW 0x154d +#define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2 +#define mmCRTCV1_CRTCV_GSL_CONTROL 0x154e +#define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpd0_dispdec +// base address: 0x0 +#define mmHPD0_DC_HPD_INT_STATUS 0x1600 +#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1601 +#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_CONTROL 0x1602 +#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpd1_dispdec +// base address: 0x20 +#define mmHPD1_DC_HPD_INT_STATUS 0x1608 +#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD1_DC_HPD_INT_CONTROL 0x1609 +#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_CONTROL 0x160a +#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpd2_dispdec +// base address: 0x40 +#define mmHPD2_DC_HPD_INT_STATUS 0x1610 +#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD2_DC_HPD_INT_CONTROL 0x1611 +#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD2_DC_HPD_CONTROL 0x1612 +#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpd3_dispdec +// base address: 0x60 +#define mmHPD3_DC_HPD_INT_STATUS 0x1618 +#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD3_DC_HPD_INT_CONTROL 0x1619 +#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD3_DC_HPD_CONTROL 0x161a +#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpd4_dispdec +// base address: 0x80 +#define mmHPD4_DC_HPD_INT_STATUS 0x1620 +#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD4_DC_HPD_INT_CONTROL 0x1621 +#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD4_DC_HPD_CONTROL 0x1622 +#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpd5_dispdec +// base address: 0xa0 +#define mmHPD5_DC_HPD_INT_STATUS 0x1628 +#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD5_DC_HPD_INT_CONTROL 0x1629 +#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD5_DC_HPD_CONTROL 0x162a +#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_perfmon2_dispdec +// base address: 0x5840 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632 +#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL 0x1633 +#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL2 0x1634 +#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_HI 0x1637 +#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_LOW 0x1638 +#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dp_aux0_dispdec +// base address: 0x0 +#define mmDP_AUX0_AUX_CONTROL 0x1766 +#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1767 +#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1768 +#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_STATUS 0x176a +#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_STATUS 0x176b +#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_DATA 0x176c +#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_DATA 0x176d +#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dp_aux1_dispdec +// base address: 0x70 +#define mmDP_AUX1_AUX_CONTROL 0x1782 +#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1783 +#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1784 +#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_STATUS 0x1786 +#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_STATUS 0x1787 +#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_DATA 0x1788 +#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_DATA 0x1789 +#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e +#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f +#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dp_aux2_dispdec +// base address: 0xe0 +#define mmDP_AUX2_AUX_CONTROL 0x179e +#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_CONTROL 0x179f +#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x17a0 +#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_STATUS 0x17a2 +#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_LS_STATUS 0x17a3 +#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_DATA 0x17a4 +#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX2_AUX_LS_DATA 0x17a5 +#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa +#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab +#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dp_aux3_dispdec +// base address: 0x150 +#define mmDP_AUX3_AUX_CONTROL 0x17ba +#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_CONTROL 0x17bb +#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_ARB_CONTROL 0x17bc +#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_STATUS 0x17be +#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_LS_STATUS 0x17bf +#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_DATA 0x17c0 +#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX3_AUX_LS_DATA 0x17c1 +#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dp_aux4_dispdec +// base address: 0x1c0 +#define mmDP_AUX4_AUX_CONTROL 0x17d6 +#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_CONTROL 0x17d7 +#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x17d8 +#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_STATUS 0x17da +#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_LS_STATUS 0x17db +#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_DATA 0x17dc +#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX4_AUX_LS_DATA 0x17dd +#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dp_aux5_dispdec +// base address: 0x230 +#define mmDP_AUX5_AUX_CONTROL 0x17f2 +#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_SW_CONTROL 0x17f3 +#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x17f4 +#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_SW_STATUS 0x17f6 +#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_LS_STATUS 0x17f7 +#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_SW_DATA 0x17f8 +#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX5_AUX_LS_DATA 0x17f9 +#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe +#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff +#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801 +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig0_dispdec +// base address: 0x0 +#define mmDIG0_DIG_FE_CNTL 0x187e +#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f +#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_DIG_CLOCK_PATTERN 0x1881 +#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_TEST_PATTERN 0x1882 +#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG0_DIG_FIFO_STATUS 0x1884 +#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_CONTROL 0x1887 +#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_STATUS 0x1888 +#define mmDIG0_HDMI_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a +#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b +#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c +#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d +#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x188f +#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_GC 0x1891 +#define mmDIG0_HDMI_GC_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_0 0x1893 +#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_1 0x1894 +#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_2 0x1895 +#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_3 0x1896 +#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_4 0x1897 +#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_0 0x1898 +#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_1 0x1899 +#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_2 0x189a +#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_3 0x189b +#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG0_AFMT_AVI_INFO0 0x189c +#define mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_AVI_INFO1 0x189d +#define mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_AVI_INFO2 0x189e +#define mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG0_AFMT_AVI_INFO3 0x189f +#define mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG0_AFMT_MPEG_INFO0 0x18a0 +#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_MPEG_INFO1 0x18a1 +#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_HDR 0x18a2 +#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_0 0x18a3 +#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_1 0x18a4 +#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_2 0x18a5 +#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_3 0x18a6 +#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_4 0x18a7 +#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_5 0x18a8 +#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_6 0x18a9 +#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_7 0x18aa +#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_0 0x18ac +#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_1 0x18ad +#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_0 0x18ae +#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_1 0x18af +#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_0 0x18b0 +#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_1 0x18b1 +#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_0 0x18b2 +#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_1 0x18b3 +#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_INFO0 0x18b4 +#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_INFO1 0x18b5 +#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_60958_0 0x18b6 +#define mmDIG0_AFMT_60958_0_BASE_IDX 2 +#define mmDIG0_AFMT_60958_1 0x18b7 +#define mmDIG0_AFMT_60958_1_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x18b9 +#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x18ba +#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x18bb +#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x18bc +#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG0_AFMT_60958_2 0x18bd +#define mmDIG0_AFMT_60958_2_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be +#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_AFMT_STATUS 0x18bf +#define mmDIG0_AFMT_STATUS_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG0_DIG_BE_CNTL 0x18c5 +#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_BE_EN_CNTL 0x18c6 +#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CNTL 0x18e9 +#define mmDIG0_TMDS_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL_CHAR 0x18ea +#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb +#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG0_TMDS_CTL_BITS 0x18f0 +#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1 +#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_VERSION 0x18f6 +#define mmDIG0_DIG_VERSION_BASE_IDX 2 +#define mmDIG0_DIG_LANE_ENABLE 0x18f7 +#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG0_AFMT_CNTL 0x18fc +#define mmDIG0_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp0_dispdec +// base address: 0x0 +#define mmDP0_DP_LINK_CNTL 0x191e +#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP0_DP_PIXEL_FORMAT 0x191f +#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP0_DP_MSA_COLORIMETRY 0x1920 +#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP0_DP_CONFIG 0x1921 +#define mmDP0_DP_CONFIG_BASE_IDX 2 +#define mmDP0_DP_VID_STREAM_CNTL 0x1922 +#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_STEER_FIFO 0x1923 +#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP0_DP_MSA_MISC 0x1924 +#define mmDP0_DP_MSA_MISC_BASE_IDX 2 +#define mmDP0_DP_VID_TIMING 0x1926 +#define mmDP0_DP_VID_TIMING_BASE_IDX 2 +#define mmDP0_DP_VID_N 0x1927 +#define mmDP0_DP_VID_N_BASE_IDX 2 +#define mmDP0_DP_VID_M 0x1928 +#define mmDP0_DP_VID_M_BASE_IDX 2 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x1929 +#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x192a +#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP0_DP_VID_MSA_VBID 0x192b +#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x192c +#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CNTL 0x192d +#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM0 0x192f +#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM1 0x1930 +#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM2 0x1931 +#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x1932 +#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x1933 +#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1934 +#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_EN 0x1935 +#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_CNTL 0x1936 +#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_RESULT 0x1937 +#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938 +#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939 +#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x193a +#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL 0x1941 +#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL1 0x1942 +#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING1 0x1943 +#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING2 0x1944 +#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING3 0x1945 +#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING4 0x1946 +#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N 0x1947 +#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x1948 +#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M 0x1949 +#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x194a +#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_TIMESTAMP 0x194b +#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP0_DP_SEC_PACKET_CNTL 0x194c +#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_CNTL 0x194d +#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_UPDATE 0x194f +#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0 0x1950 +#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1 0x1951 +#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2 0x1952 +#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT_UPDATE 0x1953 +#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_LINK_TIMING 0x1954 +#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP0_DP_MSE_MISC_CNTL 0x1955 +#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0_STATUS 0x195d +#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1_STATUS 0x195e +#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2_STATUS 0x195f +#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig1_dispdec +// base address: 0x400 +#define mmDIG1_DIG_FE_CNTL 0x197e +#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f +#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_DIG_CLOCK_PATTERN 0x1981 +#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_TEST_PATTERN 0x1982 +#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG1_DIG_FIFO_STATUS 0x1984 +#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_CONTROL 0x1987 +#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_STATUS 0x1988 +#define mmDIG1_HDMI_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a +#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b +#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c +#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d +#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x198f +#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_GC 0x1991 +#define mmDIG1_HDMI_GC_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_0 0x1993 +#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_1 0x1994 +#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_2 0x1995 +#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_3 0x1996 +#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_4 0x1997 +#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_0 0x1998 +#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_1 0x1999 +#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_2 0x199a +#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_3 0x199b +#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG1_AFMT_AVI_INFO0 0x199c +#define mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_AVI_INFO1 0x199d +#define mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_AVI_INFO2 0x199e +#define mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG1_AFMT_AVI_INFO3 0x199f +#define mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG1_AFMT_MPEG_INFO0 0x19a0 +#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_MPEG_INFO1 0x19a1 +#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_HDR 0x19a2 +#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_0 0x19a3 +#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_1 0x19a4 +#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_2 0x19a5 +#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_3 0x19a6 +#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_4 0x19a7 +#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_5 0x19a8 +#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_6 0x19a9 +#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_7 0x19aa +#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_0 0x19ac +#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_1 0x19ad +#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_0 0x19ae +#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_1 0x19af +#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_0 0x19b0 +#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_1 0x19b1 +#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_0 0x19b2 +#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_1 0x19b3 +#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_INFO0 0x19b4 +#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_INFO1 0x19b5 +#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_60958_0 0x19b6 +#define mmDIG1_AFMT_60958_0_BASE_IDX 2 +#define mmDIG1_AFMT_60958_1 0x19b7 +#define mmDIG1_AFMT_60958_1_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x19b9 +#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x19ba +#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x19bb +#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x19bc +#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG1_AFMT_60958_2 0x19bd +#define mmDIG1_AFMT_60958_2_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be +#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_AFMT_STATUS 0x19bf +#define mmDIG1_AFMT_STATUS_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG1_DIG_BE_CNTL 0x19c5 +#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_BE_EN_CNTL 0x19c6 +#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CNTL 0x19e9 +#define mmDIG1_TMDS_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL_CHAR 0x19ea +#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb +#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG1_TMDS_CTL_BITS 0x19f0 +#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1 +#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_VERSION 0x19f6 +#define mmDIG1_DIG_VERSION_BASE_IDX 2 +#define mmDIG1_DIG_LANE_ENABLE 0x19f7 +#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG1_AFMT_CNTL 0x19fc +#define mmDIG1_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp1_dispdec +// base address: 0x400 +#define mmDP1_DP_LINK_CNTL 0x1a1e +#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP1_DP_PIXEL_FORMAT 0x1a1f +#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP1_DP_MSA_COLORIMETRY 0x1a20 +#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP1_DP_CONFIG 0x1a21 +#define mmDP1_DP_CONFIG_BASE_IDX 2 +#define mmDP1_DP_VID_STREAM_CNTL 0x1a22 +#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_STEER_FIFO 0x1a23 +#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP1_DP_MSA_MISC 0x1a24 +#define mmDP1_DP_MSA_MISC_BASE_IDX 2 +#define mmDP1_DP_VID_TIMING 0x1a26 +#define mmDP1_DP_VID_TIMING_BASE_IDX 2 +#define mmDP1_DP_VID_N 0x1a27 +#define mmDP1_DP_VID_N_BASE_IDX 2 +#define mmDP1_DP_VID_M 0x1a28 +#define mmDP1_DP_VID_M_BASE_IDX 2 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x1a29 +#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a +#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP1_DP_VID_MSA_VBID 0x1a2b +#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c +#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CNTL 0x1a2d +#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM0 0x1a2f +#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM1 0x1a30 +#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM2 0x1a31 +#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x1a32 +#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x1a33 +#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34 +#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_EN 0x1a35 +#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_CNTL 0x1a36 +#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_RESULT 0x1a37 +#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38 +#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39 +#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a +#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL 0x1a41 +#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL1 0x1a42 +#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING1 0x1a43 +#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING2 0x1a44 +#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING3 0x1a45 +#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING4 0x1a46 +#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N 0x1a47 +#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x1a48 +#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M 0x1a49 +#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a +#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_TIMESTAMP 0x1a4b +#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP1_DP_SEC_PACKET_CNTL 0x1a4c +#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_CNTL 0x1a4d +#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_UPDATE 0x1a4f +#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0 0x1a50 +#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1 0x1a51 +#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2 0x1a52 +#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT_UPDATE 0x1a53 +#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_LINK_TIMING 0x1a54 +#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP1_DP_MSE_MISC_CNTL 0x1a55 +#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0_STATUS 0x1a5d +#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1_STATUS 0x1a5e +#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2_STATUS 0x1a5f +#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig2_dispdec +// base address: 0x800 +#define mmDIG2_DIG_FE_CNTL 0x1a7e +#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f +#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG2_DIG_CLOCK_PATTERN 0x1a81 +#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG2_DIG_TEST_PATTERN 0x1a82 +#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG2_DIG_FIFO_STATUS 0x1a84 +#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_CONTROL 0x1a87 +#define mmDIG2_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_STATUS 0x1a88 +#define mmDIG2_HDMI_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a +#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b +#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c +#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d +#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f +#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_GC 0x1a91 +#define mmDIG2_HDMI_GC_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_0 0x1a93 +#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_1 0x1a94 +#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_2 0x1a95 +#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_3 0x1a96 +#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_4 0x1a97 +#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_0 0x1a98 +#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_1 0x1a99 +#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_2 0x1a9a +#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_3 0x1a9b +#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG2_AFMT_AVI_INFO0 0x1a9c +#define mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_AVI_INFO1 0x1a9d +#define mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_AVI_INFO2 0x1a9e +#define mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG2_AFMT_AVI_INFO3 0x1a9f +#define mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG2_AFMT_MPEG_INFO0 0x1aa0 +#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_MPEG_INFO1 0x1aa1 +#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_HDR 0x1aa2 +#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_0 0x1aa3 +#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_1 0x1aa4 +#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_2 0x1aa5 +#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_3 0x1aa6 +#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_4 0x1aa7 +#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_5 0x1aa8 +#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_6 0x1aa9 +#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_7 0x1aaa +#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_32_0 0x1aac +#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_32_1 0x1aad +#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_44_0 0x1aae +#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_44_1 0x1aaf +#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_48_0 0x1ab0 +#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_48_1 0x1ab1 +#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_STATUS_0 0x1ab2 +#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_STATUS_1 0x1ab3 +#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_INFO0 0x1ab4 +#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_INFO1 0x1ab5 +#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_60958_0 0x1ab6 +#define mmDIG2_AFMT_60958_0_BASE_IDX 2 +#define mmDIG2_AFMT_60958_1 0x1ab7 +#define mmDIG2_AFMT_60958_1_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9 +#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x1aba +#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x1abb +#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x1abc +#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG2_AFMT_60958_2 0x1abd +#define mmDIG2_AFMT_60958_2_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe +#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG2_AFMT_STATUS 0x1abf +#define mmDIG2_AFMT_STATUS_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG2_DIG_BE_CNTL 0x1ac5 +#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_BE_EN_CNTL 0x1ac6 +#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CNTL 0x1ae9 +#define mmDIG2_TMDS_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CONTROL_CHAR 0x1aea +#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb +#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG2_TMDS_CTL_BITS 0x1af0 +#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1 +#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_VERSION 0x1af6 +#define mmDIG2_DIG_VERSION_BASE_IDX 2 +#define mmDIG2_DIG_LANE_ENABLE 0x1af7 +#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG2_AFMT_CNTL 0x1afc +#define mmDIG2_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp2_dispdec +// base address: 0x800 +#define mmDP2_DP_LINK_CNTL 0x1b1e +#define mmDP2_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP2_DP_PIXEL_FORMAT 0x1b1f +#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP2_DP_MSA_COLORIMETRY 0x1b20 +#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP2_DP_CONFIG 0x1b21 +#define mmDP2_DP_CONFIG_BASE_IDX 2 +#define mmDP2_DP_VID_STREAM_CNTL 0x1b22 +#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP2_DP_STEER_FIFO 0x1b23 +#define mmDP2_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP2_DP_MSA_MISC 0x1b24 +#define mmDP2_DP_MSA_MISC_BASE_IDX 2 +#define mmDP2_DP_VID_TIMING 0x1b26 +#define mmDP2_DP_VID_TIMING_BASE_IDX 2 +#define mmDP2_DP_VID_N 0x1b27 +#define mmDP2_DP_VID_N_BASE_IDX 2 +#define mmDP2_DP_VID_M 0x1b28 +#define mmDP2_DP_VID_M_BASE_IDX 2 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x1b29 +#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a +#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP2_DP_VID_MSA_VBID 0x1b2b +#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c +#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CNTL 0x1b2d +#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM0 0x1b2f +#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM1 0x1b30 +#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM2 0x1b31 +#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x1b32 +#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x1b33 +#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34 +#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_EN 0x1b35 +#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_CNTL 0x1b36 +#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_RESULT 0x1b37 +#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38 +#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39 +#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a +#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL 0x1b41 +#define mmDP2_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL1 0x1b42 +#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING1 0x1b43 +#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING2 0x1b44 +#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING3 0x1b45 +#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING4 0x1b46 +#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_N 0x1b47 +#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x1b48 +#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_M 0x1b49 +#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a +#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP2_DP_SEC_TIMESTAMP 0x1b4b +#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP2_DP_SEC_PACKET_CNTL 0x1b4c +#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSE_RATE_CNTL 0x1b4d +#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSE_RATE_UPDATE 0x1b4f +#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT0 0x1b50 +#define mmDP2_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT1 0x1b51 +#define mmDP2_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT2 0x1b52 +#define mmDP2_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT_UPDATE 0x1b53 +#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP2_DP_MSE_LINK_TIMING 0x1b54 +#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP2_DP_MSE_MISC_CNTL 0x1b55 +#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT0_STATUS 0x1b5d +#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT1_STATUS 0x1b5e +#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT2_STATUS 0x1b5f +#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig3_dispdec +// base address: 0xc00 +#define mmDIG3_DIG_FE_CNTL 0x1b7e +#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f +#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG3_DIG_CLOCK_PATTERN 0x1b81 +#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG3_DIG_TEST_PATTERN 0x1b82 +#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG3_DIG_FIFO_STATUS 0x1b84 +#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_CONTROL 0x1b87 +#define mmDIG3_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_STATUS 0x1b88 +#define mmDIG3_HDMI_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a +#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b +#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c +#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d +#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f +#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_GC 0x1b91 +#define mmDIG3_HDMI_GC_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_0 0x1b93 +#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_1 0x1b94 +#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_2 0x1b95 +#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_3 0x1b96 +#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_4 0x1b97 +#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_0 0x1b98 +#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_1 0x1b99 +#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_2 0x1b9a +#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_3 0x1b9b +#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG3_AFMT_AVI_INFO0 0x1b9c +#define mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_AVI_INFO1 0x1b9d +#define mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_AVI_INFO2 0x1b9e +#define mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG3_AFMT_AVI_INFO3 0x1b9f +#define mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG3_AFMT_MPEG_INFO0 0x1ba0 +#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_MPEG_INFO1 0x1ba1 +#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_HDR 0x1ba2 +#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_0 0x1ba3 +#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_1 0x1ba4 +#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_2 0x1ba5 +#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_3 0x1ba6 +#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_4 0x1ba7 +#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_5 0x1ba8 +#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_6 0x1ba9 +#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_7 0x1baa +#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_32_0 0x1bac +#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_32_1 0x1bad +#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_44_0 0x1bae +#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_44_1 0x1baf +#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_48_0 0x1bb0 +#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_48_1 0x1bb1 +#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_STATUS_0 0x1bb2 +#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_STATUS_1 0x1bb3 +#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_INFO0 0x1bb4 +#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_INFO1 0x1bb5 +#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_60958_0 0x1bb6 +#define mmDIG3_AFMT_60958_0_BASE_IDX 2 +#define mmDIG3_AFMT_60958_1 0x1bb7 +#define mmDIG3_AFMT_60958_1_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9 +#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x1bba +#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb +#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc +#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG3_AFMT_60958_2 0x1bbd +#define mmDIG3_AFMT_60958_2_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe +#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG3_AFMT_STATUS 0x1bbf +#define mmDIG3_AFMT_STATUS_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG3_DIG_BE_CNTL 0x1bc5 +#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_BE_EN_CNTL 0x1bc6 +#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CNTL 0x1be9 +#define mmDIG3_TMDS_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CONTROL_CHAR 0x1bea +#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb +#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG3_TMDS_CTL_BITS 0x1bf0 +#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1 +#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_VERSION 0x1bf6 +#define mmDIG3_DIG_VERSION_BASE_IDX 2 +#define mmDIG3_DIG_LANE_ENABLE 0x1bf7 +#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG3_AFMT_CNTL 0x1bfc +#define mmDIG3_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp3_dispdec +// base address: 0xc00 +#define mmDP3_DP_LINK_CNTL 0x1c1e +#define mmDP3_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP3_DP_PIXEL_FORMAT 0x1c1f +#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP3_DP_MSA_COLORIMETRY 0x1c20 +#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP3_DP_CONFIG 0x1c21 +#define mmDP3_DP_CONFIG_BASE_IDX 2 +#define mmDP3_DP_VID_STREAM_CNTL 0x1c22 +#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP3_DP_STEER_FIFO 0x1c23 +#define mmDP3_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP3_DP_MSA_MISC 0x1c24 +#define mmDP3_DP_MSA_MISC_BASE_IDX 2 +#define mmDP3_DP_VID_TIMING 0x1c26 +#define mmDP3_DP_VID_TIMING_BASE_IDX 2 +#define mmDP3_DP_VID_N 0x1c27 +#define mmDP3_DP_VID_N_BASE_IDX 2 +#define mmDP3_DP_VID_M 0x1c28 +#define mmDP3_DP_VID_M_BASE_IDX 2 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x1c29 +#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a +#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP3_DP_VID_MSA_VBID 0x1c2b +#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c +#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CNTL 0x1c2d +#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM0 0x1c2f +#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM1 0x1c30 +#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM2 0x1c31 +#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x1c32 +#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x1c33 +#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34 +#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_EN 0x1c35 +#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_CNTL 0x1c36 +#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_RESULT 0x1c37 +#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38 +#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39 +#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a +#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL 0x1c41 +#define mmDP3_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL1 0x1c42 +#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING1 0x1c43 +#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING2 0x1c44 +#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING3 0x1c45 +#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING4 0x1c46 +#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_N 0x1c47 +#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x1c48 +#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_M 0x1c49 +#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a +#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP3_DP_SEC_TIMESTAMP 0x1c4b +#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP3_DP_SEC_PACKET_CNTL 0x1c4c +#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSE_RATE_CNTL 0x1c4d +#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSE_RATE_UPDATE 0x1c4f +#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT0 0x1c50 +#define mmDP3_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT1 0x1c51 +#define mmDP3_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT2 0x1c52 +#define mmDP3_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT_UPDATE 0x1c53 +#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP3_DP_MSE_LINK_TIMING 0x1c54 +#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP3_DP_MSE_MISC_CNTL 0x1c55 +#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT0_STATUS 0x1c5d +#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT1_STATUS 0x1c5e +#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT2_STATUS 0x1c5f +#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig4_dispdec +// base address: 0x1000 +#define mmDIG4_DIG_FE_CNTL 0x1c7e +#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f +#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG4_DIG_CLOCK_PATTERN 0x1c81 +#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG4_DIG_TEST_PATTERN 0x1c82 +#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG4_DIG_FIFO_STATUS 0x1c84 +#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_CONTROL 0x1c87 +#define mmDIG4_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_STATUS 0x1c88 +#define mmDIG4_HDMI_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a +#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b +#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c +#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d +#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f +#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_GC 0x1c91 +#define mmDIG4_HDMI_GC_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_0 0x1c93 +#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_1 0x1c94 +#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_2 0x1c95 +#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_3 0x1c96 +#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_4 0x1c97 +#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_0 0x1c98 +#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_1 0x1c99 +#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_2 0x1c9a +#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_3 0x1c9b +#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG4_AFMT_AVI_INFO0 0x1c9c +#define mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_AVI_INFO1 0x1c9d +#define mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_AVI_INFO2 0x1c9e +#define mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG4_AFMT_AVI_INFO3 0x1c9f +#define mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG4_AFMT_MPEG_INFO0 0x1ca0 +#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_MPEG_INFO1 0x1ca1 +#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_HDR 0x1ca2 +#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_0 0x1ca3 +#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_1 0x1ca4 +#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_2 0x1ca5 +#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_3 0x1ca6 +#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_4 0x1ca7 +#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_5 0x1ca8 +#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_6 0x1ca9 +#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_7 0x1caa +#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_32_0 0x1cac +#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_32_1 0x1cad +#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_44_0 0x1cae +#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_44_1 0x1caf +#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_48_0 0x1cb0 +#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_48_1 0x1cb1 +#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_STATUS_0 0x1cb2 +#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_STATUS_1 0x1cb3 +#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_INFO0 0x1cb4 +#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_INFO1 0x1cb5 +#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_60958_0 0x1cb6 +#define mmDIG4_AFMT_60958_0_BASE_IDX 2 +#define mmDIG4_AFMT_60958_1 0x1cb7 +#define mmDIG4_AFMT_60958_1_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9 +#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x1cba +#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb +#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc +#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG4_AFMT_60958_2 0x1cbd +#define mmDIG4_AFMT_60958_2_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe +#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG4_AFMT_STATUS 0x1cbf +#define mmDIG4_AFMT_STATUS_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG4_DIG_BE_CNTL 0x1cc5 +#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_BE_EN_CNTL 0x1cc6 +#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CNTL 0x1ce9 +#define mmDIG4_TMDS_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CONTROL_CHAR 0x1cea +#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb +#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG4_TMDS_CTL_BITS 0x1cf0 +#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1 +#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_VERSION 0x1cf6 +#define mmDIG4_DIG_VERSION_BASE_IDX 2 +#define mmDIG4_DIG_LANE_ENABLE 0x1cf7 +#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG4_AFMT_CNTL 0x1cfc +#define mmDIG4_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp4_dispdec +// base address: 0x1000 +#define mmDP4_DP_LINK_CNTL 0x1d1e +#define mmDP4_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP4_DP_PIXEL_FORMAT 0x1d1f +#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP4_DP_MSA_COLORIMETRY 0x1d20 +#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP4_DP_CONFIG 0x1d21 +#define mmDP4_DP_CONFIG_BASE_IDX 2 +#define mmDP4_DP_VID_STREAM_CNTL 0x1d22 +#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP4_DP_STEER_FIFO 0x1d23 +#define mmDP4_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP4_DP_MSA_MISC 0x1d24 +#define mmDP4_DP_MSA_MISC_BASE_IDX 2 +#define mmDP4_DP_VID_TIMING 0x1d26 +#define mmDP4_DP_VID_TIMING_BASE_IDX 2 +#define mmDP4_DP_VID_N 0x1d27 +#define mmDP4_DP_VID_N_BASE_IDX 2 +#define mmDP4_DP_VID_M 0x1d28 +#define mmDP4_DP_VID_M_BASE_IDX 2 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x1d29 +#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a +#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP4_DP_VID_MSA_VBID 0x1d2b +#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c +#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CNTL 0x1d2d +#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM0 0x1d2f +#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM1 0x1d30 +#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM2 0x1d31 +#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x1d32 +#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x1d33 +#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34 +#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_EN 0x1d35 +#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_CNTL 0x1d36 +#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_RESULT 0x1d37 +#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38 +#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39 +#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a +#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL 0x1d41 +#define mmDP4_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL1 0x1d42 +#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING1 0x1d43 +#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING2 0x1d44 +#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING3 0x1d45 +#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING4 0x1d46 +#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_N 0x1d47 +#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x1d48 +#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_M 0x1d49 +#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a +#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP4_DP_SEC_TIMESTAMP 0x1d4b +#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP4_DP_SEC_PACKET_CNTL 0x1d4c +#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSE_RATE_CNTL 0x1d4d +#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSE_RATE_UPDATE 0x1d4f +#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT0 0x1d50 +#define mmDP4_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT1 0x1d51 +#define mmDP4_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT2 0x1d52 +#define mmDP4_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT_UPDATE 0x1d53 +#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP4_DP_MSE_LINK_TIMING 0x1d54 +#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP4_DP_MSE_MISC_CNTL 0x1d55 +#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT0_STATUS 0x1d5d +#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT1_STATUS 0x1d5e +#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT2_STATUS 0x1d5f +#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig5_dispdec +// base address: 0x1400 +#define mmDIG5_DIG_FE_CNTL 0x1d7e +#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f +#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG5_DIG_CLOCK_PATTERN 0x1d81 +#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG5_DIG_TEST_PATTERN 0x1d82 +#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG5_DIG_FIFO_STATUS 0x1d84 +#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG5_HDMI_CONTROL 0x1d87 +#define mmDIG5_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_STATUS 0x1d88 +#define mmDIG5_HDMI_STATUS_BASE_IDX 2 +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89 +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a +#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b +#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c +#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d +#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f +#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG5_HDMI_GC 0x1d91 +#define mmDIG5_HDMI_GC_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_0 0x1d93 +#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_1 0x1d94 +#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_2 0x1d95 +#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_3 0x1d96 +#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC1_4 0x1d97 +#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_0 0x1d98 +#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_1 0x1d99 +#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_2 0x1d9a +#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG5_AFMT_ISRC2_3 0x1d9b +#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG5_AFMT_AVI_INFO0 0x1d9c +#define mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG5_AFMT_AVI_INFO1 0x1d9d +#define mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG5_AFMT_AVI_INFO2 0x1d9e +#define mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG5_AFMT_AVI_INFO3 0x1d9f +#define mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG5_AFMT_MPEG_INFO0 0x1da0 +#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG5_AFMT_MPEG_INFO1 0x1da1 +#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_HDR 0x1da2 +#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_0 0x1da3 +#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_1 0x1da4 +#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_2 0x1da5 +#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_3 0x1da6 +#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_4 0x1da7 +#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_5 0x1da8 +#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_6 0x1da9 +#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG5_AFMT_GENERIC_7 0x1daa +#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_32_0 0x1dac +#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_32_1 0x1dad +#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_44_0 0x1dae +#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_44_1 0x1daf +#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_48_0 0x1db0 +#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_48_1 0x1db1 +#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_STATUS_0 0x1db2 +#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG5_HDMI_ACR_STATUS_1 0x1db3 +#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_INFO0 0x1db4 +#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_INFO1 0x1db5 +#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG5_AFMT_60958_0 0x1db6 +#define mmDIG5_AFMT_60958_0_BASE_IDX 2 +#define mmDIG5_AFMT_60958_1 0x1db7 +#define mmDIG5_AFMT_60958_1_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x1db9 +#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x1dba +#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb +#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc +#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG5_AFMT_60958_2 0x1dbd +#define mmDIG5_AFMT_60958_2_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe +#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG5_AFMT_STATUS 0x1dbf +#define mmDIG5_AFMT_STATUS_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG5_DIG_BE_CNTL 0x1dc5 +#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_BE_EN_CNTL 0x1dc6 +#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG5_TMDS_CNTL 0x1de9 +#define mmDIG5_TMDS_CNTL_BASE_IDX 2 +#define mmDIG5_TMDS_CONTROL_CHAR 0x1dea +#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb +#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG5_TMDS_CTL_BITS 0x1df0 +#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1 +#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG5_DIG_VERSION 0x1df6 +#define mmDIG5_DIG_VERSION_BASE_IDX 2 +#define mmDIG5_DIG_LANE_ENABLE 0x1df7 +#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG5_AFMT_CNTL 0x1dfc +#define mmDIG5_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp5_dispdec +// base address: 0x1400 +#define mmDP5_DP_LINK_CNTL 0x1e1e +#define mmDP5_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP5_DP_PIXEL_FORMAT 0x1e1f +#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP5_DP_MSA_COLORIMETRY 0x1e20 +#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP5_DP_CONFIG 0x1e21 +#define mmDP5_DP_CONFIG_BASE_IDX 2 +#define mmDP5_DP_VID_STREAM_CNTL 0x1e22 +#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP5_DP_STEER_FIFO 0x1e23 +#define mmDP5_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP5_DP_MSA_MISC 0x1e24 +#define mmDP5_DP_MSA_MISC_BASE_IDX 2 +#define mmDP5_DP_VID_TIMING 0x1e26 +#define mmDP5_DP_VID_TIMING_BASE_IDX 2 +#define mmDP5_DP_VID_N 0x1e27 +#define mmDP5_DP_VID_N_BASE_IDX 2 +#define mmDP5_DP_VID_M 0x1e28 +#define mmDP5_DP_VID_M_BASE_IDX 2 +#define mmDP5_DP_LINK_FRAMING_CNTL 0x1e29 +#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a +#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP5_DP_VID_MSA_VBID 0x1e2b +#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c +#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CNTL 0x1e2d +#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP5_DP_DPHY_SYM0 0x1e2f +#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP5_DP_DPHY_SYM1 0x1e30 +#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP5_DP_DPHY_SYM2 0x1e31 +#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x1e32 +#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x1e33 +#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34 +#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_EN 0x1e35 +#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_CNTL 0x1e36 +#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_RESULT 0x1e37 +#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38 +#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39 +#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a +#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL 0x1e41 +#define mmDP5_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP5_DP_SEC_CNTL1 0x1e42 +#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING1 0x1e43 +#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING2 0x1e44 +#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING3 0x1e45 +#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP5_DP_SEC_FRAMING4 0x1e46 +#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_N 0x1e47 +#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x1e48 +#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_M 0x1e49 +#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a +#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP5_DP_SEC_TIMESTAMP 0x1e4b +#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP5_DP_SEC_PACKET_CNTL 0x1e4c +#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP5_DP_MSE_RATE_CNTL 0x1e4d +#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP5_DP_MSE_RATE_UPDATE 0x1e4f +#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT0 0x1e50 +#define mmDP5_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT1 0x1e51 +#define mmDP5_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT2 0x1e52 +#define mmDP5_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT_UPDATE 0x1e53 +#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP5_DP_MSE_LINK_TIMING 0x1e54 +#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP5_DP_MSE_MISC_CNTL 0x1e55 +#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT0_STATUS 0x1e5d +#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT1_STATUS 0x1e5e +#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP5_DP_MSE_SAT2_STATUS 0x1e5f +#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dig6_dispdec +// base address: 0x1800 +#define mmDIG6_DIG_FE_CNTL 0x1e7e +#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f +#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG6_DIG_CLOCK_PATTERN 0x1e81 +#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG6_DIG_TEST_PATTERN 0x1e82 +#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG6_DIG_FIFO_STATUS 0x1e84 +#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG6_HDMI_CONTROL 0x1e87 +#define mmDIG6_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_STATUS 0x1e88 +#define mmDIG6_HDMI_STATUS_BASE_IDX 2 +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89 +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a +#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b +#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c +#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d +#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f +#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG6_HDMI_GC 0x1e91 +#define mmDIG6_HDMI_GC_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_0 0x1e93 +#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_1 0x1e94 +#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_2 0x1e95 +#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_3 0x1e96 +#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC1_4 0x1e97 +#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_0 0x1e98 +#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_1 0x1e99 +#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_2 0x1e9a +#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG6_AFMT_ISRC2_3 0x1e9b +#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG6_AFMT_AVI_INFO0 0x1e9c +#define mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2 +#define mmDIG6_AFMT_AVI_INFO1 0x1e9d +#define mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2 +#define mmDIG6_AFMT_AVI_INFO2 0x1e9e +#define mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2 +#define mmDIG6_AFMT_AVI_INFO3 0x1e9f +#define mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2 +#define mmDIG6_AFMT_MPEG_INFO0 0x1ea0 +#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG6_AFMT_MPEG_INFO1 0x1ea1 +#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_HDR 0x1ea2 +#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_0 0x1ea3 +#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_1 0x1ea4 +#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_2 0x1ea5 +#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_3 0x1ea6 +#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_4 0x1ea7 +#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_5 0x1ea8 +#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_6 0x1ea9 +#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG6_AFMT_GENERIC_7 0x1eaa +#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_32_0 0x1eac +#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_32_1 0x1ead +#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_44_0 0x1eae +#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_44_1 0x1eaf +#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_48_0 0x1eb0 +#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_48_1 0x1eb1 +#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_STATUS_0 0x1eb2 +#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG6_HDMI_ACR_STATUS_1 0x1eb3 +#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_INFO0 0x1eb4 +#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_INFO1 0x1eb5 +#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG6_AFMT_60958_0 0x1eb6 +#define mmDIG6_AFMT_60958_0_BASE_IDX 2 +#define mmDIG6_AFMT_60958_1 0x1eb7 +#define mmDIG6_AFMT_60958_1_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9 +#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL1 0x1eba +#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb +#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc +#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG6_AFMT_60958_2 0x1ebd +#define mmDIG6_AFMT_60958_2_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe +#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG6_AFMT_STATUS 0x1ebf +#define mmDIG6_AFMT_STATUS_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG6_DIG_BE_CNTL 0x1ec5 +#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_BE_EN_CNTL 0x1ec6 +#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG6_TMDS_CNTL 0x1ee9 +#define mmDIG6_TMDS_CNTL_BASE_IDX 2 +#define mmDIG6_TMDS_CONTROL_CHAR 0x1eea +#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb +#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG6_TMDS_CTL_BITS 0x1ef0 +#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1 +#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG6_DIG_VERSION 0x1ef6 +#define mmDIG6_DIG_VERSION_BASE_IDX 2 +#define mmDIG6_DIG_LANE_ENABLE 0x1ef7 +#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG6_AFMT_CNTL 0x1efc +#define mmDIG6_AFMT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dp6_dispdec +// base address: 0x1800 +#define mmDP6_DP_LINK_CNTL 0x1f1e +#define mmDP6_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP6_DP_PIXEL_FORMAT 0x1f1f +#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP6_DP_MSA_COLORIMETRY 0x1f20 +#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP6_DP_CONFIG 0x1f21 +#define mmDP6_DP_CONFIG_BASE_IDX 2 +#define mmDP6_DP_VID_STREAM_CNTL 0x1f22 +#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP6_DP_STEER_FIFO 0x1f23 +#define mmDP6_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP6_DP_MSA_MISC 0x1f24 +#define mmDP6_DP_MSA_MISC_BASE_IDX 2 +#define mmDP6_DP_VID_TIMING 0x1f26 +#define mmDP6_DP_VID_TIMING_BASE_IDX 2 +#define mmDP6_DP_VID_N 0x1f27 +#define mmDP6_DP_VID_N_BASE_IDX 2 +#define mmDP6_DP_VID_M 0x1f28 +#define mmDP6_DP_VID_M_BASE_IDX 2 +#define mmDP6_DP_LINK_FRAMING_CNTL 0x1f29 +#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a +#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP6_DP_VID_MSA_VBID 0x1f2b +#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c +#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CNTL 0x1f2d +#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP6_DP_DPHY_SYM0 0x1f2f +#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP6_DP_DPHY_SYM1 0x1f30 +#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP6_DP_DPHY_SYM2 0x1f31 +#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP6_DP_DPHY_8B10B_CNTL 0x1f32 +#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_PRBS_CNTL 0x1f33 +#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34 +#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_EN 0x1f35 +#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_CNTL 0x1f36 +#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_RESULT 0x1f37 +#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38 +#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39 +#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a +#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2 +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL 0x1f41 +#define mmDP6_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP6_DP_SEC_CNTL1 0x1f42 +#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING1 0x1f43 +#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING2 0x1f44 +#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING3 0x1f45 +#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP6_DP_SEC_FRAMING4 0x1f46 +#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_N 0x1f47 +#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_N_READBACK 0x1f48 +#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_M 0x1f49 +#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a +#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP6_DP_SEC_TIMESTAMP 0x1f4b +#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP6_DP_SEC_PACKET_CNTL 0x1f4c +#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP6_DP_MSE_RATE_CNTL 0x1f4d +#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP6_DP_MSE_RATE_UPDATE 0x1f4f +#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT0 0x1f50 +#define mmDP6_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT1 0x1f51 +#define mmDP6_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT2 0x1f52 +#define mmDP6_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT_UPDATE 0x1f53 +#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP6_DP_MSE_LINK_TIMING 0x1f54 +#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP6_DP_MSE_MISC_CNTL 0x1f55 +#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT0_STATUS 0x1f5d +#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT1_STATUS 0x1f5e +#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP6_DP_MSE_SAT2_STATUS 0x1f5f +#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy0_dispdec +// base address: 0x0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophycmregs0_dispdec +// base address: 0x0 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140 +#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141 +#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143 +#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144 +#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145 +#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146 +#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d +#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophytxregs0_dispdec +// base address: 0x0 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f +#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190 +#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d +#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophypllregs0_dispdec +// base address: 0x0 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1 +#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3 +#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4 +#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5 +#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7 +#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9 +#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa +#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy1_dispdec +// base address: 0x320 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophycmregs1_dispdec +// base address: 0x320 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208 +#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209 +#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b +#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c +#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d +#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e +#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215 +#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophytxregs1_dispdec +// base address: 0x320 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257 +#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258 +#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265 +#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophypllregs1_dispdec +// base address: 0x320 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269 +#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b +#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c +#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d +#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f +#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271 +#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272 +#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy2_dispdec +// base address: 0x640 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophycmregs2_dispdec +// base address: 0x640 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0 +#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1 +#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3 +#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4 +#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5 +#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6 +#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd +#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophytxregs2_dispdec +// base address: 0x640 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f +#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320 +#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d +#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophypllregs2_dispdec +// base address: 0x640 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331 +#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333 +#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334 +#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335 +#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337 +#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339 +#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a +#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy3_dispdec +// base address: 0x960 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophycmregs3_dispdec +// base address: 0x960 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398 +#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399 +#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b +#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c +#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d +#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e +#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5 +#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophytxregs3_dispdec +// base address: 0x960 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7 +#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8 +#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5 +#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophypllregs3_dispdec +// base address: 0x960 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9 +#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb +#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc +#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd +#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff +#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401 +#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402 +#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy4_dispdec +// base address: 0xc80 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophycmregs4_dispdec +// base address: 0xc80 +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460 +#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461 +#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463 +#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464 +#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465 +#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466 +#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d +#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophytxregs4_dispdec +// base address: 0xc80 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af +#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0 +#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd +#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophypllregs4_dispdec +// base address: 0xc80 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1 +#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3 +#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4 +#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5 +#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7 +#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8 +#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9 +#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca +#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy5_dispdec +// base address: 0xfa0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophycmregs5_dispdec +// base address: 0xfa0 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528 +#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529 +#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b +#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c +#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d +#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e +#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535 +#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophytxregs5_dispdec +// base address: 0xfa0 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577 +#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578 +#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585 +#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2 + + +// addressBlock: dce_dc_dc_combophypllregs5_dispdec +// base address: 0xfa0 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589 +#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b +#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c +#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d +#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f +#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590 +#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591 +#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2 +#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592 +#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_uniphy6_dispdec +// base address: 0x12c0 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1 +#define mmDCIO_ |