diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 |
1 files changed, 208 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h new file mode 100644 index 000000000000..109303e1b08d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _vce_4_0_OFFSET_HEADER +#define _vce_4_0_OFFSET_HEADER + + + +// addressBlock: vce0_vce_dec +// base address: 0x22000 +#define mmVCE_STATUS 0x0a01 +#define mmVCE_STATUS_BASE_IDX 0 +#define mmVCE_VCPU_CNTL 0x0a05 +#define mmVCE_VCPU_CNTL_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET0 0x0a09 +#define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE0 0x0a0a +#define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b +#define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE1 0x0a0c +#define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d +#define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE2 0x0a0e +#define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f +#define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE3 0x0a10 +#define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET4 0x0a11 +#define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE4 0x0a12 +#define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET5 0x0a13 +#define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE5 0x0a14 +#define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET6 0x0a15 +#define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE6 0x0a16 +#define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET7 0x0a17 +#define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE7 0x0a18 +#define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_OFFSET8 0x0a19 +#define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0 +#define mmVCE_VCPU_CACHE_SIZE8 0x0a1a +#define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0 +#define mmVCE_SOFT_RESET 0x0a48 +#define mmVCE_SOFT_RESET_BASE_IDX 0 +#define mmVCE_RB_BASE_LO2 0x0a5b +#define mmVCE_RB_BASE_LO2_BASE_IDX 0 +#define mmVCE_RB_BASE_HI2 0x0a5c +#define mmVCE_RB_BASE_HI2_BASE_IDX 0 +#define mmVCE_RB_SIZE2 0x0a5d +#define mmVCE_RB_SIZE2_BASE_IDX 0 +#define mmVCE_RB_RPTR2 0x0a5e +#define mmVCE_RB_RPTR2_BASE_IDX 0 +#define mmVCE_RB_WPTR2 0x0a5f +#define mmVCE_RB_WPTR2_BASE_IDX 0 +#define mmVCE_RB_BASE_LO 0x0a60 +#define mmVCE_RB_BASE_LO_BASE_IDX 0 +#define mmVCE_RB_BASE_HI 0x0a61 +#define mmVCE_RB_BASE_HI_BASE_IDX 0 +#define mmVCE_RB_SIZE 0x0a62 +#define mmVCE_RB_SIZE_BASE_IDX 0 +#define mmVCE_RB_RPTR 0x0a63 +#define mmVCE_RB_RPTR_BASE_IDX 0 +#define mmVCE_RB_WPTR 0x0a64 +#define mmVCE_RB_WPTR_BASE_IDX 0 +#define mmVCE_RB_ARB_CTRL 0x0a9f +#define mmVCE_RB_ARB_CTRL_BASE_IDX 0 +#define mmVCE_CLOCK_GATING_A 0x0abe +#define mmVCE_CLOCK_GATING_A_BASE_IDX 0 +#define mmVCE_CLOCK_GATING_B 0x0abf +#define mmVCE_CLOCK_GATING_B_BASE_IDX 0 +#define mmVCE_RB_BASE_LO3 0x0ad4 +#define mmVCE_RB_BASE_LO3_BASE_IDX 0 +#define mmVCE_RB_BASE_HI3 0x0ad5 +#define mmVCE_RB_BASE_HI3_BASE_IDX 0 +#define mmVCE_RB_SIZE3 0x0ad6 +#define mmVCE_RB_SIZE3_BASE_IDX 0 +#define mmVCE_RB_RPTR3 0x0ad7 +#define mmVCE_RB_RPTR3_BASE_IDX 0 +#define mmVCE_RB_WPTR3 0x0ad8 +#define mmVCE_RB_WPTR3_BASE_IDX 0 +#define mmVCE_SYS_INT_EN 0x0b00 +#define mmVCE_SYS_INT_EN_BASE_IDX 0 +#define mmVCE_SYS_INT_ACK 0x0b01 +#define mmVCE_SYS_INT_ACK_BASE_IDX 0 +#define mmVCE_SYS_INT_STATUS 0x0b01 +#define mmVCE_SYS_INT_STATUS_BASE_IDX 0 + + +// addressBlock: vce0_ctl_dec +// base address: 0x22780 +#define mmVCE_UENC_CLOCK_GATING 0x0bef +#define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0 +#define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0 +#define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0 +#define mmVCE_UENC_CLOCK_GATING_2 0x0c10 +#define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0 + + +// addressBlock: vce0_vce_sclk_dec +// base address: 0x23700 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0 +#define mmVCE_LMI_CTRL2 0x0fcf +#define mmVCE_LMI_CTRL2_BASE_IDX 0 +#define mmVCE_LMI_SWAP_CNTL3 0x0fd0 +#define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0 +#define mmVCE_LMI_CTRL 0x0fd6 +#define mmVCE_LMI_CTRL_BASE_IDX 0 +#define mmVCE_LMI_STATUS 0x0fd7 +#define mmVCE_LMI_STATUS_BASE_IDX 0 +#define mmVCE_LMI_VM_CTRL 0x0fd8 +#define mmVCE_LMI_VM_CTRL_BASE_IDX 0 +#define mmVCE_LMI_SWAP_CNTL 0x0fdd +#define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0 +#define mmVCE_LMI_SWAP_CNTL1 0x0fde +#define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0 +#define mmVCE_LMI_SWAP_CNTL2 0x0fe2 +#define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0 +#define mmVCE_LMI_CACHE_CTRL 0x0fec +#define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d +#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0 + + +// addressBlock: vce0_mmsch_dec +// base address: 0x23b00 +#define mmVCE_MMSCH_VF_VMID 0x10cb +#define mmVCE_MMSCH_VF_VMID_BASE_IDX 0 +#define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc +#define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 +#define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd +#define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 +#define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce +#define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0 +#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf +#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0 +#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0 +#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0 +#define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1 +#define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0 +#define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2 +#define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0 +#define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3 +#define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0 + + +// addressBlock: vce0_vce_rb_pg_dec +// base address: 0x23fa0 +#define mmVCE_HW_VERSION 0x11e8 +#define mmVCE_HW_VERSION_BASE_IDX 0 + + +#endif |