| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2010-09-30 | Add SystemVerilog header/source mime and tests | Ben James | 1 | -0/+10 | |
| Also changed Verilog and VHDL from "document" to "source code" https://bugs.freedesktop.org/show_bug.cgi?id=30012 | |||||
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index : xdg/shared-mime-info | |
| Shared MIME info spec (mirrored from https://gitlab.freedesktop.org/xdg/shared-mime-info) | alexl |
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