Add SystemVerilog header/source mime and tests

Also changed Verilog and VHDL from "document" to "source code"

https://bugs.freedesktop.org/show_bug.cgi?id=30012

1 files changed, 10 insertions, 0 deletions

diff --git a/tests/test.sv b/tests/test.sv
new file mode 100644
index 0000000..b8d79a2
--- /dev/null
+++ b/tests/test.sv
@@ -0,0 +1,10 @@
+
+`include "test.svh"
+
+function void
+  someclass::something();
+
+  $display("Something called!");
+
+endfunction : something
+