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2019-07-23radv/gfx10: enable CLEAR_stateSamuel Pitoiset1-2/+1
It actually works. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-23lima/ppir: fix branch codegen register encodeErico Nunes1-2/+2
The branch instruction has 6 bits per register operand which allows it to specify a component in the register. Fix codegen so that it outputs the right component, otherwise it always outputs the x component. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-23lima/ppir: fix debug logs in regallocErico Nunes1-2/+2
The macros already prepend "ppir: ", remove them from the actual strings so it doesn't appear duplicated. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-23lima/ppir: fix alignment on regalloc spilling loadsErico Nunes1-1/+1
The spilling code spills entire vec4 registers regardless of the components used by the spilled uses. The inserted stores code force the 4 components, but these loads were using a variable number of components, causing bugs on loading the spilled registers. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-23radv: fix dumping disassembly with RADV_DEBUG=shadersSamuel Pitoiset1-1/+2
Fixes: a20a9d0c5e7 ("radv: dont store disasm string unless keep_shader_info flag set") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-23st/nir: use asprintf() wrapper to fix MSVC issuesEric Engestrom1-0/+1
Fixes: 856e84083eee9b22408a ("mesa/st: add sampler uniforms") Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-23util: add asprintf() wrapper for MSVCEric Engestrom1-0/+12
Fixes: 856e84083eee9b22408a ("mesa/st: add sampler uniforms") Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-22gallium: remove boolean from state tracker APIsIlia Mirkin22-170/+168
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-22gallium: switch boolean -> bool at the interface definitionsIlia Mirkin161-770/+770
This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-23st/nir: fix arb fragment stage conversionDave Airlie1-1/+1
The comment even justifies the wrongness wrongly. We should be translating to pipe values properly here or else fragment maps to tess ctrl. Fixes: 3d7611e9a6c ("st/nir: use NIR for asm programs") Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-22radeonsi: fix warning: ‘ret’ may be used uninitializedMarek Olšák1-1/+1
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-22tgsi: fix warning: ‘interp’ may be used uninitializedMarek Olšák1-0/+1
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-22gallivm: fix warning: ‘op’ may be used uninitializedMarek Olšák1-0/+3
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-22iris: Support storage images that have matching typed formats for readsKenneth Graunke1-3/+2
Even if we don't directly support typed reads on a format, we can often translate them to a reasonable matching format. Advertise those too.
2019-07-22iris: Stop advertising MSAA storage images by mistakeKenneth Graunke1-1/+1
st_extensions.c sets const->MaxImageSamples (GL_MAX_IMAGE_SAMPLES) by looping over [16, 15, .. 1x] MSAA modes, and RGBA/BGRA/ARGB/ABGR 8888 color formats, calling pipe->is_format_supported() for each, with the usage set to PIPE_BIND_SHADER_IMAGE. If any are supported, it selects that number of samples. We were checking if sample_count <= 1, which meant that we were getting a value of 1x MSAA, rather than the expected 0x (feature doesn't exist). But, only on Icelake because Gen11 adds support for typed read messages for R8G8B8A8_UNORM. The lack of typed read messages for these formats was tricking the check on Gen9 to say no correctly. This caused some Icelake conformance failures, because we don't implement this feature. Just check for sample_count == 0 instead.
2019-07-22egl: Only expose 565 pbuffer configs if X can export them as DRI3 imagesKenneth Graunke1-37/+79
Glamor in xorg-server 1.20 cannot expose 16bpp pixmaps when running in the usual 24bpp mode. This meant our 565 pbuffer configs would ultimately fail to create a backing pixmap, leading to crashes. To hack around this, make a 16bpp pixmap and try and export it. If it works, expose the configs. Otherwise, just skip them. This also disables them on DRI2. These configs were only added to pass conformance requirements, and I doubt anybody cares about testing out 565 pbuffer visuals on DRI2-only drivers. v2: Don't leak the fds (caught by Eric Anholt) v3: Don't free(fds), it's not malloc'd Fixes: dacb11a585f ("egl: Add a 565 pbuffer-only EGL config under X11.") Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-22egl: Make the 565 pbuffer-only config single buffered.Kenneth Graunke1-2/+6
In commit dacb11a585face5ca179c34cfc588a71a425c1e0, Eric found the first matching 565 pbuffer config, and stopped. Our double-buffered configs come first in the list, so we added that, making a pbuffer-only config that claimed to be double buffered. This doesn't make sense, since pixmaps/pbuffers are fundamentally not double buffered. When using that config, every call to eglCreatePbufferSurface would fail with EGL_BAD_MATCH. The call chain looks like this: - eglCreatePbufferSurface - dri3_create_pbuffer_surface - dri3_create_surface - dri2_get_dri_config which eventually does: const bool double_buffer = surface_type == EGL_WINDOW_BIT; and then fails to find a matching config, because it ends up looking for a single-buffered config - and there aren't any. To fix this, make the 565 pbuffer config single-buffered. This fixes at least 51 dEQP-EGL.* tests. Fixes: dacb11a585f ("egl: Add a 565 pbuffer-only EGL config under X11.") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-22egl: Quiet warning about front buffer rendering for pixmaps/pbuffersKenneth Graunke1-3/+5
pbuffer configs cause a million of these warnings to trigger, but when using pixmaps or buffers, there is only one surface, so this warning doesn't make much sense. Retain it for window surfaces for now. Fixes: dacb11a585f ("egl: Add a 565 pbuffer-only EGL config under X11.") Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-22mesa: Fix ReadBuffers with pbuffersKenneth Graunke1-18/+17
pbuffers are internally single-buffered. Marek fixed DrawBuffers to handle this case, but we need to fix ReadBuffers too. Otherwise, pretty much every conformance test fails because glReadPixels breaks. v2: Refactor the switch into a helper (suggested by Eric Anholt) Fixes: 35294f2eca8 ("mesa: fix pbuffers because internally they are front buffers") Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1) Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-22mesa: fix assertion failure in TexImageMarek Olšák1-8/+6
Check the assertion after error checking. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111194 Fixes: 9dd1f7cec01 ("mesa: pass gl_texture_object as arg to not depend on state") Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-22nir: Remove a bunch of large stack arraysJason Ekstrand4-6/+15
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-22intel/fs: Stop stack allocating large arraysJason Ekstrand1-6/+12
Normally, we haven't worried too much about stack sizes as Linux tends to be fairly friendly towards large stacks. However, when running DXVK apps under wine, we're suddenly subject to Windows' more stringent stack limitations and can run out of space more easily. In particular, some of the shaders in Elite Dangerous: Horizons have quite a few registers and the arrays in split_virtual_grfs are large enough to blow a 1 MiB stack leading to crashes during shader compilation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108662 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org
2019-07-22egl/android: Update color_buffers querying for buffer ageNataraj Deshpande2-6/+31
color_buffers[] is currently hard coded to 3 for android which fails in droid_window_dequeue_buffer when ANativeWindow creates color_buffers >3 while querying buffer age during dEQP partial_update tests on chromeOS. The patch removes static color_buffers[], queries for MIN_UNDEQUEUED_BUFFERS, sets native window buffer count and allocates the correct number of color_buffers as per android. Fixes dEQP-EGL.functional.partial_update* tests on chromebooks with enabling EGL_KHR_partial_update. v2: update comment instead of removing (Eric Engestrom) v3: change static array to dynamic allocated color_buffers querying MIN_UNDEQUEUED_BUFFERS (Chia-I Wu olv@chromium.org) Fixes: 2acc69da8ce "EGL/Android: Add EGL_EXT_buffer_age extension" Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com> Acked-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-07-22intel/compiler: Use nir_opt_conditional_discardCaio Marcelo de Oliveira Filho1-0/+1
anv vkpipeline-db results for SKL: total instructions in shared programs: 3622461 -> 3611281 (-0.31%) instructions in affected programs: 396452 -> 385272 (-2.82%) helped: 2062 HURT: 1 total cycles in shared programs: 1458144669 -> 1458105320 (<.01%) cycles in affected programs: 4171830 -> 4132481 (-0.94%) helped: 1874 HURT: 180 total loops in shared programs: 2437 -> 2437 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total spills in shared programs: 8745 -> 8748 (0.03%) spills in affected programs: 8 -> 11 (37.50%) helped: 1 HURT: 1 total fills in shared programs: 23392 -> 23395 (0.01%) fills in affected programs: 8 -> 11 (37.50%) helped: 1 HURT: 1 LOST: 0 GAINED: 1 No changes to shader-db on i965 or iris. The glsl compiler already does a similar optimization. Improvement suggested by Daniel Schürmann. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-07-22pan/decode: Disable magic divisor debuggingAlyssa Rosenzweig1-0/+2
Memory corruption (for both legitimate and illegitimate reasons) causes this to hang pantrace. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Report spills:fills to shader-dbAlyssa Rosenzweig3-2/+12
Route this info through so we can track how we're doing on register spilling. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Reenable pipeline register creationAlyssa Rosenzweig1-10/+9
This was disabled to permit regression-free RA work. Now that the spill code is in place, we can reenable, with some caveats about efficacy. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Report tls_sizeAlyssa Rosenzweig4-0/+13
Pipe through the number of bytes of spilled memory used from the compiler into the main driver, where it will be used to allocate the Thread Local Storage buffer. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost: Set `initialized` in more casesAlyssa Rosenzweig2-10/+9
Indirect linear writes were not being marked as initialized, causing the back blit to be dropped, breaking the listed tests. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/ci: Update expectationsAlyssa Rosenzweig1-4/+0
We've fixed some shader tests. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Promote to *move*, not rewrite for non-SSAAlyssa Rosenzweig1-2/+9
Fixes promoted uniform loads to registers. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Dump MIR of RA failureAlyssa Rosenzweig1-1/+3
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard; Dump successor graph when printing MIRAlyssa Rosenzweig1-2/+12
We just use the pointers of the midgard_block*, which is crude, but it gets the point across and will help debug successor related issues. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Remove debug statementAlyssa Rosenzweig1-2/+0
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Implement register spillingAlyssa Rosenzweig4-54/+158
Now that we run RA in a loop, before each iteration after a failed allocation we choose a spill node and spill it to Thread Local Storage using st_int4/ld_int4 instructions (for spills and fills respectively). This allows us to compile complex shaders that normally would not fit within the 16 work register limits, although it comes at a fairly steep performance penalty. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Add mir_has_arg helperAlyssa Rosenzweig1-0/+12
Helps scan the MIR for uses of an index. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Check write-before-read in liveness analysisAlyssa Rosenzweig1-0/+13
If we write to an index before reading it, the old copy we're checking liveness for isn't live in this block, even if it does get read later. Fixes abnormally high register pressure in shaders with loops. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard/disasm: Check for certain tag errorsAlyssa Rosenzweig1-0/+18
Midgard bundles contain a tag, as well as a copy of the tag of the next bundle to facilitate prefetch. Do some simple static analysis to detect certain tag errors (particularly on shaders without branching). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Add OP_IS_CSEL helperAlyssa Rosenzweig1-0/+7
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Add mir_rewrite_index_src_single helperAlyssa Rosenzweig2-6/+13
Rather than rewriting an index away across the whole block, we expose finer (per-instruction) granularity for rewrites. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Ignore inline_constant in livenessAlyssa Rosenzweig1-0/+3
It doesn't make any sense to look at it. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost/midgard: Implement load/store scratch opcodesAlyssa Rosenzweig4-2/+52
These are used to load/store from Thread Local Storage, which is memory allocated per-thread (corresponding to ctx->scratchpad in the command stream) and used for register spilling. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midg/disasm: Check for int varying opsAlyssa Rosenzweig1-0/+4
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Remove "aliasing"Alyssa Rosenzweig2-96/+0
It was a crazy idea that didn't pan out. We're better served by a good copyprop pass. It's also unused now. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22panfrost: Promote uniform registers lateAlyssa Rosenzweig6-82/+174
Rather than creating either a load or a uniform register read with a fixed beginning offset, we always create a load and then promote to a uniform register later. This will allow us to promote in a register pressure aware manner. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Call scheduler/RA in a loopAlyssa Rosenzweig3-13/+27
This will allow us to insert instructions as a result of register allocation, permitting spilling to be implemented. As a side effect, with the assert commented out this would fix a bunch of glamor crashes (due to RA failures) so MATE becomes useable. Ideally we'll have scheduling or RA actually sorted out before the branch point but if not this gives us a one-line out to get X working... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22pan/midgard: Remove custom register selection callbackAlyssa Rosenzweig1-19/+0
What we have is equivalent to the default callback; let's use that. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-22radv: fix crash in vkCmdClearAttachments with unused attachmentSamuel Pitoiset1-1/+1
depth_stencil_attachment and/or ds_resolve attachment can be NULL. This fixes crashes with dEQP-VK.renderpass.suballocation.unused_clear_attachments.* Cc: 19.1 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-22i965: free object labels when deletingSergii Romantsov3-0/+3
Some leaks detected with GL_KHR_debug on i965. CC: Timothy Arceri <t_arceri@yahoo.com.au> Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-07-22radv/gfx10: update descriptors for inline uniform blocksSamuel Pitoiset1-3/+10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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