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path: root/src/mesa/drivers/dri/i965/gen7_l3_state.c
AgeCommit message (Expand)AuthorFilesLines
2020-10-06i965: drop likely/unlikely around INTEL_DEBUGMarcin Ślusarz1-1/+1
2020-01-30i965: Re-emit l3 state before BLORP executesJason Ekstrand1-3/+3
2020-01-30intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand1-1/+2
2018-11-26i965/icl: Set use full ways in L3CNTLREGAnuj Phogat1-0/+1
2018-03-27i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke1-4/+1
2017-11-14i965: Make use of brw_load_register_imm32() helper functionAnuj Phogat1-11/+6
2017-11-10i965: Make L3 configuration atom listen for TCS/TES program updates.Kenneth Graunke1-0/+2
2017-10-12i965: Use prog->info.num_images for needs_dc computationJason Ekstrand1-2/+3
2017-08-30i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin1-1/+1
2017-08-30i965: drop brw->is_baytrail in favor of devinfo->is_baytrailLionel Landwerlin1-3/+3
2017-08-30i965: drop brw->gen in favor of devinfo->genLionel Landwerlin1-1/+2
2017-08-18i965: Stop looking at NewDriverState when emitting 3DSTATE_URBJason Ekstrand1-0/+9
2017-01-23mesa: use gl_program for CurrentProgram rather than gl_shader_programTimothy Arceri1-3/+3
2017-01-05i965: add a kernel_features bitfield to intel screenIago Toral Quiroga1-1/+1
2017-01-05i965: get rid of brw->can_do_pipelined_register_writesIago Toral Quiroga1-2/+3
2016-11-19st/mesa/glsl/nir/i965: make use of new gl_shader_program_data in gl_shader_pr...Timothy Arceri1-2/+2
2016-10-05i965: use L3 data cache for SSBOsLionel Landwerlin1-1/+2
2016-09-23intel/i965: make gen_device_info mutableLionel Landwerlin1-4/+4
2016-09-20i965: Rename intelScreen to screen.Kenneth Graunke1-5/+5
2016-09-03intel: Pull the guts of gen7_l3_state.c into a shared helperJason Ekstrand1-331/+37
2016-09-03intel: s/brw_device_info/gen_device_info/Jason Ekstrand1-8/+8
2016-04-23i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke1-0/+1
2016-02-11i965: Consider tessellation in get_pipeline_state_l3_weights.Kenneth Graunke1-1/+6
2016-02-08i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez1-2/+2
2016-02-08i965: Invalidate state cache before L3 partitioning set-up.Francisco Jerez1-0/+1
2016-02-08i965: Fix cache pollution race during L3 partitioning set-up.Francisco Jerez1-8/+23
2015-12-09i965: Work around L3 state leaks during context switches.Francisco Jerez1-4/+57
2015-12-09i965: Add debug flag to print out the new L3 state during transitions.Francisco Jerez1-0/+17
2015-12-09i965: Implement L3 state atom.Francisco Jerez1-0/+81
2015-12-09i965: Calculate appropriate L3 partition weights for the current pipeline state.Francisco Jerez1-0/+53
2015-12-09i965: Implement selection of the closest L3 configuration based on a vector o...Francisco Jerez1-0/+95
2015-12-09i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ...Francisco Jerez1-1/+1
2015-12-09i965/hsw: Enable L3 atomics.Francisco Jerez1-0/+14
2015-12-09i965: Implement programming of the L3 configuration.Francisco Jerez1-0/+95
2015-12-09i965: Import tables enumerating the set of validated L3 configurations.Francisco Jerez1-0/+167
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