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path: root/src/mesa/drivers/dri/i965/brw_reg.h
AgeCommit message (Expand)AuthorFilesLines
2017-01-20i965: Add support for constant evaluation on Q and UQ typesIan Romanick1-0/+1
2017-01-20i965: Replace reg_type_size[] with a function.Matt Turner1-0/+8
2017-01-03i965/vec4/scalarize_df: support more swizzles via vstride=0Iago Toral Quiroga1-0/+2
2017-01-03i965/vec4/scalarize_df: do not scalarize swizzles that we can support nativelyIago Toral Quiroga1-0/+3
2017-01-03i965: add brw_vecn_grf()Connor Abbott1-0/+6
2016-10-19i965: fix subnr overflow in suboffset()Iago Toral Quiroga1-8/+5
2016-09-21i965/fs: Take Dispatch/Vector mask into account in FIND_LIVE_CHANNELJason Ekstrand1-0/+12
2016-09-21i965/reg: Make brw_sr0_reg take a subnr and return a vec1 regJason Ekstrand1-12/+8
2016-09-03intel: s/brw_device_info/gen_device_info/Jason Ekstrand1-2/+2
2016-07-21i965: add helper for creating packing writemaskTimothy Arceri1-0/+7
2016-07-21i965: add helpers for creating component layout swizzleTimothy Arceri1-0/+3
2016-06-02i965: Add missing types to type_sz().Matt Turner1-1/+5
2016-05-27i965: Define brw_int_type() helper.Francisco Jerez1-0/+20
2016-05-20i965: Fix brw_regs_equal() for NaN and positive/negative zero.Kenneth Graunke1-1/+2
2016-05-14i965: Fix undefined df bits in brw_reg comparisons.Kenneth Graunke1-8/+19
2016-05-10i965: add brw_imm_dfConnor Abbott1-0/+9
2016-05-10i965: Determine size of double precision float registerTopi Pohjolainen1-0/+1
2016-03-08i965/hsw: Initialize SLM index in state registerJordan Justen1-0/+16
2016-03-06i965: Add support for swizzling arbitrary immediates to (brw_)swizzle().Francisco Jerez1-2/+5
2016-03-06i965: Pass symbolic swizzle to brw_swizzle() as a single argument.Francisco Jerez1-11/+4
2015-12-30i965/gen8: Always use BRW_REGISTER_TYPE_UW for MUL on GEN8+Marta Lofstedt1-27/+0
2015-12-22i965: Add tessellation control shaders.Kenneth Graunke1-0/+1
2015-11-20i965: Add brw_imm_uv().Matt Turner1-0/+9
2015-11-20i965: Don't bother setting regioning on immediates.Matt Turner1-6/+0
2015-11-19i965: Make brw_imm_vf4() take 8-bit restricted floats.Matt Turner1-31/+7
2015-11-13i965: Combine register file field.Matt Turner1-2/+2
2015-11-13i965: Use brw_reg's nr field to store register number.Matt Turner1-5/+5
2015-11-13i965: Add and use enum brw_reg_file.Matt Turner1-12/+13
2015-11-13i965: Reorganize brw_reg fields.Matt Turner1-8/+8
2015-11-13i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner1-20/+20
2015-11-11i965/brw_reg: Add a brw_VxH_indirect helperJason Ekstrand1-0/+11
2015-10-22i965: Note that the UV immediate type is Gen6+.Matt Turner1-1/+1
2015-09-21i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga1-1/+1
2015-09-21i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga1-3/+4
2015-08-03i965/vec4: Add auxiliary func to build a writemask from a component sizeEduardo Lima Mitev1-0/+6
2015-07-29Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()Anuj Phogat1-1/+1
2015-06-12i965: Add notification registerJordan Justen1-0/+16
2015-05-12i965: Document brw_mask_reg().Francisco Jerez1-1/+5
2015-04-22i965: Make the brw_inst helpers take a device_info instead of a contextJason Ekstrand1-2/+2
2015-04-21i965/fs: Calculate delta_x and delta_y together.Matt Turner1-0/+7
2015-04-21i965: Make type_sz() return unsigned.Matt Turner1-1/+1
2015-03-23i965/vec4: Some more trivial swizzle clean-up.Francisco Jerez1-4/+2
2015-03-23i965/vec4: Fix signedness of brw_is_single_value_swizzle() argument.Francisco Jerez1-1/+1
2015-03-23i965: Define some useful swizzle helper functions.Francisco Jerez1-0/+97
2015-02-19i965/fs: Replace ud_reg_to_w() with a more general helper function.Francisco Jerez1-0/+22
2015-01-20i965: Extract scalar region checking logicBen Widawsky1-0/+13
2015-01-20i965: Add QWORD sizes to type_sz macroBen Widawsky1-0/+3
2014-12-15i965/brw_reg: struct constructor now needs explicit negate and abs values.Andres Gomez1-2/+20
2014-11-25i965: Add functions to convert float <-> VF.Matt Turner1-0/+4
2014-09-30i965/brw_reg: Make the accumulator register take an explicit width.Jason Ekstrand1-2/+3
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