index
:
mesa/mesa
10.0
10.1
10.2
10.3
10.4
10.5
10.6
11.0
11.1
11.2
12.0
13.0
17.0
17.1
17.2
17.3
18.0
18.1
18.2
18.3
19.0
19.1
19.2
19.3
20.0
20.1
20.2
20.3
21.0
21.1
21.2
21.3
22.0
22.1
22.2
22.3
23.0
23.1
23.2
23.3
24.0
24.1
7.10
7.11
7.8
7.8-gles
7.9
8.0
9.0
9.1
9.2
a7xx-gmem
amber
elima/radv-video-encode-caps-maxbitrate
explicit-sync
main
powervr-mesa-next-wayland
review/fragment_shader_barycentric
staging/23.2
staging/23.3
staging/24.0
staging/24.1
uav-counter-meta
vk-no-nir-android
zink-stablefix
The Mesa 3D Graphics Library (mirrored from https://gitlab.freedesktop.org/mesa/mesa)
brianp
summary
refs
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path:
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src
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mesa
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drivers
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dri
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i965
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brw_pipe_control.c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-10-15
i965: Remove Gen10-specific state setup and workarounds
Ian Romanick
1
-3
/
+2
2020-10-15
i965: Rename gen10_emit_isp_disable to gen7_emit_isp_disable
Ian Romanick
1
-1
/
+1
2020-05-20
i965: add identifier BO
Lionel Landwerlin
1
-0
/
+24
2020-05-20
i965: store workaround_bo offset
Lionel Landwerlin
1
-5
/
+10
2019-07-31
tree-wide: replace MAYBE_UNUSED with ASSERTED
Eric Engestrom
1
-1
/
+1
2019-03-11
i965: Use genxml for emitting PIPE_CONTROL.
Kenneth Graunke
1
-201
/
+42
2019-03-11
i965: Rename ISP_DIS to INDIRECT_STATE_POINTERS_DISABLE.
Kenneth Graunke
1
-1
/
+1
2018-11-14
i965: avoid 'unused variable' warnings
Andrii Simiklit
1
-1
/
+1
2018-05-22
i965: Remove ring switching entirely
Jason Ekstrand
1
-22
/
+10
2018-05-22
i965: Introduce a "memory zone" concept on BO allocation.
Kenneth Graunke
1
-1
/
+2
2018-05-09
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
Jason Ekstrand
1
-1
/
+2
2018-05-09
i965: require pixel scoreboard stall prior to ISP disable
Lionel Landwerlin
1
-1
/
+8
2018-03-27
i965: Drop unused alignment parameter from brw_bo_alloc().
Kenneth Graunke
1
-1
/
+1
2018-03-27
i965: Drop PIPE_CONTROL_NO_WRITE from various calls.
Kenneth Graunke
1
-1
/
+1
2018-03-01
i965: Shorten the name of the workaround BO.
Kenneth Graunke
1
-3
/
+1
2018-01-26
i965/gen10: Use CS Stall instead of WriteImmediate.
cros-mesa-18.1_pre1-r4-vanilla
chadv/cros-mesa-18.1_pre1-r4-vanilla
Rafael Antognolli
1
-6
/
+4
2018-01-26
i965/gen10: Ignore push constant packets during context restore.
Rafael Antognolli
1
-0
/
+49
2017-11-17
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
Kenneth Graunke
1
-1
/
+5
2017-11-16
i965: Implement another VF cache invalidate workaround on Gen8+.
Kenneth Graunke
1
-8
/
+33
2017-11-14
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Anuj Phogat
1
-2
/
+5
2017-11-14
i965: Program DWord Length in MI_FLUSH_DW
Anuj Phogat
1
-1
/
+1
2017-11-10
i965/gen10: Use the correct form of | for the RCPFE workaround
Jason Ekstrand
1
-2
/
+2
2017-11-03
i965/gen10: Implement WaForceRCPFEHangWorkaround
Anuj Phogat
1
-0
/
+23
2017-08-30
i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().
Kenneth Graunke
1
-0
/
+1
2017-08-30
i965: drop brw->is_haswell in favor of devinfo->is_haswell
Lionel Landwerlin
1
-2
/
+2
2017-08-30
i965: drop brw->gen in favor of devinfo->gen
Lionel Landwerlin
1
-15
/
+29
2017-08-04
i965: Reduce passing 2x32b of reloc_domains to 2 bits
Chris Wilson
1
-8
/
+4
2017-06-14
i965: Do an end-of-pipe sync after flushes
Jason Ekstrand
1
-3
/
+3
2017-06-14
i965: Add an end-of-pipe sync helper
Topi Pohjolainen
1
-1
/
+99
2017-06-14
i965: Unify the two emit_pipe_control functions
Jason Ekstrand
1
-73
/
+64
2017-06-14
i965: Take a uint64_t immediate in emit_pipe_control_write
Jason Ekstrand
1
-12
/
+10
2017-04-10
i965/drm: Rename drm_bacon_bo to brw_bo.
Kenneth Graunke
1
-5
/
+5
2017-04-10
i965/drm: Use our internal libdrm (drm_bacon) rather than the real one.
Kenneth Graunke
1
-3
/
+3
2016-12-14
i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().
Francisco Jerez
1
-0
/
+1
2016-09-28
i965: Remove useless (harmful) assertion
Ben Widawsky
1
-1
/
+1
2016-09-03
intel: s/brw_device_info/gen_device_info/
Jason Ekstrand
1
-1
/
+1
2016-08-19
i965: Roll intel_reg.h into brw_defines.h
Jason Ekstrand
1
-1
/
+1
2016-07-07
i965: Fix remaining flush vs invalidate race conditions in brw_emit_pipe_cont...
Francisco Jerez
1
-0
/
+18
2016-07-07
i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.
Francisco Jerez
1
-9
/
+10
2016-07-07
i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
Francisco Jerez
1
-10
/
+11
2016-03-28
i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs.
Kenneth Graunke
1
-2
/
+0
2016-02-08
i965: Rename define for the PIPE_CONTROL DC flush bit.
Francisco Jerez
1
-1
/
+1
2015-12-21
i965: Only apply CS stall workaround pre-SKL
Ben Widawsky
1
-2
/
+4
2015-12-09
i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.
Francisco Jerez
1
-1
/
+3
2015-09-08
i965/gen8+: Skip depth stalls on state change
Ben Widawsky
1
-0
/
+8
2015-07-08
i965: Move pipecontrol workaround bo to brw_pipe_control
Chris Wilson
1
-6
/
+34
2015-06-24
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Chris Wilson
1
-4
/
+4
2015-06-24
i965: Transplant PIPE_CONTROL routines to brw_pipe_control
Chris Wilson
1
-0
/
+331