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mesa/mesa
10.0
10.1
10.2
10.3
10.4
10.5
10.6
11.0
11.1
11.2
12.0
13.0
17.0
17.1
17.2
17.3
18.0
18.1
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18.3
19.0
19.1
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19.3
20.0
20.1
20.2
20.3
21.0
21.1
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21.3
22.0
22.1
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22.3
23.0
23.1
23.2
23.3
24.0
24.1
7.10
7.11
7.8
7.8-gles
7.9
8.0
9.0
9.1
9.2
a7xx-gmem
amber
elima/radv-video-encode-caps-maxbitrate
explicit-sync
main
powervr-mesa-next-wayland
review/fragment_shader_barycentric
staging/23.2
staging/23.3
staging/24.0
staging/24.1
uav-counter-meta
vk-no-nir-android
zink-stablefix
The Mesa 3D Graphics Library (mirrored from https://gitlab.freedesktop.org/mesa/mesa)
brianp
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i965
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brw_defines.h
Age
Commit message (
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Author
Files
Lines
2020-10-01
intel/gen9: Enable MSC RAW Hazard Avoidance
Anuj Phogat
1
-0
/
+1
2019-09-23
Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"
Kenneth Graunke
1
-4
/
+0
2019-09-11
intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM
Anuj Phogat
1
-0
/
+4
2019-08-12
i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.
Rafael Antognolli
1
-0
/
+4
2019-08-12
i965/gen9: Optimize slice and subslice load balancing behavior.
Francisco Jerez
1
-0
/
+5
2019-08-07
intel/perf: move get_query_data into gen_perf
Mark Janes
1
-12
/
+0
2019-08-07
intel/perf: move perf-related constants to common location
Mark Janes
1
-14
/
+0
2019-07-08
i965: disable repacking for compression for applicable gen
Dongwon Kim
1
-0
/
+1
2019-06-28
Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch"
Anuj Phogat
1
-4
/
+0
2019-04-18
i965: implement WaEnableStateCacheRedirectToCS
Lionel Landwerlin
1
-0
/
+1
2019-03-19
i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Anuj Phogat
1
-0
/
+4
2019-01-29
intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITS
Jason Ekstrand
1
-1
/
+1
2018-12-14
i965/gen10+: Enable object level preemption.
Rafael Antognolli
1
-0
/
+5
2018-11-26
i965/icl: Set use full ways in L3CNTLREG
Anuj Phogat
1
-0
/
+1
2018-11-01
i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG
Anuj Phogat
1
-0
/
+1
2018-09-21
i965/icl: Set Enabled Texel Offset Precision Fix bit
Anuj Phogat
1
-0
/
+4
2018-08-21
i965/icl: Allow headerless sampler messages for pre-emptable contexts
Anuj Phogat
1
-0
/
+4
2018-04-23
i965: perf: snapshot RPSTAT register
Lionel Landwerlin
1
-0
/
+12
2018-01-09
intel: Apply Geminilake "Barrier Mode" workaround.
Kenneth Graunke
1
-0
/
+5
2017-12-04
i965: Move PIPE_CONTROL defines and prototypes to brw_pipe_control.h.
Kenneth Graunke
1
-43
/
+0
2017-11-17
i965: Remove DWord length from MI_FLUSH_DW definition
Anuj Phogat
1
-1
/
+1
2017-11-03
i965/gen10: Implement Wa3DStateMode
Anuj Phogat
1
-0
/
+2
2017-11-03
i965/gen10: Enable float blend optimization
Anuj Phogat
1
-0
/
+3
2017-11-03
i965/gen10: Implement WaSampleOffsetIZ workaround
Anuj Phogat
1
-0
/
+1
2017-08-02
i965: Set "Subslice Hashing Mode" to 16x16 on Apollolake.
Kenneth Graunke
1
-0
/
+7
2017-07-13
i965: Switch to absolute addressing for constant buffer 0.
Kenneth Graunke
1
-0
/
+6
2017-06-27
i965: Add Gen8+ INTEL_performance_query support
Robert Bragg
1
-0
/
+1
2017-05-30
i965: Set the "Float Blend Optimization Enable" bit on Gen9+.
Kenneth Graunke
1
-0
/
+1
2017-05-26
i965: Move clip program compilation to the compiler
Jason Ekstrand
1
-7
/
+0
2017-05-26
i965: Move SF compilation to the compiler
Jason Ekstrand
1
-2
/
+0
2017-05-03
i965: Move MOCS macros to brw_context.h.
Rafael Antognolli
1
-42
/
+0
2017-03-27
i965: Delete tile resource mode code
Anuj Phogat
1
-9
/
+0
2017-03-13
intel: fix compiler build
Iago Toral Quiroga
1
-8
/
+0
2017-03-13
i965: split EU defines to brw_eu_defines.h
Emil Velikov
1
-1188
/
+0
2017-03-13
i965: move brw_define.h ifndef guard to the top
Emil Velikov
1
-3
/
+3
2017-03-13
i965: remove unused macros from brw_defines.h
Emil Velikov
1
-19
/
+1
2017-03-06
i965: Delete vestiges of resource streamer code.
Kenneth Graunke
1
-52
/
+0
2017-03-02
i965: Replace BRW_SURFACEFORMAT_* with ISL_FORMAT_*.
Kenneth Graunke
1
-247
/
+0
2017-03-01
i965: Reduce cross-pollination between the DRI driver and compiler
Jason Ekstrand
1
-0
/
+2
2017-03-01
i965: Get rid of BRW_PRIM_OFFSET
Jason Ekstrand
1
-8
/
+0
2017-01-03
i965/vec4: Rename DF to/from F generator opcodes
Iago Toral Quiroga
1
-2
/
+2
2017-01-03
i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
Iago Toral Quiroga
1
-0
/
+2
2017-01-03
i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
Iago Toral Quiroga
1
-0
/
+2
2017-01-03
i965/vec4: add double/float conversion pseudo-opcodes
Iago Toral Quiroga
1
-0
/
+2
2016-12-14
i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.
Francisco Jerez
1
-1
/
+0
2016-12-14
i965: Factor out oword block read and write message control calculation.
Francisco Jerez
1
-0
/
+6
2016-12-12
treewide: s/comparitor/comparator/
Ilia Mirkin
1
-1
/
+1
2016-12-07
i965: enable INTEL_conservative_rasterization on Gen9+
Lionel Landwerlin
1
-0
/
+1
2016-11-29
i965/fs: Refactor handling of constant tg4 offsets
Jason Ekstrand
1
-1
/
+1
2016-11-23
i965: Use 3DSTATE_CLIP's User Clip Distance Enable bitmask on Gen8+.
Kenneth Graunke
1
-0
/
+1
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