mesa/mesa - The Mesa 3D Graphics Library (mirrored from https://gitlab.freedesktop.org/mesa/mesa)

Age	Commit message (Expand)	Author	Files	Lines
2018-03-08	i965/fs: Add infrastructure for generating CSEL instructions.	Kenneth Graunke	1	-0/+1
2018-02-28	intel/compiler: Add Gen11+ native float type	Matt Turner	1	-0/+7
2018-02-10	intel/compiler: fix 64bit value prints on 32bit	Grazvydas Ignotas	1	-2/+2
2017-10-20	i965: Add align1 ternary instruction disassembler support	Matt Turner	1	-64/+288
2017-10-20	i965: Add align1 ternary instruction support to conversion functions	Matt Turner	1	-12/+4
2017-10-20	i965: Rename brw_inst's functions that access the 3src register type	Matt Turner	1	-8/+8
2017-10-20	i965: Rename brw_inst 3src functions in preparation for align1	Matt Turner	1	-23/+23
2017-10-20	i965: Print subreg in units of type-size on ternary instructions	Matt Turner	1	-5/+26
2017-10-04	i965: Fix support for disassembling 64-bit integer immediates	Matt Turner	1	-2/+2
2017-08-21	i965: Stop using hardware register types directly	Matt Turner	1	-28/+19
2017-08-21	i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.c	Matt Turner	1	-39/+33
2017-08-21	i965: Rename brw_inst's functions that access the register type	Matt Turner	1	-11/+11
2017-08-21	i965: Reverse file/type arguments to register type functions	Matt Turner	1	-2/+2
2017-08-21	i965: Add support for disassembling 64-bit integer immediates	Matt Turner	1	-0/+6
2017-08-21	i965: Use separate enums for register vs immediate types	Matt Turner	1	-22/+24
2017-08-02	i965: Fix indentation	Matt Turner	1	-6/+6
2017-05-26	intel/compiler: Make brw_disasm take const assembly	Jason Ekstrand	1	-10/+10
2017-04-14	i965/disasm: also print nibctrl in IVB for execsize=8	Iago Toral Quiroga	1	-3/+3
2017-03-13	i965: Move the back-end compiler to src/intel/compiler	Jason Ekstrand	1	-0/+1646