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path: root/src/gallium
AgeCommit message (Expand)AuthorFilesLines
2019-01-08nir: rename global/local to private/function memoryKarol Herbst3-4/+4
2019-01-08autotools: Remove tegra vdpau driverDylan Baker1-2/+0
2019-01-08clover/meson: Ignore 'svn' suffix when computing CLANG_RESOURCE_DIRPierre Moreau1-1/+1
2019-01-08virgl: use primconvert provoking vertex properlyDave Airlie2-8/+24
2019-01-08spirv: Add support for using derefs for UBO/SSBO accessJason Ekstrand1-0/+1
2019-01-08glsl_type: Add support for explicitly laid out matrices and arraysJason Ekstrand1-2/+2
2019-01-08nir: Distinguish between normal uniforms and UBOsJason Ekstrand1-2/+3
2019-01-07etnaviv: annotate variables only used in debug buildLucas Stach1-7/+4
2019-01-07etnaviv: enable full overwrite in a few more casesLucas Stach1-4/+7
2019-01-04v3d: Fix up VS output setup during precompiles.Eric Anholt1-6/+10
2019-01-03virgl: remove empty fileGurchetan Singh1-0/+0
2019-01-03virgl: don't flush an empty rangeGurchetan Singh1-0/+4
2019-01-03virgl/vtest: Use default socket name from protocol headerJakob Bornecrantz1-3/+1
2019-01-03freedreno: fix staging resource size for arraysRob Clark1-2/+10
2019-01-03freedreno: remove blit_via_copy_region()Rob Clark1-4/+0
2019-01-03freedreno/a6xx: rework blitter APIRob Clark1-54/+8
2019-01-03freedreno: try blitter for fd_resource_copy_region()Rob Clark1-0/+27
2019-01-03freedreno: rework blit APIRob Clark8-27/+29
2019-01-03freedreno: skip depth resolve if not writtenRob Clark3-4/+14
2019-01-02v3d: Refactor compiler entrypoints.Eric Anholt1-26/+6
2019-01-02v3d: Don't forget to include RT writes in precompiles.Eric Anholt1-0/+10
2019-01-02v3d: Fix segfault when failing to compile a program.Eric Anholt1-2/+4
2019-01-02radeonsi: always unmap texture CPU mappings on 32-bit CPU architecturesMarek Olšák1-0/+16
2019-01-02radeonsi: remove unused variables in si_insert_input_ptrMarek Olšák1-3/+1
2019-01-02radeonsi: use u_decomposed_prims_for_vertices instead of u_prims_for_verticesMarek Olšák1-1/+3
2019-01-02radeonsi: make si_cp_wait_mem more configurableMarek Olšák5-8/+8
2019-01-02radeonsi: call si_fix_resource_usage for the GS copy shader as wellMarek Olšák1-0/+4
2019-01-02radeonsi: don't emit redundant PKT3_NUM_INSTANCES packetsMarek Olšák2-2/+10
2019-01-02st/glsl_to_nir: call nir_lower_load_const_to_scalar() in the stTimothy Arceri1-2/+0
2019-01-02radeonsi: make use of ac_are_tessfactors_def_in_all_invocs()Timothy Arceri1-8/+2
2019-01-02radeonsi: remove unrequired param in si_nir_scan_tess_ctrl()Timothy Arceri3-3/+1
2019-01-02tgsi/scan: correctly walk instructions in tgsi_scan_tess_ctrl()Timothy Arceri1-29/+43
2019-01-02tgsi/scan: fix loop exit point in tgsi_scan_tess_ctrl()Timothy Arceri1-1/+1
2019-01-01nv30: disable rendering to 3D texturesIlia Mirkin1-0/+6
2018-12-30nv30: fix some s3tc layout issuesIlia Mirkin2-7/+26
2018-12-30nv30: use correct helper to get blocks in y directionIlia Mirkin1-1/+1
2018-12-30nv30: add support for multi-layer transfersIlia Mirkin1-4/+35
2018-12-30nv30: fix rare issue with fp unbinding not finding the bufctxIlia Mirkin1-1/+1
2018-12-30nv30: avoid setting user_priv without setting cur_ctxIlia Mirkin1-3/+1
2018-12-30v3d: Add support for requesting the sample offsets.Eric Anholt1-0/+22
2018-12-30v3d: Hook up some shader-db output to GL_ARB_debug_output.Eric Anholt1-0/+12
2018-12-29v3d: Add a "precompile" debug flag for shader-db.Eric Anholt1-0/+76
2018-12-28meson: Override C++ standard to gnu++11 when building with altivec on ppc64Dylan Baker1-0/+3
2018-12-28radeonsi: Enable adaptive_sync by default for radeonNicholas Kazlauskas1-0/+4
2018-12-28etnaviv: Consolidate buffer references from framebuffersTomeu Vizoso3-10/+9
2018-12-28virgl/vtest: fix front buffer flush with protocol version 0.Dave Airlie1-1/+1
2018-12-26nv50,nvc0: add missing CAPs for unsupported featuresIlia Mirkin2-0/+3
2018-12-26nvc0: enable GL_NV_shader_atomic_float on pre-MaxwellIlia Mirkin1-0/+2
2018-12-26nv50/ir: add support for converting ATOMFADD to proper irIlia Mirkin1-0/+4
2018-12-26gallium: add PIPE_CAP_TGSI_ATOMFADD to indicate supportIlia Mirkin3-0/+4