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2019-06-11virgl: consider newly created resources idleChia-I Wu1-6/+8
A newly created resource can be regarded as idle. We don't care if the RESOURCE_CREATE command has been retired, unless it is used for fencing. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-11virgl: make resource_wait/resource_is_busy cheaperChia-I Wu2-0/+27
The round trip to the kernel is expensive. Add a local cache to avoid it when possible. There is a race condition when two contexts access the same resource at the same time (e.g., ctx1 submits a cmdbuf that accesses a resource while ctx2 maps the resource). But that is probably an app bug in the first place. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-11virgl: add virgl_drm_{alloc,free,clear}_res_listChia-I Wu1-17/+42
Helpers to work with resource list. virgl_drm_release_all_res is removed. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-11virgl: do not cache external resourcesChia-I Wu2-1/+10
We should not reuse a resource for other purposes when it can still be accessed by another process or device. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-07virgl: Make VIRGL_BIND_STAGING resources cacheableAlexandros Frantzis2-2/+4
This could help performance when trying to recreate such resources for copy transfers. Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com> Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-06-07virgl: Deduplicate checks for resource cachingAlexandros Frantzis4-20/+14
Also fixes a missed check for VIRGL_BIND_CUSTOM in one of the duplicate code snippets. Note that legacy fences also use VIRGL_BIND_CUSTOM, but we ensured they don't go through the cache in the previous commit. Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com> Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-06-07virgl: Don't try to use cached resources for legacy fencesAlexandros Frantzis2-6/+12
Resources for fences should not be from the cache, since we are basing the fence status on the resource creation busy status. Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com> Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-06-06winsys/svga/drm: Fix 32-bit RPCI send messageDeepak Rawat1-12/+23
Depending on whether compiled with frame-pointer or not, the temporary memory location used for the bp parameter in these macros are referenced relative to the stack pointer or the frame pointer. Hence we can never reference that parameter when we've modified either the stack pointer or the frame pointer, because then the compiler would generate an incorrect stack reference. Fix this by pushing the temporary memory parameter on a known location on the stack before modifying the stack- and frame pointers. Also in case of failuire RPCI channel is not closed which lead to vmx running out of channels. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2019-06-02winsys/drm: Fix out of scope variable usageDeepak Rawat1-12/+13
In this particular instance, struct member were used outside of the block where it was defined. Fix this by moving the definition outside of block. Signed-off-by: Deepak Rawat <drawat@vmware.com> Fixes: 569f83898768 ("winsys/svga: Add support for new surface ioctl, multisample pattern") Reviewed-by: Brian Paul <brianp@vmware.com>
2019-06-05build: Build etnaviv drmGuido Günther1-2/+4
Signed-off-by: Guido Günther <guido.gunther@puri.sm> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-06-03amd/common: use generated register headerNicolai Hähnle2-2/+1
2019-05-27radeonsi: clean up winsys creationMarek Olšák1-8/+0
- unify the code - choose radeon or amdgpu based on the DRM version, not based on which one succeeds first
2019-05-27ac: treat Mullins as Kabini, remove the enumMarek Olšák1-3/+0
it's the same design
2019-05-17svga: Add an environment variable to force coherent surface memoryThomas Hellstrom4-3/+18
The vmwgfx driver supports emulated coherent surface memory as of version 2.16. Add en environtment variable to enable this functionality for texture- and buffer maps: SVGA_FORCE_COHERENT. This environment variable should be used for testing only. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2019-05-17pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flagsThomas Hellstrom1-16/+7
In order to be able to add access modes to a pb_validate_entry, update the pb_validate_add_buffer function to take a pointer hash table and also to return whether the buffer was already on the validate list. Update the svga winsys accordingly. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-17winsys/svga: Fix RELOC_INTERNAL mob GPU accessThomas Hellstrom1-1/+9
SVGA_RELOC_INTERNAL indicates a transfer between surface and backing mob. This means that if the GPU for example reads from the surface it writes to the backing mob. But since the buffer mapping code allows for simultaneous gpu- and cpu read access, a read from the surface to the mob will not synchronize a subsequent map to the readback. Fix this by inverting the mob access mode in a surface relocation with SVGA_RELOC_INTERNAL set. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-17svga: Remove the surface_invalidate winsys functionThomas Hellstrom3-18/+0
Instead unconditionally call SVGA3D_InvalidateGBSurface() since it's needed also for Linux for dirty buffers and operation without SurfaceDMA. For non-guest-backed operation, remove the surface cache surface invalidation altogether. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-16r600+radeonsi: use ctx_query_reset_status on radeonMarek Olšák2-8/+0
This allows a nice cleanup, because the winsys always handles it.
2019-05-16winsys/radeon: implement ctx_query_reset_status by copying radeonsiMarek Olšák4-6/+43
To make it behave like amdgpu. I'm just trying to move this out of radeonsi. The radeonsi code will be removed in the next commit.
2019-05-16winsys/amdgpu: report a CS rejection as a reset only if there's no GPU resetMarek Olšák1-6/+5
2019-05-16winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_spaceMarek Olšák2-8/+15
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16winsys/amdgpu: add a parallel compute IB coupled with a gfx IBMarek Olšák3-5/+160
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16winsys/amdgpu: always set NO_CPU_ACCESS and NO_SUBALLOC on GDS resourcesMarek Olšák1-2/+5
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-15ac: rename SI-CIK-VI to GFX6-GFX7-GFX8Marek Olšák5-24/+24
Acked-by: Dave Airlie <airlied@redhat.com> We already use GFX9 and I don't want us to have confusing naming in the driver. GFXn naming is better from the driver perspective, because it's the real version of the gfx portion of the hw. Also, CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI. It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have nothing to do with GFXn and they have their own version numbers.
2019-05-13v3d: Use driconf to expose non-MSAA texture limits for Xorg.Eric Anholt6-15/+25
The V3D 4.2 HW has a limit to MSAA texture sizes of 4096. With non-MSAA, we can go up to 7680 (actually probably 8138, but that hasn't been validated by the HW team). Exposing 7680 in X11 will allow dual 4k displays.
2019-05-10winsys/amdgpu: add VCN JPEG to no user fence groupLeo Liu1-1/+2
There is no user fence for JPEG, the bug triggering kernel WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT) Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: mesa-stable@lists.freedesktop.org
2019-05-06virgl: export resource_is_busy from winsysChia-I Wu2-11/+14
Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-02svga: move host logging to winsysCharmaine Lee5-0/+495
This patch adds a host_log interface to svga_winsys and moves the host logging code to the winsys layer. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Neha Bhende <bhenden@vmware.com>
2019-05-02winsys/svga: Don't abort on EBUSY errors from execbufferThomas Hellstrom1-1/+3
This error code typically indicated that a buffer object that was referenced by the command stream was being used for CPU access by another client. The correct action here is to retry after a while. Use usleep() until we have proper kernel support for this wait. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2019-05-02winsys/svga: Update the drm interface fileThomas Hellstrom2-174/+188
The file vmwgfx_drm.h was a bit outdated. Update to a recent version, including defines supporting coherent memory. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2019-05-02winsys/svga: Enable the transfer_from_buffer GPU command for vgpu10Thomas Hellstrom1-0/+1
We didn't have the path using this command enabled as typically we take an alternate path using DMA uploads. Emable it so that we can exercise that code-path by turning off the DMA path. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2019-05-02winsys/svga: Add an environment variable to force host-backed operationThomas Hellstrom1-6/+11
The vmwgfx kernel module has a compatibility mode for user-space that is not guest-backed resource aware. Add an environment variable to facilitate testing of this mode on guest-backed aware kernels: if the environment variable SVGA_FORCE_HOST_BACKED is defined, the driver will use host-backed operation. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2019-04-30winsys/svga/drm: Include sys/types.hKhem Raj1-0/+1
vmw_screen.h uses dev_t which is defines in sys/types.h this header is required to be included for getting dev_t definition. This issue happens on musl C library, it is hidden on glibc since sys/types.h is included through another system headers Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-04-26vc4: Fall back to renderonly if the vc4 driver doesn't have v3d.Eric Anholt2-3/+35
I have a platform with vc4 display but V3D 4.x. We can fall back on kmsro's probing to bring up the v3d gallium driver. Acked-by: Rob Clark <robdclark@chromium.org>
2019-04-26kmsro: Add support for V3D.Eric Anholt2-0/+16
Like vc4, we expect to have SOCs with various displays that have a single V3D instance for rendering. v2: Add v3d to the list of drivers that make enabling kmsro valid. Acked-by: Rob Clark <robdclark@chromium.org>
2019-04-25virgl/drm: insert correct handles into the table. (v3)Dave Airlie1-1/+4
This inserts a handle for the flink name and a handle the correct gem handle for the bo. v2: fix handles/names confusion (Lepton Wu) v3: set flink name correctly (Lepton Wu) Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-04-25virgl/drm: handle flink name better.Dave Airlie2-20/+11
This realigns this code with code from radeon. Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-04-25virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2-15/+13
This cleans up and realigns this code with what is in radeon v2: fix names->handles (Lepton Wu) Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-04-23winsys/amdgpu: clean up and remove nonsensical assertionMarek Olšák1-2/+1
The assertion considers max_dw from the current IB in the chain, but big_ib_buffer is a buffer for the next IB, which can be smaller. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23winsys/amdgpu: enable chaining for compute IBsMarek Olšák1-6/+6
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE lastMarek Olšák1-19/+17
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23winsys/amdgpu: make IBs writable and expose their addressMarek Olšák1-1/+3
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák1-7/+0
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-22iris: Add mechanism for iris-specific driconf optionsKenneth Graunke2-3/+5
Based on Nicolai's 0f8c5de8690e7c87aa2e24383065efaca7e6fe78. Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-04-21lima: add Android buildIcenowy Zheng1-0/+32
Currently only meson build supported is added for lima driver. Add Android build support for lima. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Qiang Yu <yuq825@gmail.com>
2019-04-18virgl/vtest: bump up protocol version + support encoded transfersGurchetan Singh3-3/+12
This more accurately reflects what the drm winsys does. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-By: Gert Wollny <gert.wollny@collabora.com> Reviewed-By: Piotr Rak <p.rak@samsung.com>
2019-04-18virgl/vtest: wait after issuing a transfer getGurchetan Singh1-2/+3
Otherwise, there's artifacts when running Unigine Valley with protocol version 2. We can get away with not waiting for most buffers, but let's be conservative. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-By: Gert Wollny <gert.wollny@collabora.com> Reviewed-By: Piotr Rak <p.rak@samsung.com>
2019-04-18virgl/vtest: modify sending and receiving data for shared memoryGurchetan Singh1-4/+35
We need to copy the shared memory region to the display target. Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-By: Gert Wollny <gert.wollny@collabora.com> Reviewed-By: Piotr Rak <p.rak@samsung.com>
2019-04-18virgl/vtest: receive and handle shared memory fdGurchetan Singh2-7/+55
The only tricky part is with protocol 0 we can either have a display target or resource backing store. With protocol 2 we can have both. Make the map/unmap functions only deal with the resource backing store. v2: Handle MSAA texture case. v3: spelling v4: Fix dangling else (@prak) v5: mmap --> os_mmap (@prak) + added comments (@gerddie) Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-By: Gert Wollny <gert.wollny@collabora.com> Reviewed-By: Piotr Rak <p.rak@samsung.com>
2019-04-18virgl/vtest: plumb support for shared memoryGurchetan Singh3-6/+10
Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-By: Gert Wollny <gert.wollny@collabora.com> Reviewed-By: Piotr Rak <p.rak@samsung.com>
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