path: root/src/gallium/winsys
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12 daysgallium: Replace the usage of __FUNCTION__ with __func__ in all gallium codeYonggang Luo6-24/+24
Signed-off-by: Yonggang Luo <> Acked-by: Erik Faye-Lund <> Acked-by: David Heidelberg <> Part-of: <>
2022-11-19util: Move src/gallium/include/pipe/p_format.h to src/util/format/u_formats.hYonggang Luo7-7/+7
Because p_format.h shared between vulkan drivers and opengl drivers Signed-off-by: Yonggang Luo <> Reviewed-by: Marek Olšák <> Part-of: <>
2022-11-15tree-wide: Convert all usage of PIPE_(OS|ARCH|CC)_* to DETECT_(OS|ARCH|CC)_* ↵Yonggang Luo1-2/+2
by use grep This should be the last commit, and should be take care that can only in comment block or version Exclude files: src/util/detect_*.h From: PIPE_(OS|ARCH|CC)_([0-9A-Z_]+) To: DETECT_$1_$2 Signed-off-by: Yonggang Luo <> Reviewed-by: Marek Olšák <> Part-of: <>
2022-11-15tree-wide: Convert all usage of defined(PIPE_(OS|ARCH|CC)_*) to ↵Yonggang Luo2-4/+4
DETECT_(OS|ARCH|CC)_* by use grep From: defined[\s]*\([\s]*PIPE_(OS|ARCH|CC)_([0-9A-Z_]+)[\s]*\) To: DETECT_$1_$2 Signed-off-by: Yonggang Luo <> Reviewed-by: Marek Olšák <> Part-of: <>
2022-11-15util: Rename src/gallium/include/pipe/p_config.h to src/util/detect_arch.hYonggang Luo1-1/+1
Even though the defines in p_config.h are stared with PIPE_, they are indeed are generic detecting mechanics, we will rename them to DETECT_* in latter MR We rename src/gallium/include/pipe/p_config.h src/util/detect_arch.h because the detect code in src/gallium/include/pipe/p_config.h are most about processor architecture detecting. The file util/detect.h is added to replace functional of src/gallium/include/pipe/p_config.h So we replace of #include "pipe/p_config.h" with #include "util/detect.h" The file util/detect_cc.h is added as a placeholder for moving compiler related macro defines from p_config.h into it in following commits Signed-off-by: Yonggang Luo <> Reviewed-by: Marek Olšák <> Part-of: <>
2022-11-15util: Move src/gallium/auxiliary/os/os_mman.h to src/util/os_mman.hYonggang Luo4-4/+4
Use "util/detect_os.h" instead of "pipe/p_config.h" and "pipe/p_compiler.h" in src/util/os_mman.h This is a prepare to implement os_mman on windows Signed-off-by: Yonggang Luo <> Reviewed-by: Marek Olšák <> Part-of: <>
2022-11-09nvc0: recognise ga10x chipsetsBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <> Acked-by: M Henning <> Reviewed-by: Adam Jackson <> Reviewed-by: Karol Herbst <> Part-of: <>
2022-11-08util: Remove os/os_thread.h and replace #include "os/os_thread.h" with ↵Yonggang Luo10-10/+10
#include "util/u_thread.h" Signed-off-by: Yonggang Luo <> Reviewed-by: Jesse Natalie <> Part-of: <>
2022-11-07intel: Add and use intel_gem_get_param()José Roberto de Souza2-9/+4
Again sharing the same function across all Intel drivers. Reviewed-by: Tapani Pälli <> Signed-off-by: José Roberto de Souza <> Part-of: <>
2022-10-31winsys/amdgpu: clamp up the alignment if zeroSunil Khatri1-1/+2
Zero alignment buffers is a valid alignment and is used for the cases when there is no special alignment enforced due to hardware requirement. Clamp up the buffer alignment of such buffers to gart_page_size. Screenshot app uses such buffers with zero alignment which is returned NULL by winsys and failed and hence failed to capture. Signed-off-by: Sunil Khatri <> Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-10-29gallium: Stub support for Asahi + DRMAlyssa Rosenzweig5-0/+132
Copy-paste a pile of winsys code from panfrost and find-and-replace the name to asahi. This should contain all the glue code needed for asahi+kmsro. The kernel driver is under way (led by Asahi Lina, not me), but it's not wred up here. My goal was rather to run shader-db, which expects a render node, which means drm-shim, which means DRM loader support. With this patch and a trivial drm-shim, shader-db runs. In general I am reticent to touch UABI related code when the UABI hasn't been finalized upstream, or started design at all, hence the RFC. Realistically this patch assumes the following about the future UABI: 0. It will be a DRM driver. This is nonnegotiable. 1. The render node will be named "asahi". The other reasonable name would be "apple", which I'm using for the display controller (not yet upstream, but getting close). 2. Display and rendering will be split in the kernel, requiring kmsro in userspace, as agreed in past discussions. The 3D accelerator (AGX) and the display controller (DCP) are completely orthogonal blocks with separate lineages. True, Apple A14 (~= M1) has AGX and DCP together, and it seems like all the chips that will get upstream support will have this for the forseeable future. Nevertheless, it's a historical coincidence. Apple A12 had an AGX block with a pre-DCP Apple display controller, which would use a completely different display driver. Older SoCs had a PowerVR block with an Apple shader core, with a pre-DCP Apple display controller. Even older SoCs had a pure PowerVR block (+ Apple display). The AGX and DCP kernel drivers are not expected to share any nontrivial code. We don't gain anything by bundling them together. Likewise, the many codec blocks are completely orthogonal. This is all standard practice for Arm SoCs. It is true that AGX has never been used with a non-Apple display controller; it is highly unlikely this would change (either by AGX licensing out or something like Mali-DP getting licensed in). But an extra kmsro user doesn't actually add more complexity to Mesa, so shrug. Signed-off-by: Alyssa Rosenzweig <> Reviewed-by: Eric Engestrom <> [meson, ack on gallium] Part-of: <>
2022-10-26winsys/amdgpu: Set RADEON_FLAG_32BIT againMichel Dänzer1-0/+9
Avoids hang running rendercheck -t cacomposite -f a8r8g8b8 via glamor on Navi 14. Closes: Fixes: 7833c5139a54 ("winsys/amdgpu: use cached GTT for command buffers and don't set the 32BIT flag") Reviewed-by: Marek Olšák <> Part-of: <>
2022-10-18winsys/amdgpu: fix (enable) preemption for chained IBsMarek Olšák1-1/+2
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-10-14util/mesa/wide: Rename _SIMPLE_MTX_INITIALIZER_NP to SIMPLE_MTX_INITIALIZERYonggang Luo1-1/+1
Signed-off-by: Yonggang Luo <> Reviewed-by: Jesse Natalie <> Part-of: <>
2022-09-23winsys/amdgpu: init 'r' before using itPierre-Eric Pelloux-Prayer1-0/+2
Reviewed-by: Marek Olšák <> Fixes: 471c82d21ef ("winsys/amdgpu: flatten huge if and reorder code in amdgpu_cs_submit_ib") Part-of: <>
2022-09-10virgl: Set use_staging in resource_from_handleIsaac Bosompem1-0/+8
This flag controls virgl's behavior when buffers are accessed on the guest through Mesa's GBM interface. As such, this flag needs to be consistent in both the resource creation and fd import case. Previously, the fd import resource's flag value would be inconsistent with the original resource's value. This patch fixes this by inferring the value of this flag based on the resource's size. Signed-Off By: Isaac Bosompem <> Part-of: <>
2022-08-31radeonsi/sqtt: set stable pstate if possiblePierre-Eric Pelloux-Prayer2-0/+35
This avoids the need to manually change the power profile. Reviewed-by: Mihai Preda <> Part-of: <>
2022-08-31d3d12: Change displayable format logicJesse Natalie1-0/+6
Instead of not reporting support for the pixel format at all, just disable swapchain creation. Some apps want to create off-screen contexts targeting these formats, but since WGL doesn't really have "off-screen," the pixel format enumeration should return support for these. Reviewed-by: Giancarlo Devich <> Part-of: <>
2022-08-29winsys/amdgpu: use cached GTT for command buffers and don't set the 32BIT flagMarek Olšák1-12/+5
This improves performance a lot in a few viewperf tests. The 32-bit flag was unnecessary. Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-08-29virgl: Fix buffer overflow warning:Gert Wollny1-1/+1
./src/gallium/winsys/virgl/drm/virgl_drm_winsys.c: In function ‘virgl_drm_winsys_resource_set_type’: ../src/gallium/winsys/virgl/drm/virgl_drm_winsys.c:607:10: warning: array subscript 14 is above array bounds of ‘uint32_t[14]’ {aka ‘unsigned int[14]’} [-Warray-bounds] 607 | cmd[VIRGL_PIPE_RES_SET_TYPE_PLANE_OFFSET(i)] = plane_offsets[i]; | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../src/gallium/winsys/virgl/drm/virgl_drm_winsys.c:582:13: note: while referencing ‘cmd’ 582 | uint32_t cmd[VIRGL_PIPE_RES_SET_TYPE_SIZE(VIRGL_MAX_PLANE_COUNT)]; | ^~~ Signed-off-by: Gert Wollny <> Part-of: <>
2022-08-25winsys/amdgpu: fix non-page-aligned sparse buffer creationQiang Yu1-1/+1
ARB_sparse_buffer does not require sparse buffer size to be page aligned. So we need to align it before VM ops as KMD will check whether it's aligned and return EINVAL if not. Fixes: 667da4eaed3 ("winsys/amdgpu: sparse buffer creation / destruction / commitment") Closes: Reviewed-by: Marek Olšák <> Signed-off-by: Qiang Yu <> Part-of: <>
2022-08-23iris: Drop extra file-descriptor dup in iris_drm_screen_create()Jordan Justen1-4/+1
In a99e85db9eb, we added a dup into iris_screen_create(). Apparently some android code paths must be hitting iris_screen_create() without calling iris_drm_screen_create(). After a99e85db9eb, the code paths that do hit iris_drm_screen_create() will now dup the fd twice, but iris_screen_destroy() will only close 1 of these fds. Fixes: a99e85db9eb ("iris:Duplicate DRM fd internally instead of reuse.") Signed-off-by: Jordan Justen <> Reviewed-by: Kenneth Graunke <> Tested-by: Tapani Pälli <> Reviewed-by: José Roberto de Souza <> Part-of: <>
2022-08-19winsys/amdgpu: change num_rejected_cs to a bool flagMarek Olšák2-5/+6
and don't increment the total sum after the first rejection Reviewed-by: Mihai Preda <> Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-08-19winsys/amdgpu: flatten huge if and reorder code in amdgpu_cs_submit_ibMarek Olšák1-138/+131
This correctly tracks when we get a failure and jump to cleanup. Reviewed-by: Mihai Preda <> Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-08-19winsys/amdgpu: terminate process on CS rejection when unrobust context is lostMarek Olšák1-1/+11
We agreed on this with the kernel team as the most graceful way to deal with this scenario. Remove the allow_context_lost use because it's always true there if num_rejected_cs is true. Reviewed-by: Mihai Preda <> Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-08-19radeonsi: rename stop_exec_on_failure -> allow_context_lostMarek Olšák3-5/+5
Reviewed-by: Mihai Preda <> Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-08-10wgl: Allow per-framebuffer swap interval overridesJesse Natalie1-3/+3
Acked-by: Daniel Stone <> Acked-by: Mike Blumenkrantz <> Acked-by: Sidney Just <> Acked-by: Jason Ekstrand <> Tested-by: Yonggang Luo <> Part-of: <>
2022-08-09amdgpu/bo: update uses_secure_bos when importing buffersPierre-Eric Pelloux-Prayer1-0/+1
Fixes: 90b98c06493 ("amd/tmz: move uses_secure_bos to radeon_winsys") Reviewed-by: Marek Olšák <> Part-of: <>
2022-08-05d3d12: Fixes compile error with mingw/gcc-x64 when static linkage to runtime ↵Yonggang Luo1-0/+1
library Closes #6968 Signed-off-by: Yonggang Luo <> Suggested-by: Jesse Natalie <> Reviewed-by: Jesse Natalie <> Tested-by: Prodea Alexandru-Liviu <> Part-of: <>
2022-08-05virgl/vtest: fix memory overwrite problem in virgl_vtest_send_get_caps()Feng Jiang1-2/+7
Signed-off-by: Feng Jiang <> Part-of: <>
2022-08-02virgl: do not share virgl_screen between different drm_filesFeng Jiang1-1/+38
Now, only one instance of virgl_screen exists for a device (/dev/dri/cardX), and it is shared by different frontends (eg GLX, GBM, etc.). There is a problem with this, as follows: /* Init GLX */ ... glXCreateContext(...); ... /* GBM */ gbm_fd = open("/dev/dri/card0", O_RDWR); dev = gbm_create_device(gbm_fd); bo = gbm_bo_create(dev, ...); plane_handle = gbm_bo_get_handle_for_plane(bo, ...); drmPrimeHandleToFD(gbm_fd, handle.u32, flags, &plane_fd); The above drmPrimeHandleToFD() call will fail with ENOENT. The reason is that GBM and GLX share the same virgl_screen (file descriptor), and it is not gbm_fd that is used to create gbm_bo, but other fd (opened during GLX initialization). Since the scope of prime handle is limited to drm_file, the above plane_handle is invalid under gbm_fd. By canceling the sharing of virgl_screen between different drm_files, GBM can use the correct fd to create resources, thereby avoiding the problem of invalid prime handle. Signed-off-by: Feng Jiang <> Reviewed-by: Gert Wollny <> Part-of: <>
2022-08-02virgl: Set res->maybe_busy to true when creating resourcesJiang Feng1-1/+1
Currently, res->maybe_busy is false by default. If wait immediately after the resource is created, virgl_drm_resource_wait() will return directly without checking the actual state of the kernel, which will cause synchronization problems, such as: On Guest: pipe_buffer_create [mesa] virgl_drm_winsys_resource_create virtio_gpu_resource_create_ioctl [kernel] virtio_gpu_fence_alloc virtio_gpu_object_create virtio_gpu_cmd_resource_create_3d VIRTIO_GPU_CMD_RESOURCE_CREATE_3D virtio_gpu_object_attach virtio_gpu_cmd_resource_attach_backing VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING resource_wait [mesa] virgl_drm_resource_wait /* return directly without fence waiting */ pipe_buffer_map [mesa] virgl_drm_resource_map virtio_gpu_map_ioctl [kernel] os_mmap memcpy /* <== here */ On Host (with QEMU): VIRTIO_GPU_CMD_RESOURCE_CREATE_3D virgl_cmd_create_resource_3d [qemu] virgl_renderer_resource_create [virglrenderer] VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING virgl_resource_attach_backing [qemu] virtio_gpu_create_mapping_iov virgl_renderer_resource_attach_iov [virglrenderer] virgl_resource_attach_iov vrend_pipe_resource_attach_iov vrend_write_to_iovec /* <== here */ virtio_gpu_cleanup_mapping_iov [qemu] In the example above, there is a race condition between memcpy and vrend_write_to_iovec. Signed-off-by: Jiang Feng <> Reviewed-by: Gert Wollny <> Reviewed-by: Chia-I Wu <> Part-of: <>
2022-07-28util/list: rename LIST_ENTRY() to list_entry()Eric Engestrom1-3/+3
This follows the Linux kernel convention, and avoids collision with macOS header macro. Closes: Closes: Cc: mesa-stable Signed-off-by: Eric Engestrom <> Acked-by: David Heidelberg <> Reviewed-by: Yonggang Luo <> Part-of: <>
2022-07-27gallium/radeon: require radeon DRM 2.50.0 (kernel 4.12) from July 2017Marek Olšák1-8/+2
This is the latest radeon DRM version. Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: remove unused has_unaligned_shader_loadsMarek Olšák1-3/+0
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: remove amdgpu_gpu_info parameter from ac_query_gpu_infoMarek Olšák2-2/+1
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27radeonsi: remove workarounds for radeon DRM < 2.45.0Marek Olšák2-15/+0
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27gallium/radeon: require radeon DRM 2.45.0 from April 2016Marek Olšák2-64/+39
This removes most non-radeonsi workarounds. Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27amd: require amdgpu DRM 3.2.0 from April 2016Marek Olšák1-1/+0
This removes an early bug workaround. Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: remove redundant vce_encodeMarek Olšák1-2/+0
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: remove redundant uvd_decodeMarek Olšák1-2/+0
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: remove vram_size and gtt_size in favor of *_kb variantsMarek Olšák2-9/+6
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: rework and extend device info to be more informativeMarek Olšák1-2/+2
This is the result with AMD_DEBUG=info: Device info: name = NAVI23 marketing_name = AMD Radeon RX 6600 num_se = 2 num_rb = 8 num_cu = 28 max_gpu_freq = 2750 MHz max_gflops = 9856 GFLOPS l0_cache_size = 16 KB l1_cache_size = 128 KB l2_cache_size = 2048 KB l3_cache_size = 32 MB memory_channels = 8 (TCC blocks) memory_size = 8 GB (8192 MB) memory_freq = 14 GHz memory_bus_width = 128 bits memory_bandwidth = 224 GB/s clock_crystal_freq = 100000 KHz IP GFX 10.3 queues:1 IP COMP 10.3 queues:4 IP SDMA 5.2 queues:2 IP VCN_DEC 3.0 queues:1 IP VCN_ENC 3.0 queues:1 IP VCN_JPG 3.0 queues:1 It might not be 100% correct with other chips. Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-27ac/gpu_info: rename info fields to num_cu, memory_bus_width, memory_freq_mhzMarek Olšák1-3/+3
Reviewed-by: Pierre-Eric Pelloux-Prayer <> Part-of: <>
2022-07-18kms/dri: add mutex lock around map/unmapDave Airlie1-2/+18
this can get called from multiple threads with the recent llvmpipe overlapping rendering changes, so make sure to lock around the map/unmapping so they can't race. This should fixes some crashes seen with kwin. Reviewed-by: Mike Blumenkrantz <> Tested-by: Adam Williamson (Fedora) Cc: mesa-stable Part-of: <>
2022-07-15d3d12: Add helpers to build with correct ABI for MinGWJesse Natalie1-1/+1
Reviewed-by: Bill Kristiansen <> Reviewed-by: Sil Vilerino <> Part-of: <>
2022-06-23d3d12: Fixes compiling error in d3d12/wgl/d3d12_wgl_framebuffer.cpp with gccYonggang Luo1-0/+2
error message: ``` ../../src/gallium/winsys/d3d12/wgl/d3d12_wgl_framebuffer.cpp:231:42: error: no matching function for call to 'operator new(sizetype, d3d12_wgl_framebuffer*&)' 231 | new (fb) struct d3d12_wgl_framebuffer(); | ^ <built-in>: note: candidate: 'void* operator new(long long unsigned int)' Signed-off-by: Yonggang Luo <> Reviewed-by: Jesse Natalie <> Acked-by: Daniel Stone <> Part-of: <>
2022-06-22radeon: Support shared memory user pointers.Jason Volk2-5/+13
The RADEON_GEM_USERPTR_ANONONLY flag is hardcoded here which excludes shared memory pages. DRM is actually capable of supporting shared file- backed memory, but only if it's read-only. This mutability intent has to be conveyed through the stack, so a flags argument is added to the winsys regime to pass RADEON_FLAG_READ_ONLY. Part-of: <>
2022-06-16kmsro: add error message on drm ioctl failureMike Blumenkrantz1-1/+4
Reviewed-by: Adam Jackson <> Part-of: <>
2022-06-15c11: Implement thread_local in c11/threads.hYonggang Luo1-1/+2
Use thread_local when possible Signed-off-by: Yonggang Luo <> Reviewed-by: Jesse Natalie <> Part-of: <>