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2021-06-21freedreno: Handle full blit discards by invalidating the resource.Emma Anholt1-6/+0
The previous implementation had several issues: - It wasn't checking all the conditions necessary for "this blit updates the whole surface", like PIPE_MASK_Z but not S on a depth/stencil buffer. - It would reset the previous batchbuffer, even if that batch had side effects on other buffers. - The layering was painful to follow and made any recursion extra dangerous. Now, we use a more conservative test (enough for the resource shadowing case) and just invalidate the buffer up front, which should have the right logic for discarding drawing to that resource. I found I had to add fd_bc_flush_writer() to the end of fd_blitter_blit() -- a flush was happening at fb state restore time when the discard flag was set, and losing that flush breaks dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11455>
2021-06-21freedreno: Flush if at risk of overflowing bos tableRob Clark4-1/+50
Fixes overflow crash in tex-miplevel-selection Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4007 Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11487>
2021-06-21freedreno/a6xx: Handle fb_read in sysmem pathRob Clark1-10/+0
Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11487>
2021-06-21freedreno/ci: Garbage collect some a630 flakesRob Clark1-6/+0
Haven't seen these, at least since flake reporting switched to OFTC channel (~1 month ago) Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11487>
2021-06-21nir/propagate_invariant: add invariant_prim optionRhys Perry1-1/+1
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11035>
2021-06-18freedreno/ci: Increase # of jobs for CI runnersRob Clark1-0/+1
The idea is that the tests will spend *some* time stalling waiting to read back results from the GPU. So use a # of jobs that is slightly more than the # of CPUs to keep the CPUs more busy. Locally this is dropping a bit more than a minute off a parallel deqp-gles31 run, so turn it on across the board for a6xx. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
2021-06-18freedreno/ci: Start longest traces firstRob Clark1-81/+96
Shave off a bit of runtime on the CI job by starting the longer traces first. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
2021-06-18freedreno/ir3: Move NIR printing to mesa_log.Emma Anholt4-28/+28
Now we can get some NIR debug on Android. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18freedreno/ir3: Move the native code output to mesa_log as well.Emma Anholt1-3/+11
I didn't feel like rewriting ir3_shader_disasm() off of FILE *s, so use the same trick as the disasm_info path above to write to memory and then hand the multi-line blob off to mesa_log. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18freedreno/ir3: Use mesa_log_stream() for ir3 disassembly.Emma Anholt2-116/+121
This means you can get dumps on android, and output on Linux goes to stderr. However, this does mean that on Linux the output goes from looking like: AFTER: ir3_legalize: block3276208368 { 0000:0001:002: cov.u32s16 hr2.x, c2.x 0000:0002:002: mov.u32u32 r0.x, c0.x [...] to: MESA: info: AFTER: ir3_legalize: MESA: info: block3405271904 { MESA: info: 0000:0001:002: cov.u32s16 hr2.x, c2.x MESA: info: 0000:0002:002: mov.u32u32 r0.x, c0.x Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18freedreno/ir3: Move the assert output to mesa_loge().Emma Anholt1-1/+2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-17freedreno: Add some cheza flakes from the last week.Emma Anholt1-1/+8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11453>
2021-06-17freedreno/fdl: Give the tiling mode a nice name in debug dumps.Emma Anholt2-2/+15
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
2021-06-16ir3/ra: Fix array parallelcopy confusionConnor Abbott2-7/+12
With array registers, there are two num's we care about: 1. The base num that the whole array starts at (->array.base) 2. The num that the instruction uses, plus possibly an indirect offset (->num or ->array.offset) For parallel copies we always copy the whole array, so (2) is irrelevant here. For phis and parallel copies inserted for phis, we used assign_reg() which assigned ->array.base, but we forgot about this when constructing our own parallel copies for live range splitting, just setting ->num instead. The parallel copy lowering was also inconsistent here, using ra_reg_get_num() (which looks at ->array.base for arrays) for sources but looking at ->num directly for destinations. This makes everything use ->array.base consistently. While we're here, make sure to remove IR3_REG_SSA from liveout copies to make sure printing works correctly. Fixes: 0ffcb19 ("ir3: Rewrite register allocation") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
2021-06-16ir3: Improve printing of array parallelcopies/phisConnor Abbott2-2/+8
Normally something with IR3_REG_ARRAY doesn't have a register assigned, but we keep IR3_REG_ARRAY for parallel copies after RA because we need to know the appropriate size. We want to see the register assigned for these when printing the RA result before parallel copies are lowered. The register is in ->array.base in this case, so initialize it to INVALID_REG and print ->array.base if it's been assigned to something, similar to ->num in the normal case. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
2021-06-16util/queue: add a global data pointer for the queue objectMike Blumenkrantz2-3/+3
this better enables object-specific (e.g., context) queues where the owner of the queue will always be needed and various pointers will be passed in for tasks Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11312>
2021-06-15freedreno: Be more strict about QUERY_AVAILABLE to simplify the code.Emma Anholt1-0/+1
ARB_oq doesn't just say "polling in a loop will make it complete eventually", it says "querying will make it complete in finite time." Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11368>
2021-06-15freedreno/registers: define REG_DSI_CPHY_MODE_CTRLJonathan Marek1-0/+1
For use by the kernel driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11381>
2021-06-15ci: Unify {BARE_METAL,LAVA}_TEST_SCRIPT environmentDaniel Stone1-5/+5
Should also probably never have been different. Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Martin Peres <martin.peres@mupuf.org> Acked-by: Emma Anholt <emma@anholt.net> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
2021-06-15ci: Unify {BM,LAVA}_START_XORG environmentDaniel Stone1-4/+4
Why were they ever different ... ? Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Martin Peres <martin.peres@mupuf.org> Acked-by: Emma Anholt <emma@anholt.net> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11337>
2021-06-15turnip: Copy command buffers to deferred submit requestHyunjun Ko1-45/+80
To make sure the index of global bo table in drm_msm_gem_submit_cmd is valid at actual submit time. v1. Move the entry_count calculation into the submit request creation function. Fixes: #4877 Fixes: 3f229e34 ("turnip: Implement VK_KHR_timeline_semaphore.") Signed-off-by: Hyunjun Ko <zzoon@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11260>
2021-06-14ci/deqp: Skip dEQP-VK.wsi.display.get_display_plane_capabilitiesEmma Anholt1-3/+0
The flakiness of this test is due to CI running deqp in parallel, rather than exposing any underlying driver issue. Just skip it in CI until we come up with a reasonable way to handle tests to be run in isolation during a deqp-runner run (likely as part of https://gitlab.freedesktop.org/anholt/deqp-runner/-/issues/7). Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
2021-06-14ci/deqp: Skip flush_finish on all CI jobs.Emma Anholt2-6/+0
They're too slow to run in CI even on non-tiled renderers, they don't block conformance (unless you crash), and provide unreliable warning results unless you isolate them from other activity on the system. This means that the following jobs now skip these tests: - deqp-iris-* - deqp-llvmpipe (you know, the one mentioned in the comment!) - deqp-virgl-gl - deqp-zink-lvp Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
2021-06-14ci/deqp: Drop stress/perf skips lists.Emma Anholt2-8/+0
The mustpass doesn't have any tests matching these, so no need to skip. These tests only show up if you run without using a mustpass list. Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
2021-06-14freedreno/drm-shim: keep GEM buffers page-alignedAlexander Monakov1-3/+6
Trying to run turnip under drm-shim reveals that pretended device offsets are not sufficiently aligned, failing this assert in tu_pipeline.c: /* emit program binary & private memory layout * binary_iova should be aligned to 1 instrlen unit (128 bytes) */ assert((binary_iova & 0x7f) == 0); Round up BO size to 4096 in msm_ioctl_gem_new to avoid this (the kernel aligns to page size). Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
2021-06-14freedreno/drm-shim: pretend to offer DRM 1.6.0Alexander Monakov1-1/+1
turnip's DRM device interface requires version 1.6 (for SYNCOBJ). To unblock use of turnip over drm-shim, raise shim's version to 1.6. This allows to see shader disassembly, while submission fails with DRM_SHIM: unhandled core DRM ioctl 0xC4 (0xc01064c4) TU: error: DRM_IOCTL_SYNCOBJ_RESET failure: Invalid argument Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
2021-06-14turnip: add missing VKAPI_ATTR/CALLHyunjun Ko18-280/+291
Signed-off-by: Hyunjun Ko <zzoon@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11099>
2021-06-13freedreno/a6xx: Fix r16_snorm blitsRob Clark1-13/+13
The .NORM bit doesn't seem to do what we think or want.. tu also doesn't set it, and things seem to work out better when we don't. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11343>
2021-06-11freedreno/registers: add A5XX_RBBM_STATUS3 bitRob Clark1-1/+3
Same bit as a6xx. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
2021-06-10ci/freedreno: Enable running all of piglit_gl for a530's manual test.Emma Anholt1-2/+2
Otherwise the xfails will end up stale after piglit uprevs that change the test set. Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
2021-06-10ir3: Copy propagate immed/const to meta instructionsConnor Abbott2-13/+53
This is allowed with the new RA, and makes a huge difference in preventing extra moves when preferential coloring doesn't work. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Insert output collects in the main shaderConnor Abbott1-0/+11
We were inserting them in what was NIR's end block with the "end" instruction, which meant that the moves they generated couldn't be scheduled with the rest of the last block as part of post-RA scheduling. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Add simple CSE passConnor Abbott4-0/+150
RA currently can't handle a live value that's part of a vector and introduces extra copies. This was espeically a problem for bary.f, where the bary coords were being split and repeatedly re-collected. But this could be a problem in other situations as well. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/sched: Consider unused destinations when computing live effectConnor Abbott1-1/+1
If an instruction's destination is unused, then we shouldn't penalize it. For example, this helps us schedule atomic operations whose results aren't read. This works around RA failures when CSE is enabled in some robustness2 tests. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/sched: Make collects count against tex/sfu limitsConnor Abbott1-6/+25
In a scenario where there are a lot of texture fetches with constant coordinates, this prevents the scheduler from scheduling all the setup instructions after the first group of textures has been scheduled because they are the only non-syncing thing and scheduling them didn't decrease tex_delay. Collects with immed/const sources will turn into moves of those sources, so we should treat them the same. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/sched: Don't schedule collect earlyConnor Abbott1-1/+10
I don't think there was ever a good reason to do this, but when we start folding constants/immediates into collect, this can become actively harmful. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Remove right and left copy prop restrictionsConnor Abbott5-114/+0
This is leftover from the old RA, and inhibits copy propagation unnecessarily with the new RA. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/ra: Add a validation passConnor Abbott4-0/+562
This helps catch tricky-to-debug bugs in RA, or helps rule them out. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Rewrite register allocationConnor Abbott18-2090/+3532
Switch to the new SSA-based register allocator. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Expose occupancy calculation functionsConnor Abbott2-11/+20
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Add pass to lower arrays to SSAConnor Abbott3-0/+303
This will be run right after nir->ir3. Even though we have SSA coming out of NIR, we still need it for NIR registers, even though we keep the original array around to insert false dependencies. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Add dominance infrastructureConnor Abbott3-0/+138
Mostly lifted from nir. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Remove unused check_src_cond()Connor Abbott1-27/+0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/postsched: Don't use SSA source informationConnor Abbott1-4/+24
This was only used for calculating if a source is a tex or SFU instruction, which is easily replacable. It's going away with the new RA. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/delay: Delete pre-RA repeat handlingConnor Abbott1-22/+0
It looks likely that any implementation of (rptN) in ir3 will have to actually create (rptN) instructions after RA, which means that this can be dropped. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Rewrite delay calculationConnor Abbott6-218/+256
The old delay calculation relied on the SSA information staying around, and wouldn't work once we start introducing phi nodes and making "normal" values defined in multiple blocks not array regs anymore. What's worse is that properly inserting phi nodes when splitting live ranges would make that code even more complicated, and this was the last place post-RA that actually needed that information. The new version only compares the physical registers of sources and destinations. It works by going backwards up to a maximum number of cycles, so it might be slightly slower when the definition is closer but should be faster when it is farther away. To avoid complicating the new method, the old method is kept around, but only for pre-RA scheduling and it can therefore be drastically simplified as the array case can be dropped. ir3_delay_calc() is split into a few variants to avoid an explosion of boolean arguments in users, especially now that merged_regs now has to be passed to it. The new method is a little more complicated when it comes to handling (rptN), because both the assigner and consumer may be (rptN). This adds some unit tests for those cases, in addition to dropping the to-SSA code in the test harness since it's no longer needed. Finally, ir3_legalize has to be switched to using physical registers for the branch condition. This was the one place where IR3_REG_SSA remained after RA. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Make branch conditions non-SSAConnor Abbott2-8/+14
In particular, make sure they have a physreg assigned. This was the last place after RA where SSA registers were created, which won't work with the new post-RA delay calculation that relies on the physreg. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Add reg_elems(), reg_elem_size(), and reg_size()Connor Abbott1-0/+20
For working with registers in units of half-regs in the new RA. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3/delay: Fix full->half and half->full delayConnor Abbott1-5/+18
The current compiler never does this, but the new compiler will start to in mergeregs mode. There is an extra penalty for this. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
2021-06-10ir3: Add ir3_register::array.baseConnor Abbott4-9/+9
There were two different approaches I saw in the post-RA code for figuring out what regiser range a relative access touched: 1. Use reg->array.offset and reg->array.size. This is wrong in case reg->array.offset was non-zero before RA, because array.size is the size of the whole array and array.offset has the const offset within the array baked in. 2. Lookup the array from the array ID and use the base + range there. This is correct, but won't work with the new RA, where an array might not always be assigned to the same register. This replaces both methods with a new ir3_register::array.base field, and switches all the users I could find to it. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-15 03:37:32 +0000