diff options
| author | Connor Abbott <cwabbott0@gmail.com> | 2021-05-17 16:16:55 +0200 |
|---|---|---|
| committer | Emma Anholt <emma@anholt.net> | 2021-06-10 12:20:38 -0700 |
| commit | c947475533a61c0461a82ec9924ce4279f17e9fc (patch) | |
| tree | cfcf403b42dd2e38d45b50492f340746d66ddd42 /src/freedreno | |
| parent | 58d82add87ede4dc6533f97f7e23e4ba09e1d242 (diff) | |
ir3/delay: Delete pre-RA repeat handling
It looks likely that any implementation of (rptN) in ir3 will have to
actually create (rptN) instructions after RA, which means that this can
be dropped.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Diffstat (limited to 'src/freedreno')
| -rw-r--r-- | src/freedreno/ir3/ir3_delay.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/freedreno/ir3/ir3_delay.c b/src/freedreno/ir3/ir3_delay.c index 1d382b45a80..7a310f236e4 100644 --- a/src/freedreno/ir3/ir3_delay.c +++ b/src/freedreno/ir3/ir3_delay.c @@ -165,28 +165,6 @@ delay_calc_srcn_prera(struct ir3_block *block, continue; d = delay_calc_srcn_prera(block, src->def->instr, consumer, srcn); - - /* A (rptN) instruction executes in consecutive cycles so - * it's outputs are written in successive cycles. And - * likewise for it's (r)'d (incremented) inputs, they are - * read on successive cycles. - * - * So we need to adjust the delay for (rptN)'s assigners - * and consumers accordingly. - * - * Note that the dst of a (rptN) instruction is implicitly - * (r) (the assigner case), although that is not the case - * for src registers. There is exactly one case, bary.f, - * which has a vecN (collect) src that is not (r)'d. - */ - if ((assigner->opc == OPC_META_SPLIT) && src->def->instr->repeat) { - /* (rptN) assigner case: */ - d -= MIN2(d, src->def->instr->repeat - assigner->split.off); - } else if ((assigner->opc == OPC_META_COLLECT) && consumer->repeat && - (consumer->regs[srcn]->flags & IR3_REG_R)) { - d -= MIN2(d, n); - } - delay = MAX2(delay, d); } } else { |