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path: root/src/freedreno/registers
AgeCommit message (Expand)AuthorFilesLines
2021-06-15freedreno/registers: define REG_DSI_CPHY_MODE_CTRLJonathan Marek1-0/+1
2021-06-11freedreno/registers: add A5XX_RBBM_STATUS3 bitRob Clark1-1/+3
2021-06-05freedreno/regs: split old/not used phy registers to separate DBDmitry Baryshkov3-64/+76
2021-05-31freedreno/headergen2: Fix compile warnings with CP_DRAW_INDIRECT_MULTIRob Clark1-3/+3
2021-05-31freedreno/registers: Add a few a6xx regs and notesRob Clark2-3/+74
2021-05-31freedreno/afuc: Add pipe reg name decodingRob Clark1-0/+3
2021-05-16freedreno/a6xx: Add a few registersRob Clark2-0/+6
2021-05-16freedreno/regs: split DSI PHY registers to separate xml files.Dmitry Baryshkov9-1059/+1115
2021-05-07freedreno/a5xx: SP_BLEND_CNTL has per-mrt blend enable bitDanylo Piliaiev1-1/+2
2021-05-07turnip,freedreno/a6xx: SP_BLEND_CNTL has per-mrt blend enable bitDanylo Piliaiev1-1/+2
2021-05-05freedreno/a5xx: Fix up border color pointers.Eric Anholt1-1/+1
2021-05-03freedreno/a6xx: Better document SP_GS_PRIM_SIZEConnor Abbott1-1/+14
2021-04-21freedreno/regs: add 5nm DSI PHY/PLL regsRobert Foss1-0/+221
2021-04-15turnip: document GRAS_LRZ_CNTL's UNK5 bitfieldSamuel Iglesias Gonsálvez1-1/+2
2021-04-01turnip: enable infinities for f16 math and document the registerDanylo Piliaiev1-1/+3
2021-03-29freedreno/a5xx: Add support for clip distances and use them for userclip.Eric Anholt1-3/+18
2021-03-22freedreno/a6xx: Rename the RB_BLIT_INFO.INTEGER field to SAMPLE_0.Eric Anholt1-1/+1
2021-03-11freedreno/a6xx: Cleanup SP_XS_CTRL_REG0 definitionsConnor Abbott1-27/+45
2021-03-11freedreno/registers: Handle typed registers with fieldsConnor Abbott1-2/+7
2021-03-10freedreno/a5xx: port handling of PIPE_BUFFER textures from a6xxDanylo Piliaiev1-0/+9
2021-02-19turnip,freedreno/a6xx: tell hw the size of shared mem used by CSDanylo Piliaiev1-10/+15
2021-02-19freedreno/a6xx: update some registersJonathan Marek1-129/+190
2021-02-19freedreno/a6xx: always use reg64 for address registers (no LO/HI)Jonathan Marek2-98/+30
2021-02-19freedreno/a6xx: update perfcntr registers (declare as arrays)Jonathan Marek1-378/+43
2021-02-19freedreno/registers: use macro instead of inline function for array regsJonathan Marek1-1/+1
2021-02-19freedreno/a6xx: Document threadsize-related fieldsConnor Abbott1-5/+22
2021-01-16freedreno/a2xx: add RB perfcounter 1-3Joel Linn1-0/+9
2021-01-16freedreno/a2xx: fix/add RBBM perfcounterJoel Linn1-3/+6
2020-12-21freedreno/a6xx: Fix SP_HS_UNKNOWN_A831 value and document itDanylo Piliaiev1-1/+7
2020-11-19freedreno/a6xx: Document private memory registersConnor Abbott1-7/+101
2020-11-03freedreno/a6xx: Update SO registers for streamsConnor Abbott1-13/+47
2020-10-06util: remove util_float_to_half and util_half_to_float wrappersMarek Olšák1-1/+1
2020-10-01Revert F16C series (MR 6774)Matt Turner1-1/+1
2020-09-30util: remove util_float_to_half and util_half_to_float wrappersMarek Olšák1-1/+1
2020-09-29freedreno/registers: Add a couple things used on kernel sideRob Clark2-1/+5
2020-09-09freedreno: Make the pack struct have a .qword for wide addresses.Eric Anholt1-3/+10
2020-09-04freedreno/regs: add 7nm DSI PHY/PLL regsJonathan Marek1-0/+222
2020-08-20freedreno/a6xx: Add multiview registersConnor Abbott2-9/+48
2020-08-19freedreno/registers: SC_WAIT_WC is not a6xxRob Clark1-1/+1
2020-08-13turnip: implement VK_EXT_custom_border_colorJonathan Marek1-1/+1
2020-08-07freedreno/registers: add some missing regs to buildRob Clark1-0/+4
2020-08-05freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.Eric Anholt1-1/+11
2020-08-04freedreno: Document draw predication packetsConnor Abbott1-4/+60
2020-08-03turnip: workaround for a630 d24_unorm_s8_uint failsJonathan Marek1-2/+2
2020-08-03freedreno/registers: install gzip'd register databaseRob Clark2-0/+24
2020-08-03freedreno/registers: split header build into subdirsRob Clark3-39/+73
2020-08-03freedreno/registers: add .gitignoreRob Clark1-0/+1
2020-07-31freedreno/a6xx: Fix CP_BIN_SIZE_ADDRESS nameConnor Abbott1-5/+17
2020-07-29freedreno/rnn: schema updates for dynamic/irregular offsetsRob Clark1-1/+4
2020-07-29freedreno/registers/mdp5: fix validation errorRob Clark1-0/+2
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