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path: root/src/freedreno/.gitlab-ci
AgeCommit message (Expand)AuthorFilesLines
2021-05-31freedreno/afuc: Use emulator to extract jmptblRob Clark1-0/+128
2021-05-31freedreno/ci: Add real packet-table loading for afuc testRob Clark3-1/+57
2021-05-31freedreno/afuc: Extract full gpu-idRob Clark1-1/+1
2021-05-31freedreno/registers: Add a few a6xx regs and notesRob Clark1-11/+11
2021-05-31freedreno/afuc: Add pipe reg name decodingRob Clark1-2/+2
2021-05-31freedreno/afuc: Clean up special regsRob Clark2-29/+29
2021-05-07freedreno/a5xx: SP_BLEND_CNTL has per-mrt blend enable bitDanylo Piliaiev3-6/+6
2021-04-01turnip: enable infinities for f16 math and document the registerDanylo Piliaiev3-7/+7
2021-03-11freedreno/a6xx: Cleanup SP_XS_CTRL_REG0 definitionsConnor Abbott3-28/+28
2021-03-09freedreno/hw: fix populating branch targets in isa_decode pre-passDanylo Piliaiev1-0/+3
2021-02-19turnip,freedreno/a6xx: tell hw the size of shared mem used by CSDanylo Piliaiev1-2/+2
2021-02-19freedreno/a6xx: update some registersJonathan Marek3-219/+219
2021-02-19freedreno/a6xx: always use reg64 for address registers (no LO/HI)Jonathan Marek3-366/+366
2021-02-19freedreno/a6xx: update perfcntr registers (declare as arrays)Jonathan Marek3-370/+370
2021-02-19freedreno/a6xx: Document threadsize-related fieldsConnor Abbott3-43/+43
2021-01-13freedreno/ir3/decode: Switch over to new disasmRob Clark4-1353/+79
2021-01-13freedreno/ir3: Realign disasm shader statsRob Clark1-71/+71
2021-01-13freedreno/ir3: Better sstall estimationRob Clark3-80/+80
2021-01-06freedreno/ir3: Fix mova1 disasmRob Clark1-6/+6
2021-01-06freedreno/ir3: Fix half-immed decoding issuesRob Clark1-1/+1
2021-01-06ir3: Support MOVMSKConnor Abbott1-1/+1
2020-12-21freedreno/a6xx: Fix SP_HS_UNKNOWN_A831 value and document itDanylo Piliaiev3-11/+11
2020-11-19freedreno/a6xx: Document private memory registersConnor Abbott3-81/+81
2020-11-19freedreno/ci: Strip location from assertsConnor Abbott2-4/+5
2020-11-03freedreno/a6xx: Update SO registers for streamsConnor Abbott3-31/+31
2020-09-29freedreno/registers: Add a couple things used on kernel sideRob Clark1-1/+1
2020-08-20freedreno/a6xx: Add multiview registersConnor Abbott3-62/+62
2020-08-19freedreno/ir3: Fix assertion failures dumping CS high full regs.Eric Anholt3-46/+1052
2020-08-18freedreno: Add afuc regression testConnor Abbott4-1/+535
2020-08-11freedreno/crashdec: handle section name typosRob Clark1-1/+1
2020-08-11freedreno/ir3: add more disasm statsRob Clark3-37/+74
2020-08-05freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.Eric Anholt3-15/+15
2020-07-31freedreno/a6xx: Fix CP_BIN_SIZE_ADDRESS nameConnor Abbott1-9/+9
2020-07-29freedreno: Add trace for CP_DRAW_INDIRECT_MULTIConnor Abbott3-0/+1672
2020-07-28freedreno/ci: add a2xx trace to CI jobRob Clark3-0/+7947
2020-07-28freedreno: deduplicate a3xx+ disasmRob Clark3-1144/+81
2020-07-28freedreno: add CI for envytools toolsRob Clark13-0/+42490
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