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2023-12-14i915G: show correct number of needed ALU instructions at errmessGKraats2-6/+4
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26340>
2023-10-26meson: Add gallium-drivers=all optionAlyssa Rosenzweig2-1/+10
Again, useful to lint common code changes and for our macbook-wielding rel manager <3 Omits i915g due to dependency hell, everything else builds on fedora asahi. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Cc: mesa-stable Reviewed-by: Eric Engestrom <eric@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25882>
2023-10-18glsl: Remove lower_discard().Emma Anholt5-210/+0
Replaced by the new NIR pass. i915g results: total instructions in shared programs: 510678 -> 510714 (<.01%) total temps in shared programs: 30429 -> 30426 (<.01%) rv370 results: total instructions in shared programs: 737649 -> 737656 (<.01%) instructions in affected programs: 82 -> 89 (8.54%) total temps in shared programs: 112093 -> 112094 (<.01%) temps in affected programs: 6 -> 7 (16.67%) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24763>
2023-10-18nir: Flatten ifs with discards in nir_opt_peephole_select for HW without CF.Emma Anholt1-3/+43
i915g and r300-r400 don't have if statements, and discards are all nir_intrinsic_discard_if. We can flatten those discards here, saving a separate GLSL pass to try to do so. i915g: GAINED: shaders/closed/xcom-enemy-unknown/413.shader_test FS rv370: GAINED: shaders/closed/xcom-enemy-unknown/12.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/122.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/132.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/145.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/146.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/19.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/413.shader_test FS GAINED: shaders/closed/xcom-enemy-unknown/415.shader_test FS Closes: #9918 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24763>
2023-02-28glsl/opt_algebraic: Drop fdot 0-channel optimizations.Emma Anholt1-35/+0
No change on i915g shader-db. Acked-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21475>
2023-01-26ci: Add manual rules variations to disable irrelevant driver jobs.Emma Anholt13-87/+234
If you're only affecting one or a couple of drivers, it would be nice if your pipeline buttons on the web UI weren't full of manual run buttons for all the other drivers. This is a bunch of duplicated lines, but less than it could have been now that we have !references. In some of these cases (i915g, nouveau, etnaviv), we have no non-manual jobs for those drivers, so I could have just rewritten the original "driver-rules" to "driver-manual-rules". I decided to keep things consistent between drivers, though, because this is all esoteric enough to readers already without making different drivers' rules look different. Fixes: #4891 Acked-by: David Heidelberg <david.heidelberg@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17445>
2022-11-23i915g: fix typo in #ifEric Engestrom1-2/+2
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19963>
2022-10-31i915g: Advertise PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENTAlyssa Rosenzweig1-0/+1
Currently buffer_map returns the raw pointer, there is no syncing or flushing or staging buffers or resource shadowing anywhere. That means if the driver is currently correct, it is implementing persistent and coherent behaviour already, so the CAP is trivial. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19392>
2022-10-29panfrost,asahi: Support ARB_buffer_storageAlyssa Rosenzweig4-1/+4
After a great deal of spec lawyering in #dri-devel, I am convinced this is probably okay for the same reasons as v3d and freedreno. The batch reordering and flush deferral optimizations are seemingly still ok. The requirement that writes are visible "immediately" in the spec actually means "in the subsequent [OpenGL] command" for the CPU -> GPU direction, which avoids pitfalls where PERSISTENT|COHERENT could be used as a "doorbell". With that understanding, the extension doesn't actually require anything special for tilers other than coherency at GPU submit boundaries, which is true for any driver that does not use a sync ioctl. After this commit, the remaining drivers that don't set the CAP are d3d12, softpipe, etnaviv, and i915g. I am unsure about d3d12, but the latter 3 could probbaly enable it trivially for the same reason. v2: Don't use copy_resource path for persistent mappings (Emma). Emma explained on GitLab: I don't think you should have the copy_resource path taken for PIPE_RESOURCE_FLAG_MAP_PERSISTENT BOs. Imagine the user has a general-purpose BO they're streaming stuff into and doing draws that they keep persistently mapped until wrapping. They call some GL function on the same buffer that does a fallback write map on the BO (u_default_buffer_subdata, util_resource_copy_region, whatever) -- the buffer is in use, copy triggers, allocates a new BO. Whoops, the user's pointer for streaming writes is now freed. Closes: #7570 Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19351>
2022-06-02i915g: Ignore the new SEPARABLE_PROGRAM property.Emma Anholt1-1/+3
We didn't need to know about it before, and we still don't. Fixes: b63403054237 ("tgsi: Add SEPARABLE_PROGRAM property") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16845>
2022-05-19nir/i915g/r300/nv30: skip marking varyings as flat in some driversTimothy Arceri5-1/+15
Some older drivers don't support GLSL versions with the concept of flat varyings and also don't support integers. Here we add a new setting to make sure we don't use the optimisation that sets varyings to flat. This setting helps us avoid marking varyings as flat and therefore potentially having them changed to ints via varying packing. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6500 Fixes: 7647023f3bb5 ("glsl: enable the use of the nir based varying linker") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16573>
2022-05-17i915g/ci: Add depth-clear-precision-check xfails like everyone else.Emma Anholt1-0/+6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
2022-05-17i915g: switch to NIR loop unrollingTimothy Arceri2-7/+2
Shader-db stats: total instructions in shared programs: 406749 -> 406890 (0.03%) instructions in affected programs: 216 -> 357 (65.28%) total tex_indirect in shared programs: 12666 -> 12671 (0.04%) tex_indirect in affected programs: 29 -> 34 (17.24%) total temps in shared programs: 23447 -> 23451 (0.02%) temps in affected programs: 296 -> 300 (1.35%) total const in shared programs: 59400 -> 59455 (0.09%) const in affected programs: 50 -> 105 (110.00%) LOST: 0 GAINED: 17 Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-05-17i915g: use a valid setting for force_indirect_unrollingTimothy Arceri1-1/+1
Otherwise we can hit asserts for example nir_deref_mode_must_be() asserts on !(modes & ~nir_var_all) Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
2022-03-04nir/opt_shrink_vectors: remove duplicate components from vecNDaniel Schürmann1-38/+65
vecN instructions which are only used by other ALU will now get duplicate channels removed. i915g: total instructions in shared programs: 396309 -> 396294 (<.01%) instructions in affected programs: 186 -> 171 (-8.06%) r300: total instructions in shared programs: 1165059 -> 1164354 (-0.06%) instructions in affected programs: 35884 -> 35179 (-1.96%) total temps in shared programs: 165497 -> 165326 (-0.10%) temps in affected programs: 2990 -> 2819 (-5.72%) softpipe: total instructions in shared programs: 2860028 -> 2859084 (-0.03%) instructions in affected programs: 55539 -> 54595 (-1.70%) total temps in shared programs: 516939 -> 516546 (-0.08%) temps in affected programs: 6623 -> 6230 (-5.93%) Acked-by: Emma Anholt <emma@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12468>
2022-03-04nir/opt_shrink_vectors: shrink load_const properlyDaniel Schürmann1-12/+74
This patch enables removal of arbitrary channels in load_const instructions, if they are either unused or duplicates of other channels and only used by ALU. Totals from 692 (0.51% of 134913) affected shaders: (GFX10.3) VGPRs: 21832 -> 21544 (-1.32%) CodeSize: 1322016 -> 1313080 (-0.68%); split: -0.68%, +0.01% Instrs: 243635 -> 242231 (-0.58%); split: -0.58%, +0.00% Latency: 1856138 -> 1857237 (+0.06%); split: -0.09%, +0.15% InvThroughput: 424298 -> 421671 (-0.62%); split: -0.62%, +0.01% VClause: 4580 -> 4583 (+0.07%); split: -0.02%, +0.09% SClause: 14336 -> 14354 (+0.13%); split: -0.04%, +0.17% Copies: 8897 -> 8859 (-0.43%); split: -0.45%, +0.02% PreSGPRs: 20439 -> 20437 (-0.01%) PreVGPRs: 16011 -> 15907 (-0.65%); split: -0.97%, +0.32% i915g: total instructions in shared programs: 396471 -> 396309 (-0.04%) instructions in affected programs: 6408 -> 6246 (-2.53%) total const in shared programs: 56458 -> 56422 (-0.06%) const in affected programs: 407 -> 371 (-8.85%) LOST: shaders/closed/steam/trine-2/fp-3.shader_test FS r300: total instructions in shared programs: 1164421 -> 1165059 (0.05%) instructions in affected programs: 143981 -> 144619 (0.44%) total temps in shared programs: 165488 -> 165497 (<.01%) temps in affected programs: 318 -> 327 (2.83%) total consts in shared programs: 922140 -> 921952 (-0.02%) consts in affected programs: 12438 -> 12250 (-1.51%) softpipe: total instructions in shared programs: 2859978 -> 2860028 (<.01%) instructions in affected programs: 183355 -> 183405 (0.03%) total temps in shared programs: 517071 -> 516939 (-0.03%) temps in affected programs: 1416 -> 1284 (-9.32%) total imm in shared programs: 103601 -> 102767 (-0.81%) imm in affected programs: 3928 -> 3094 (-21.23%) Acked-by: Emma Anholt <emma@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12468>
2022-03-03i915g: Emit better code for SEQ(x, 0) and SNE(x, 0)Ian Romanick1-18/+54
total instructions in shared programs: 789000 -> 788481 (-0.07%) instructions in affected programs: 16179 -> 15660 (-3.21%) helped: 157 HURT: 0 helped stats (abs) min: 3 max: 12 x̄: 3.31 x̃: 3 helped stats (rel) min: 1.56% max: 14.29% x̄: 4.24% x̃: 2.56% 95% mean confidence interval for instructions value: -3.51 -3.10 95% mean confidence interval for instructions %-change: -4.70% -3.78% Instructions are helped. LOST: 0 GAINED: 3 v2: Drop setting src1 to zero. Suggested by Emma. Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03i915g: Handle constants composed exclusively of 0 or ±1 speciallyIan Romanick2-2/+41
This can avoid some cases where a constant has to be loaded into a temporary register. v2: Update i915-g33-fails.txt. total instructions in shared programs: 788625 -> 782376 (-0.79%) instructions in affected programs: 166269 -> 160020 (-3.76%) helped: 1578 HURT: 0 helped stats (abs) min: 3 max: 21 x̄: 3.96 x̃: 3 helped stats (rel) min: 1.56% max: 33.33% x̄: 4.82% x̃: 3.45% 95% mean confidence interval for instructions value: -4.06 -3.86 95% mean confidence interval for instructions %-change: -5.00% -4.64% Instructions are helped. LOST: 0 GAINED: 35 Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03nir/algebraic: Optimize some cases of (sXX(a, b) != 0.0)Ian Romanick1-0/+17
I noticed the SGE case while looking at the output of shaders/closed/steam/trine-2/fp-3.shader_test on i915g. These are especially bad on i915 that needs two instructions to implement SNE. An alternative would be to duplicate the sne(sXX(a, b), 0.0) rules in an algebraic pass that occurs after bool_to_float. Doing the work earlier seems preferable. i915 total instructions in shared programs: 788274 -> 788223 (<.01%) instructions in affected programs: 666 -> 615 (-7.66%) helped: 5 HURT: 0 helped stats (abs) min: 9 max: 12 x̄: 10.20 x̃: 9 helped stats (rel) min: 5.00% max: 11.11% x̄: 8.12% x̃: 8.16% 95% mean confidence interval for instructions value: -12.24 -8.16 95% mean confidence interval for instructions %-change: -10.81% -5.43% Instructions are helped. LOST: 0 GAINED: 2 The two gained shaders are assembly fragment programs in Euro Truck Simulator 2. Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03i915g/ci: update piglit failsIan Romanick1-2/+0
I believe these were fixed by !14573. Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-02-25nir: Allow the _replicates opcodes to have num_components != 4.Emma Anholt2-7/+2
This required relaxing a core NIR assertion which I don't think is doing any important validation. The shader-db effects here are small, but they're important for avoiding a regression when we start doing per-component DCE in opt_shrink_vectors (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12468) softpipe shader-db: total instructions in shared programs: 2859777 -> 2859454 (-0.01%) instructions in affected programs: 18881 -> 18558 (-1.71%) total temps in shared programs: 293994 -> 293914 (-0.03%) temps in affected programs: 418 -> 338 (-19.14%) i915g: total instructions in shared programs: 407562 -> 407544 (<.01%) instructions in affected programs: 570 -> 552 (-3.16%) r300: total instructions in shared programs: 1414450 -> 1414459 (<.01%) instructions in affected programs: 44494 -> 44503 (0.02%) total vinst in shared programs: 473782 -> 473727 (-0.01%) vinst in affected programs: 1102 -> 1047 (-4.99%) total sinst in shared programs: 231224 -> 231216 (<.01%) sinst in affected programs: 432 -> 424 (-1.85%) total temps in shared programs: 197605 -> 197607 (<.01%) temps in affected programs: 103 -> 105 (1.94%) crocus hsw: total instructions in shared programs: 8158185 -> 8158134 (<.01%) instructions in affected programs: 10927 -> 10876 (-0.47%) Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15178>
2022-02-23iris,crocus,i915g: Don't stub flush_frontbufferAlyssa Rosenzweig3-37/+0
This callback is only intended for software rasterizers, layered drivers, and other special drivers that go through the software winsys path. Remove the unimplemented stubs from the Intel drivers. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Dave Airlie <airlied@redhat.com> [crocus] Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15118>
2022-02-15i915g: Initialize the rest of the "from_nir" temporary VS struct.Emma Anholt1-2/+1
draw looked at the uninitialized XFB state, which should just be zeroed out since i915 doesn't have XFB. Fixes: 2b3fc26da8be ("i915g: Switch to using nir-to-tgsi.") Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14896>
2022-02-10nir_to_tgsi: Replace the NIR SSA liveness with TGSI reg-level liveness.Emma Anholt3-79/+327
Allocating NIR registers ends up being required for drivers like r600 and nv30, which don't do their own allocation (except in some cases on r600 where sb is used). Rather than add a NIR register liveness impl (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14158), switch from NIR-based liveness to just doing the same channel-based liveness logic that the NIR registers needed at the TGSI level. The actual liveness code here basically comes straight out of brw_vec4_live_variables.cpp. Since we do the liveness in TGSI now, it also means we don't need to be careful about not reading SSA values from later TGSI instructions (which may be useful for doing some greedy instruction selection in generating TGSI instructions). i915g: total instructions in shared programs: 400719 -> 380730 (-4.99%) instructions in affected programs: 284760 -> 264771 (-7.02%) total tex_indirect in shared programs: 12289 -> 12290 (<.01%) tex_indirect in affected programs: 4 -> 5 (25.00%) total temps in shared programs: 32172 -> 22086 (-31.35%) temps in affected programs: 30647 -> 20561 (-32.91%) LOST: 0 GAINED: 148 r300: total instructions in shared programs: 1472463 -> 1459286 (-0.89%) instructions in affected programs: 507009 -> 493832 (-2.60%) total temps in shared programs: 212143 -> 201678 (-4.93%) temps in affected programs: 78007 -> 67542 (-13.42%) softpipe: total temps in shared programs: 517071 -> 294387 (-43.07%) temps in affected programs: 509324 -> 286640 (-43.72%) Acked-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>
2022-02-10i915g: Report the temps usageEmma Anholt1-2/+4
This is another important metric for this driver, and we don't do our own RA so ours is just what TGSI uses. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>
2022-02-08nir_to_tgsi: Add a flag for lowering fabs, and use it in r300/i915.Emma Anholt5-17/+34
Saves instructions if the same fabs value is used multiple times. i915g: total instructions in shared programs: 397005 -> 396525 (-0.12%) instructions in affected programs: 11061 -> 10581 (-4.34%) LOST: 0 GAINED: 22 r300 (not r500): total instructions in shared programs: 180286 -> 179767 (-0.29%) instructions in affected programs: 27102 -> 26583 (-1.91%) total temps in shared programs: 29692 -> 29638 (-0.18%) temps in affected programs: 356 -> 302 (-15.17%) Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>
2022-01-07i915g/ci: update piglit failsChristian Gmeiner1-3/+0
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14439>
2022-01-07nir_to_tgsi: Enable fdot_replicates flag.Emma Anholt5-0/+16
That's how the TGSI math opcodes work. This lets lower_vec_to_regs coalesce the DP output into the .yzw channels, giving an impressive shader-db win on softpipe: total instructions in shared programs: 2929840 -> 2794036 (-4.64%) instructions in affected programs: 1651438 -> 1515634 (-8.22%) total temps in shared programs: 372730 -> 332744 (-10.73%) temps in affected programs: 118151 -> 78165 (-33.84%) and a minor one on r300: total instructions in shared programs: 51238 -> 51149 (-0.17%) instructions in affected programs: 2621 -> 2532 (-3.40%) total vinst in shared programs: 15655 -> 15618 (-0.24%) vinst in affected programs: 468 -> 431 (-7.91%) total temps in shared programs: 9838 -> 9828 (-0.10%) temps in affected programs: 59 -> 49 (-16.95%) and a bigger one on i915g: total instructions in shared programs: 398064 -> 395901 (-0.54%) instructions in affected programs: 29271 -> 27108 (-7.39%) total tex_indirect in shared programs: 12261 -> 12233 (-0.23%) tex_indirect in affected programs: 98 -> 70 (-28.57%) LOST: 0 GAINED: 5 The r300 change is less impressive because it does some backend copy-prop, but also because intermediate storage of DPs now takes a vec4 instead of a scalar. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14200>
2022-01-05i915g: Turn off FP16 in the vertex shaders.Emma Anholt1-3/+6
This ended up being turned on in gallivm, but since we use nir_to_tgsi on the VS and TGSI doesn't have FP16, we can't let that happen. Fixes: f814a2449e2c ("llvmpipe: enable FP16 and update CL + traces piglit results.") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14403>
2021-12-29ci/i915g: Add a couple more recent regressions.Emma Anholt1-0/+4
The new frontfacing one is just different UB for the same lack of frontfacing support. And for RGB10_A2, we have another fail in that area already as well. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14300>
2021-12-29ci: Enable reporting to the flakes IRC channel for i915g and crocus.Emma Anholt2-0/+2
Acked-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14300>
2021-12-23i915g: avoid left shifting a negative numberThomas H.P. Andersen1-1/+1
Fixes a warning with clang Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14289>
2021-12-22i915g: fix implicit-fallthrough warningThomas H.P. Andersen1-0/+1
Fixes a warning on clang. Uses FALLTHROUGH like the surrounding code. Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14252>
2021-12-09loader: Restore i915g support.Emma Anholt1-0/+7
The cleanup of i915c cleaned up our PCI ID list. Fixes: 0cad451f007f ("classic/i915: Remove driver") Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14131>
2021-11-01i915g: Improve the explanation for the 1D Y swizzle.Emma Anholt1-4/+3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13133>
2021-11-01i915g: Make sure we consider negates/swizzles on bias/shadow coords.Emma Anholt4-69/+39
Caught by imirkin while debugging #4986. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13133>
2021-11-01i915g: Check for negate/swizzle on TGSI_OPCODE_KILL_IF's src.yzw.Emma Anholt1-1/+1
Caught by imirkin while debugging #4986. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13133>
2021-10-13ci: Update piglit to 7d7dd2688c214e1b3c00f37226500cbec4a58efb.Emma Anholt6-67/+12
This brings in a bunch of i915g spurious fail fixes, fixes for !12613, and new tests. Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13253>
2021-10-05i915g: Check for the scanout-layout conditions before setting level info.Emma Anholt1-3/+4
Fixes leaks (release) or assertion failures (debug) on allocating small scanout resources, when falling through to the non-scanout-specific layout code, which became more common as of ad50b47a14e9 ("gbm: assume USE_SCANOUT in create_with_modifiers"). Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13202>
2021-09-27i915g: Use the non-vbuf code path by default to fix index overflows.Emma Anholt6-53/+8
We were assertion failing on some large draws due to indices >16bits, despite asking draw to limit the max indices. I haven't managed to track it down, so flip us back to the older, non-index drawing path that doesn't hit this bug until it can get fixed. Leave an I915_DEBUG=vbuf flag around so we can look into this later. This is a pretty big performance hit for vertex shaders. Using glmark2 -b build:use-vbo=true: i915g-vbuf: 211 fps i915g-nonvbuf: 185 fps i915c: 41 fps Given how massively better i915g still is than i915c (llvmpipe VS instead of the classic swrast interpreter), I think it's still worth it to get i915g correct before we fix this perf regression. Fixes: #4971 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13052>
2021-09-27i915g: Unifdef VBUF_MAP_BUFFER.Emma Anholt1-40/+0
You do want to stream the vertices out to the WC mapping, as the code has been doing, rather than writing into malloc and doing a memcpy later and wasting cache space. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13052>
2021-09-27i915g: Remove dead VBUF_USE_POOL code.Emma Anholt1-15/+0
Not defined anywhere, and the members it's setting up don't exist. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13052>
2021-09-27i915g: Improve debug output for the fresh-batch overflow case.Emma Anholt2-0/+7
Much more useful info for dEQP-GLES2.functional.buffer.write.random.0 than "i915_vbuf_render_draw_elements: Assertion `0' failed." Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13052>
2021-09-22ci/vc4,i915g: Add links to VK-GL-CTS issues for some of our xfails.Emma Anholt2-16/+8
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12962>
2021-09-20ci/i915g: Clarify failure happening in fbo-fragcoord2.Emma Anholt1-2/+1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12917>
2021-09-06i915g: Reject non-unrolled loops or non-flattend IFs at link time.Emma Anholt3-385/+49
i915 has no support for control flow, so we need to link-fail shaders that fail to unrooll loops. This is valid for GLES2, and non-conformant but the best we can do for GL2. Note that we still have some dEQP failures where loops that should be unrollable and thus are required to be supported don't get unrolled (#4979). Closes: #4978 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12218>
2021-09-06mesa/st: Add an optional GLSL link fail msg to finalize_nir.Emma Anholt17-37/+69
GLES2 drivers are allowed to reject some GLSL constructs, like dynamic loop bounds (which neither i915g nor vc4 can fully support), but gallium hasn't had any way to trigger a link failure. Add a return msg to the finalize_nir hook, which is called at the end of GLSL linking, and use that. This means that some other callers of finalize need to do something with the msg, and we (for now) just throw it away. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12218>
2021-09-06i915g: Add finalize_nir.Emma Anholt1-0/+65
This allows mesa/st to do some more optimization of state variables, but more importantly it will be what we use to do GLSL link-time errors for loops. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12218>
2021-09-06i915g: Expose PIPE_CAP_TGSI_TEXCOORD.Emma Anholt5-1/+14
We want to be able to use finalize_nir, but doing so requires this flag to be set because not having it is incompatible with being able to finalize twice (since the texcoord workaround varyings shift happens at variant time rather than link time). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12218>
2021-09-06i915g: Simplify the process of texcoord mapping to TGSI semantics.Emma Anholt4-67/+37
Custom index-as-semantic defines and extra bool flags at state update time are unnecessary if we just store the semantics and index that each texcoord should be. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12218>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 15:19:43 +0000