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2019-06-04vl: Enable DRM by default.Bas Nieuwenhuizen3-4/+4
2019-06-04anv: Advertise support for VK_EXT_fragment_shader_interlockJason Ekstrand3-0/+12
2019-06-04spirv: Implement SPV_EXT_fragment_shader_interlockJason Ekstrand2-0/+38
2019-06-04spirv: Update the headers from latest Khronos masterJason Ekstrand2-3/+330
2019-06-04vulkan: Update the XML and headers to 1.1.110Jason Ekstrand2-23/+456
2019-06-04ac/nir: mark some texture intrinsics as convergentRhys Perry1-0/+18
2019-06-04radv: fix some compiler warningsRhys Perry1-4/+4
2019-06-04intel/fs: Skip registers faster when setting spill costsJason Ekstrand1-2/+10
2019-06-04radeonsi/nir: Fix type in bindless address computationConnor Abbott1-2/+2
2019-06-04etnaviv: implement set_active_query_state(..) for hw queriesChristian Gmeiner1-1/+10
2019-06-04radv: do not use gfx fast depth clears for layered depth/stencil imagesSamuel Pitoiset1-0/+1
2019-06-04ac,radv: do not emit vec3 for raw load/store on SISamuel Pitoiset4-8/+20
2019-06-03intel/compiler: Fix assertions in brw_alu3Sagar Ghuge1-3/+3
2019-06-03iris: Fix SO stride units for DrawTransformFeedbackKenneth Graunke2-2/+2
2019-06-04st/glsl: make sure to propagate initialisers to driver storageTimothy Arceri5-27/+23
2019-06-03spirv: Like Uniform, do nothing for UniformIdCaio Marcelo de Oliveira Filho2-0/+3
2019-06-03spirv: Implement SpvOpCopyLogicalCaio Marcelo de Oliveira Filho1-0/+2
2019-06-03spirv: Generalize OpSelectCaio Marcelo de Oliveira Filho1-38/+48
2019-06-03spirv: Move OpSelect handling to a functionCaio Marcelo de Oliveira Filho1-60/+66
2019-06-03nir/vars_to_ssa: Handle UNDEF_NODE in more placesCaio Marcelo de Oliveira Filho1-4/+8
2019-06-03ac/registers: don't use the si, cik, vi names, use gfxNMarek Olšák6-1405/+1405
2019-06-03amd/common: use generated register headerNicolai Hähnle26-16362/+26
2019-06-03amd/common: use SH{0,1}_CU_EN definitions only of COMPUTE_STATIC_THREAD_MGMT_SE0Nicolai Hähnle2-10/+10
2019-06-03amd/common: unify PITCH_GFX6 and PITCH_GFX9Nicolai Hähnle5-20/+20
2019-06-03amd/common: rename R_3F2_CONTROL to IB_CONTROL for disambiguationNicolai Hähnle2-2/+2
2019-06-03amd/common: cleanup DATA_FORMAT/NUM_FORMAT field namesNicolai Hähnle6-25/+25
2019-06-03amd/common: derive ac_debug tables from register JSONNicolai Hähnle4-177/+131
2019-06-03amd/registers: add JSON description of packet3 fieldsNicolai Hähnle1-0/+338
2019-06-03amd/registers: add JSON descriptions of registersNicolai Hähnle1-0/+15985
2019-06-03amd/registers: scripts for processing register descriptions in JSONNicolai Hähnle5-0/+1631
2019-06-03freedreno: Fix GCC build error.Vinson Lee1-1/+1
2019-06-03mesa: Use string literals for format stringsMark Janes1-3/+3
2019-06-03iris: Always reserve binding table space for NIR constantsCaio Marcelo de Oliveira Filho2-9/+14
2019-06-03iris: Print binding tables when INTEL_DEBUG=btCaio Marcelo de Oliveira Filho3-0/+55
2019-06-03iris: Compact binding tablesCaio Marcelo de Oliveira Filho3-76/+234
2019-06-03iris: Create an enum for the surface groupsCaio Marcelo de Oliveira Filho3-35/+45
2019-06-03iris: Handle binding table in the driverCaio Marcelo de Oliveira Filho6-121/+232
2019-06-03iris: Pull brw_nir_analyze_ubo_ranges() call out setup_uniformsCaio Marcelo de Oliveira Filho1-3/+10
2019-06-03spirv: Implement OpPtrEqual, OpPtrNotEqual and OpPtrDiffCaio Marcelo de Oliveira Filho1-0/+64
2019-06-03nir: Add functions to subtract and compare addressesCaio Marcelo de Oliveira Filho2-0/+54
2019-06-03nir: Add nir_ball_iequal() helperCaio Marcelo de Oliveira Filho1-0/+13
2019-06-03mesa: ARB program parser should clean parametersSergii Romantsov2-2/+13
2019-06-03freedreno/ir3: fix counting and printing for half registers.Hyunjun Ko4-9/+20
2019-06-03freedreno/ir3: Fix up the half reg source even when src instr==NULLNeil Roberts1-3/+2
2019-06-03freedreno/ir3: Add a 16-bit implementation of nir_op_imulNeil Roberts1-9/+15
2019-06-03freedreno/ir3: set dst type of alu instructions correctly.Hyunjun Ko1-5/+8
2019-06-03freedreno/ir3: adjust the bitsize of regs when an array loading.Hyunjun Ko2-7/+16
2019-06-03freedreno/ir3: convert back to 32-bit values for half constant registers.Hyunjun Ko2-4/+54
2019-06-03freedreno/ir3: check the type of regs of absneg opcode in is_same_type_mov.Hyunjun Ko1-0/+16
2019-06-03freedreno/ir3: set proper dst type for uniform according to the type of nir d...Hyunjun Ko2-7/+14
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