diff options
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
24 files changed, 1091 insertions, 963 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h index 71413716333..46e30b905a0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_bo_drm.h +++ b/src/mesa/drivers/dri/radeon/radeon_bo_drm.h @@ -39,6 +39,7 @@ #define RADEON_BO_FLAGS_MICRO_TILE 2 struct radeon_bo_manager; +struct radeon_cs; struct radeon_bo { uint32_t alignment; @@ -74,6 +75,7 @@ struct radeon_bo_funcs { int (*bo_get_tiling)(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch); int (*bo_is_busy)(struct radeon_bo *bo, uint32_t *domain); + int (*bo_is_referenced_by_cs)(struct radeon_bo *bo, struct radeon_cs *cs); }; struct radeon_bo_manager { @@ -199,6 +201,15 @@ static inline int radeon_bo_is_static(struct radeon_bo *bo) return 0; } +static inline int _radeon_bo_is_referenced_by_cs(struct radeon_bo *bo, + struct radeon_cs *cs, + const char *file, + const char *func, + unsigned line) +{ + return bo->cref > 1; +} + #define radeon_bo_open(bom, h, s, a, d, f)\ _radeon_bo_open(bom, h, s, a, d, f, __FILE__, __FUNCTION__, __LINE__) #define radeon_bo_ref(bo)\ @@ -215,5 +226,7 @@ static inline int radeon_bo_is_static(struct radeon_bo *bo) _radeon_bo_wait(bo, __FILE__, __func__, __LINE__) #define radeon_bo_is_busy(bo, domain) \ _radeon_bo_is_busy(bo, domain, __FILE__, __func__, __LINE__) +#define radeon_bo_is_referenced_by_cs(bo, cs) \ + _radeon_bo_is_referenced_by_cs(bo, cs, __FILE__, __FUNCTION__, __LINE__) #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c index 8fac5c6c512..99d3ec7005e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c +++ b/src/mesa/drivers/dri/radeon/radeon_buffer_objects.c @@ -136,8 +136,13 @@ radeonBufferSubData(GLcontext * ctx, const GLvoid * data, struct gl_buffer_object *obj) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_buffer_object *radeon_obj = get_radeon_buffer_object(obj); + if (radeon_bo_is_referenced_by_cs(radeon_obj->bo, radeon->cmdbuf.cs)) { + radeon_firevertices(radeon); + } + radeon_bo_map(radeon_obj->bo, GL_TRUE); _mesa_memcpy(radeon_obj->bo->ptr + offset, data, size); diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index 097ab7cf613..3b4366aa61c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -257,7 +257,9 @@ void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) radeonContextPtr radeon = RADEON_CONTEXT(ctx); if (ctx->Scissor.Enabled) { /* We don't pipeline cliprect changes */ - radeon_firevertices(radeon); + if (!radeon->radeonScreen->kernel_mm) { + radeon_firevertices(radeon); + } radeonUpdateScissor(ctx); } } @@ -1123,8 +1125,6 @@ void radeonFlush(GLcontext *ctx) if (radeon->dma.flush) radeon->dma.flush( ctx ); - radeonEmitState(radeon); - if (radeon->cmdbuf.cs->cdw) rcommonFlushCmdBuf(radeon, __FUNCTION__); @@ -1147,9 +1147,6 @@ void radeonFlush(GLcontext *ctx) } } } - - make_empty_list(&radeon->query.not_flushed_head); - } /* Make sure all commands have been sent to the hardware and have diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index f3201911ac6..def0cc17a91 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -43,7 +43,7 @@ void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, struct radeon_bo *bo); struct radeon_renderbuffer * -radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv); +radeon_create_renderbuffer(gl_format format, __DRIdrawablePrivate *driDrawPriv); static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) { struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 6b9b1e3c5e4..71f70d724b9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -262,10 +262,9 @@ GLboolean radeonInitContext(radeonContextPtr radeon, else radeon->texture_row_align = 32; radeon->texture_rect_row_align = 64; - radeon->texture_compressed_row_align = 64; + radeon->texture_compressed_row_align = 32; } - make_empty_list(&radeon->query.not_flushed_head); radeon_init_dma(radeon); return GL_TRUE; @@ -496,19 +495,7 @@ radeon_make_renderbuffer_current(radeonContextPtr radeon, static unsigned radeon_bits_per_pixel(const struct radeon_renderbuffer *rb) { - switch (rb->base._ActualFormat) { - case GL_RGB5: - case GL_DEPTH_COMPONENT16: - return 16; - case GL_RGB8: - case GL_RGBA8: - case GL_DEPTH_COMPONENT24: - case GL_DEPTH24_STENCIL8_EXT: - case GL_STENCIL_INDEX8_EXT: - return 32; - default: - return 0; - } + return _mesa_get_format_bytes(rb->base.Format) * 8; } void diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 0309345393d..ad953ddbb5a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -208,6 +208,10 @@ struct radeon_tex_obj { * and so on. */ GLboolean validated; + /* Minimum LOD to be used during rendering */ + unsigned minLod; + /* Miximum LOD to be used during rendering */ + unsigned maxLod; GLuint override_offset; GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ @@ -324,6 +328,7 @@ struct radeon_swtcl_info { GLuint vertex_attr_count; GLuint emit_prediction; + struct radeon_bo *bo; }; #define RADEON_MAX_AOS_ARRAYS 16 @@ -502,7 +507,6 @@ struct radeon_context { struct { struct radeon_query_object *current; - struct radeon_query_object not_flushed_head; struct radeon_state_atom queryobj; } query; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 8f4485aee7c..5e700be4a59 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -69,7 +69,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define need_GL_EXT_fog_coord #define need_GL_EXT_secondary_color #define need_GL_EXT_framebuffer_object -#include "extension_helper.h" +#include "main/remap_helper.h" #define DRIVER_DATE "20061018" @@ -79,7 +79,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Extension strings exported by the R100 driver. */ -const struct dri_extension card_extensions[] = +static const struct dri_extension card_extensions[] = { { "GL_ARB_multitexture", NULL }, { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions}, @@ -109,7 +109,7 @@ const struct dri_extension card_extensions[] = { NULL, NULL } }; -const struct dri_extension mm_extensions[] = { +static const struct dri_extension mm_extensions[] = { { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { NULL, NULL } }; diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c index c6edbae9a1b..b8c65f4ce62 100644 --- a/src/mesa/drivers/dri/radeon/radeon_dma.c +++ b/src/mesa/drivers/dri/radeon/radeon_dma.c @@ -151,6 +151,7 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, aos->components = size; aos->count = count; + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: radeonEmitVec4(out, data, stride, count); break; @@ -161,6 +162,7 @@ void rcommon_emit_vector(GLcontext * ctx, struct radeon_aos *aos, assert(0); break; } + radeon_bo_unmap(aos->bo); } void radeon_init_dma(radeonContextPtr rmesa) @@ -183,10 +185,6 @@ void radeonRefillCurrentDmaRegion(radeonContextPtr rmesa, int size) __FUNCTION__, size, rmesa->dma.minimum_size); - /* unmap old reserved bo */ - if (!is_empty_list(&rmesa->dma.reserved)) - radeon_bo_unmap(first_elem(&rmesa->dma.reserved)->bo); - if (is_empty_list(&rmesa->dma.free) || last_elem(&rmesa->dma.free)->bo->size < size) { dma_bo = CALLOC_STRUCT(radeon_dma_bo); @@ -207,6 +205,7 @@ again_alloc: counter on unused buffers for later freeing them from begin of list */ dma_bo = last_elem(&rmesa->dma.free); + assert(dma_bo->bo->cref == 1); remove_from_list(dma_bo); insert_at_head(&rmesa->dma.reserved, dma_bo); } @@ -223,8 +222,6 @@ again_alloc: /* Cmd buff have been flushed in radeon_revalidate_bos */ goto again_alloc; } - - radeon_bo_map(first_elem(&rmesa->dma.reserved)->bo, 1); } /* Allocates a region from rmesa->dma.current. If there isn't enough @@ -281,7 +278,6 @@ void radeonFreeDmaRegions(radeonContextPtr rmesa) foreach_s(dma_bo, temp, &rmesa->dma.reserved) { remove_from_list(dma_bo); - radeon_bo_unmap(dma_bo->bo); radeon_bo_unref(dma_bo->bo); FREE(dma_bo); } @@ -306,10 +302,6 @@ static int radeon_bo_is_idle(struct radeon_bo* bo) WARN_ONCE("Your libdrm or kernel doesn't have support for busy query.\n" "This may cause small performance drop for you.\n"); } - /* Protect against bug in legacy bo handling that causes bos stay - * referenced even after they should be freed */ - if (bo->cref != 1) - return 0; return ret != -EBUSY; } @@ -346,9 +338,7 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa) foreach_s(dma_bo, temp, &rmesa->dma.wait) { if (dma_bo->expire_counter == time) { WARN_ONCE("Leaking dma buffer object!\n"); - /* force free of buffer so we don't realy start - * leaking stuff now*/ - while ((dma_bo->bo = radeon_bo_unref(dma_bo->bo))) {} + radeon_bo_unref(dma_bo->bo); remove_from_list(dma_bo); FREE(dma_bo); continue; @@ -367,9 +357,6 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa) insert_at_tail(&rmesa->dma.free, dma_bo); } - /* unmap the last dma region */ - if (!is_empty_list(&rmesa->dma.reserved)) - radeon_bo_unmap(first_elem(&rmesa->dma.reserved)->bo); /* move reserved to wait list */ foreach_s(dma_bo, temp, &rmesa->dma.reserved) { /* free objects that are too small to be used because of large request */ @@ -403,11 +390,12 @@ void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); struct radeon_dma *dma = &rmesa->dma; - if (RADEON_DEBUG & RADEON_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); dma->flush = NULL; + radeon_bo_unmap(rmesa->swtcl.bo); + if (!is_empty_list(&dma->reserved)) { GLuint current_offset = dma->current_used; @@ -422,6 +410,8 @@ void rcommon_flush_last_swtcl_prim( GLcontext *ctx ) } rmesa->swtcl.numverts = 0; } + radeon_bo_unref(rmesa->swtcl.bo); + rmesa->swtcl.bo = NULL; } /* Alloc space in the current dma region. */ @@ -432,6 +422,7 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) void *head; if (RADEON_DEBUG & RADEON_IOCTL) fprintf(stderr, "%s\n", __FUNCTION__); + if(is_empty_list(&rmesa->dma.reserved) ||rmesa->dma.current_vertexptr + bytes > first_elem(&rmesa->dma.reserved)->bo->size) { if (rmesa->dma.flush) { @@ -455,7 +446,13 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize ) rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == rmesa->dma.current_vertexptr ); - head = (first_elem(&rmesa->dma.reserved)->bo->ptr + rmesa->dma.current_vertexptr); + if (!rmesa->swtcl.bo) { + rmesa->swtcl.bo = first_elem(&rmesa->dma.reserved)->bo; + radeon_bo_ref(rmesa->swtcl.bo); + radeon_bo_map(rmesa->swtcl.bo, 1); + } + + head = (rmesa->swtcl.bo->ptr + rmesa->dma.current_vertexptr); rmesa->dma.current_vertexptr += bytes; rmesa->swtcl.numverts += nverts; return head; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 0ae906a6cea..7ec641ff18a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -33,7 +33,6 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/context.h" -#include "main/texformat.h" #include "main/texrender.h" #include "drivers/common/meta.h" @@ -91,11 +90,8 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_R3_G3_B2: case GL_RGB4: case GL_RGB5: - rb->_ActualFormat = GL_RGB5; + rb->Format = _dri_texformat_rgb565; rb->DataType = GL_UNSIGNED_BYTE; - rb->RedBits = 5; - rb->GreenBits = 6; - rb->BlueBits = 5; cpp = 2; break; case GL_RGB: @@ -103,12 +99,8 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB10: case GL_RGB12: case GL_RGB16: - rb->_ActualFormat = GL_RGB8; + rb->Format = _dri_texformat_argb8888; rb->DataType = GL_UNSIGNED_BYTE; - rb->RedBits = 8; - rb->GreenBits = 8; - rb->BlueBits = 8; - rb->AlphaBits = 0; cpp = 4; break; case GL_RGBA: @@ -119,12 +111,8 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - rb->_ActualFormat = GL_RGBA8; + rb->Format = _dri_texformat_argb8888; rb->DataType = GL_UNSIGNED_BYTE; - rb->RedBits = 8; - rb->GreenBits = 8; - rb->BlueBits = 8; - rb->AlphaBits = 8; cpp = 4; break; case GL_STENCIL_INDEX: @@ -133,39 +121,36 @@ radeon_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_STENCIL_INDEX8_EXT: case GL_STENCIL_INDEX16_EXT: /* alloc a depth+stencil buffer */ - rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; - rb->StencilBits = 8; cpp = 4; break; case GL_DEPTH_COMPONENT16: - rb->_ActualFormat = GL_DEPTH_COMPONENT16; + rb->Format = MESA_FORMAT_Z16; rb->DataType = GL_UNSIGNED_SHORT; - rb->DepthBits = 16; cpp = 2; break; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: - rb->_ActualFormat = GL_DEPTH_COMPONENT24; + rb->Format = MESA_FORMAT_X8_Z24; rb->DataType = GL_UNSIGNED_INT; - rb->DepthBits = 24; cpp = 4; break; case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT; + rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; - rb->DepthBits = 24; - rb->StencilBits = 8; cpp = 4; break; default: _mesa_problem(ctx, - "Unexpected format in intel_alloc_renderbuffer_storage"); + "Unexpected format in radeon_alloc_renderbuffer_storage"); return GL_FALSE; } + rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat); + if (ctx->Driver.Flush) ctx->Driver.Flush(ctx); /* +r6/r7 */ @@ -213,7 +198,7 @@ radeon_alloc_window_storage(GLcontext * ctx, struct gl_renderbuffer *rb, ASSERT(rb->Name == 0); rb->Width = width; rb->Height = height; - rb->_ActualFormat = internalFormat; + rb->InternalFormat = internalFormat; return GL_TRUE; } @@ -255,8 +240,13 @@ radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb, return GL_FALSE; } + +/** + * Create a renderbuffer for a window's color, depth and/or stencil buffer. + * Not used for user-created renderbuffers. + */ struct radeon_renderbuffer * -radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) +radeon_create_renderbuffer(gl_format format, __DRIdrawablePrivate *driDrawPriv) { struct radeon_renderbuffer *rrb; @@ -267,67 +257,64 @@ radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) _mesa_init_renderbuffer(&rrb->base, 0); rrb->base.ClassID = RADEON_RB_CLASS; - /* XXX format junk */ + rrb->base.Format = format; + switch (format) { - case GL_RGB5: - rrb->base._ActualFormat = GL_RGB5; - rrb->base._BaseFormat = GL_RGBA; - rrb->base.RedBits = 5; - rrb->base.GreenBits = 6; - rrb->base.BlueBits = 5; + case MESA_FORMAT_RGB565: + assert(_mesa_little_endian()); + rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_RGB; + break; + case MESA_FORMAT_RGB565_REV: + assert(!_mesa_little_endian()); + rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_RGB; + break; + case MESA_FORMAT_XRGB8888: + assert(_mesa_little_endian()); + rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_RGB; + break; + case MESA_FORMAT_XRGB8888_REV: + assert(!_mesa_little_endian()); rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_RGB; break; - case GL_RGB8: - rrb->base._ActualFormat = GL_RGB8; - rrb->base._BaseFormat = GL_RGB; - rrb->base.RedBits = 8; - rrb->base.GreenBits = 8; - rrb->base.BlueBits = 8; - rrb->base.AlphaBits = 0; + case MESA_FORMAT_ARGB8888: + assert(_mesa_little_endian()); rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_RGBA; break; - case GL_RGBA8: - rrb->base._ActualFormat = GL_RGBA8; - rrb->base._BaseFormat = GL_RGBA; - rrb->base.RedBits = 8; - rrb->base.GreenBits = 8; - rrb->base.BlueBits = 8; - rrb->base.AlphaBits = 8; + case MESA_FORMAT_ARGB8888_REV: + assert(!_mesa_little_endian()); rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_RGBA; break; - case GL_STENCIL_INDEX8_EXT: - rrb->base._ActualFormat = GL_STENCIL_INDEX8_EXT; - rrb->base._BaseFormat = GL_STENCIL_INDEX; - rrb->base.StencilBits = 8; + case MESA_FORMAT_S8: rrb->base.DataType = GL_UNSIGNED_BYTE; + rrb->base._BaseFormat = GL_STENCIL_INDEX; break; - case GL_DEPTH_COMPONENT16: - rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; - rrb->base._BaseFormat = GL_DEPTH_COMPONENT; - rrb->base.DepthBits = 16; + case MESA_FORMAT_Z16: rrb->base.DataType = GL_UNSIGNED_SHORT; + rrb->base._BaseFormat = GL_DEPTH_COMPONENT; break; - case GL_DEPTH_COMPONENT24: - rrb->base._ActualFormat = GL_DEPTH_COMPONENT24; - rrb->base._BaseFormat = GL_DEPTH_COMPONENT; - rrb->base.DepthBits = 24; + case MESA_FORMAT_X8_Z24: rrb->base.DataType = GL_UNSIGNED_INT; + rrb->base._BaseFormat = GL_DEPTH_COMPONENT; break; - case GL_DEPTH24_STENCIL8_EXT: - rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; - rrb->base.DepthBits = 24; - rrb->base.StencilBits = 8; + case MESA_FORMAT_S8_Z24: rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; + rrb->base._BaseFormat = GL_DEPTH_STENCIL; break; default: - fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); + fprintf(stderr, "%s: Unknown format %s\n", + __FUNCTION__, _mesa_get_format_name(format)); _mesa_delete_renderbuffer(&rrb->base); return NULL; } rrb->dPriv = driDrawPriv; - rrb->base.InternalFormat = format; + rrb->base.InternalFormat = _mesa_get_format_base_format(format); rrb->base.Delete = radeon_delete_renderbuffer; rrb->base.AllocStorage = radeon_alloc_window_storage; @@ -387,46 +374,30 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, struct gl_texture_image *texImage) { int retry = 0; + gl_format texFormat; + restart: - if (texImage->TexFormat == &_mesa_texformat_argb8888) { - rrb->cpp = 4; - rrb->base._ActualFormat = GL_RGBA8; - rrb->base._BaseFormat = GL_RGBA; + if (texImage->TexFormat == _dri_texformat_argb8888) { rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_rgb565) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_RGB5; - rrb->base._BaseFormat = GL_RGB; + else if (texImage->TexFormat == _dri_texformat_rgb565) { rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb1555) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_RGB5_A1; - rrb->base._BaseFormat = GL_RGBA; + else if (texImage->TexFormat == _dri_texformat_argb1555) { rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb4444) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_RGBA4; - rrb->base._BaseFormat = GL_RGBA; + else if (texImage->TexFormat == _dri_texformat_argb4444) { rrb->base.DataType = GL_UNSIGNED_BYTE; - DBG("Render to ARGB1555 texture OK\n"); + DBG("Render to ARGB4444 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_z16) { - rrb->cpp = 2; - rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; - rrb->base._BaseFormat = GL_DEPTH_COMPONENT; + else if (texImage->TexFormat == MESA_FORMAT_Z16) { rrb->base.DataType = GL_UNSIGNED_SHORT; DBG("Render to DEPTH16 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { - rrb->cpp = 4; - rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; - rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; + else if (texImage->TexFormat == MESA_FORMAT_S8_Z24) { rrb->base.DataType = GL_UNSIGNED_INT_24_8_EXT; DBG("Render to DEPTH_STENCIL texture OK\n"); } @@ -434,26 +405,31 @@ restart: /* try redoing the FBO */ if (retry == 1) { DBG("Render to texture BAD FORMAT %d\n", - texImage->TexFormat->MesaFormat); + texImage->TexFormat); return GL_FALSE; } + /* XXX why is the tex format being set here? + * I think this can be removed. + */ texImage->TexFormat = radeonChooseTextureFormat(ctx, texImage->InternalFormat, 0, - texImage->TexFormat->DataType, + _mesa_get_format_datatype(texImage->TexFormat), 1); retry++; goto restart; } - rrb->base.InternalFormat = rrb->base._ActualFormat; + texFormat = texImage->TexFormat; + + rrb->base.Format = texFormat; + + rrb->cpp = _mesa_get_format_bytes(texFormat); + rrb->pitch = texImage->Width * rrb->cpp; + rrb->base.InternalFormat = texImage->InternalFormat; + rrb->base._BaseFormat = _mesa_base_fbo_format(ctx, rrb->base.InternalFormat); + rrb->base.Width = texImage->Width; rrb->base.Height = texImage->Height; - rrb->base.RedBits = texImage->TexFormat->RedBits; - rrb->base.GreenBits = texImage->TexFormat->GreenBits; - rrb->base.BlueBits = texImage->TexFormat->BlueBits; - rrb->base.AlphaBits = texImage->TexFormat->AlphaBits; - rrb->base.DepthBits = texImage->TexFormat->DepthBits; - rrb->base.StencilBits = texImage->TexFormat->StencilBits; rrb->base.Delete = radeon_delete_renderbuffer; rrb->base.AllocStorage = radeon_nop_alloc_storage; diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index 02de8e5fd1d..7ad781ba619 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -62,8 +62,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) __DRIdrawablePrivate *const readable = radeon_get_readable(rmesa); __DRIscreenPrivate *sPriv = rmesa->dri.screen; - assert(drawable != NULL); - drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); /* The window might have moved, so we might need to get new clip @@ -74,12 +72,13 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) * Since the hardware state depends on having the latest drawable * clip rects, all state checking must be done _after_ this call. */ - DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); - if (drawable != readable) { + if (drawable) + DRI_VALIDATE_DRAWABLE_INFO(sPriv, drawable); + if (readable && drawable != readable) { DRI_VALIDATE_DRAWABLE_INFO(sPriv, readable); } - if (rmesa->lastStamp != drawable->lastStamp) { + if (drawable && (rmesa->lastStamp != drawable->lastStamp)) { radeon_window_moved(rmesa); rmesa->lastStamp = drawable->lastStamp; } diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c index 08e1c5d00df..d810e6080eb 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c @@ -76,12 +76,14 @@ static void emit_vecfog(GLcontext *ctx, struct radeon_aos *aos, /* Emit the data */ + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); for (i = 0; i < count; i++) { out[0] = radeonComputeFogBlendFactor( ctx, *(GLfloat *)data ); out++; data += stride; } + radeon_bo_unmap(aos->bo); } static void emit_s0_vec(uint32_t *out, GLvoid *data, int stride, int count) @@ -151,6 +153,7 @@ static void emit_tex_vector(GLcontext *ctx, struct radeon_aos *aos, /* Emit the data */ + radeon_bo_map(aos->bo, 1); out = (uint32_t*)((char*)aos->bo->ptr + aos->offset); switch (size) { case 1: @@ -170,6 +173,7 @@ static void emit_tex_vector(GLcontext *ctx, struct radeon_aos *aos, exit(1); break; } + radeon_bo_unmap(aos->bo); } @@ -196,12 +200,12 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.obj.buf) rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), - (char *)VB->ObjPtr->data, - VB->ObjPtr->size, - VB->ObjPtr->stride, + (char *)VB->AttribPtr[_TNL_ATTRIB_POS]->data, + VB->AttribPtr[_TNL_ATTRIB_POS]->size, + VB->AttribPtr[_TNL_ATTRIB_POS]->stride, count); - switch( VB->ObjPtr->size ) { + switch( VB->AttribPtr[_TNL_ATTRIB_POS]->size ) { case 4: vfmt |= RADEON_CP_VC_FRMT_W0; case 3: vfmt |= RADEON_CP_VC_FRMT_Z; case 2: vfmt |= RADEON_CP_VC_FRMT_XY; @@ -216,9 +220,9 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.norm.buf) rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), - (char *)VB->NormalPtr->data, + (char *)VB->AttribPtr[_TNL_ATTRIB_NORMAL]->data, 3, - VB->NormalPtr->stride, + VB->AttribPtr[_TNL_ATTRIB_NORMAL]->stride, count); vfmt |= RADEON_CP_VC_FRMT_N0; @@ -227,9 +231,9 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (inputs & VERT_BIT_COLOR0) { int emitsize; - if (VB->ColorPtr[0]->size == 4 && - (VB->ColorPtr[0]->stride != 0 || - VB->ColorPtr[0]->data[0][3] != 1.0)) { + if (VB->AttribPtr[_TNL_ATTRIB_COLOR0]->size == 4 && + (VB->AttribPtr[_TNL_ATTRIB_COLOR0]->stride != 0 || + VB->AttribPtr[_TNL_ATTRIB_COLOR0]->data[0][3] != 1.0)) { vfmt |= RADEON_CP_VC_FRMT_FPCOLOR | RADEON_CP_VC_FRMT_FPALPHA; emitsize = 4; } @@ -242,9 +246,9 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.rgba.buf) rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), - (char *)VB->ColorPtr[0]->data, + (char *)VB->AttribPtr[_TNL_ATTRIB_COLOR0]->data, emitsize, - VB->ColorPtr[0]->stride, + VB->AttribPtr[_TNL_ATTRIB_COLOR0]->stride, count); nr++; @@ -256,9 +260,9 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) rcommon_emit_vector( ctx, &(rmesa->tcl.aos[nr]), - (char *)VB->SecondaryColorPtr[0]->data, + (char *)VB->AttribPtr[_TNL_ATTRIB_COLOR1]->data, 3, - VB->SecondaryColorPtr[0]->stride, + VB->AttribPtr[_TNL_ATTRIB_COLOR1]->stride, count); } @@ -273,8 +277,8 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.fog.buf) emit_vecfog( ctx, &(rmesa->tcl.aos[nr]), - (char *)VB->FogCoordPtr->data, - VB->FogCoordPtr->stride, + (char *)VB->AttribPtr[_TNL_ATTRIB_FOG]->data, + VB->AttribPtr[_TNL_ATTRIB_FOG]->stride, count); vfmt |= RADEON_CP_VC_FRMT_FPFOG; @@ -290,24 +294,24 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (!rmesa->tcl.tex[unit].buf) emit_tex_vector( ctx, &(rmesa->tcl.aos[nr]), - (char *)VB->TexCoordPtr[unit]->data, - VB->TexCoordPtr[unit]->size, - VB->TexCoordPtr[unit]->stride, + (char *)VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->data, + VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size, + VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->stride, count ); nr++; vfmt |= RADEON_ST_BIT(unit); /* assume we need the 3rd coord if texgen is active for r/q OR at least 3 coords are submitted. This may not be 100% correct */ - if (VB->TexCoordPtr[unit]->size >= 3) { + if (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) { vtx |= RADEON_Q_BIT(unit); vfmt |= RADEON_Q_BIT(unit); } if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) vtx |= RADEON_Q_BIT(unit); - else if ((VB->TexCoordPtr[unit]->size >= 3) && + else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) && ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) { - GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3); + GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3); if (((rmesa->NeedTexMatrix >> unit) & 1) && (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h b/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h index 515783135d6..d764ccb9826 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h +++ b/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h @@ -56,18 +56,18 @@ static void TAG(emit)( GLcontext *ctx, radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __FUNCTION__); - coord = (GLuint (*)[4])VB->ObjPtr->data; - coord_stride = VB->ObjPtr->stride; + coord = (GLuint (*)[4])VB->AttribPtr[_TNL_ATTRIB_POS]->data; + coord_stride = VB->AttribPtr[_TNL_ATTRIB_POS]->stride; if (DO_TEX2) { - if (VB->TexCoordPtr[2]) { + if (VB->AttribPtr[_TNL_ATTRIB_TEX2]) { const GLuint t2 = GET_TEXSOURCE(2); - tc2 = (GLuint (*)[4])VB->TexCoordPtr[t2]->data; - tc2_stride = VB->TexCoordPtr[t2]->stride; - if (DO_PTEX && VB->TexCoordPtr[t2]->size < 3) { + tc2 = (GLuint (*)[4])VB->AttribPtr[_TNL_ATTRIB_TEX0 + t2]->data; + tc2_stride = VB->AttribPtr[_TNL_ATTRIB_TEX0 + t2]->stride; + if (DO_PTEX && VB->AttribPtr[_TNL_ATTRIB_TEX0 + t2]->size < 3) { fill_tex |= (1<<2); } - else if (DO_PTEX && VB->TexCoordPtr[t2]->size < 4) { + else if (DO_PTEX && VB->AttribPtr[_TNL_ATTRIB_TEX0 + t2]->size < 4) { rqcoordsnoswap |= (1<<2); } } else { @@ -77,14 +77,14 @@ static void TAG(emit)( GLcontext *ctx, } if (DO_TEX1) { - if (VB->TexCoordPtr[1]) { + if (VB->AttribPtr[_TNL_ATTRIB_TEX1]) { const GLuint t1 = GET_TEXSOURCE(1); - tc1 = (GLuint (*)[4])VB->TexCoordPtr[t1]->data; - tc1_stride = VB->TexCoordPtr[t1]->stride; - if (DO_PTEX && VB->TexCoordPtr[t1]->size < 3) { + tc1 = (GLuint (*)[4])VB->AttribPtr[_TNL_ATTRIB_TEX0 + t1]->data; + tc1_stride = VB->AttribPtr[_TNL_ATTRIB_TEX0 + t1]->stride; + if (DO_PTEX && VB->AttribPtr[_TNL_ATTRIB_TEX0 + t1]->size < 3) { fill_tex |= (1<<1); } - else if (DO_PTEX && VB->TexCoordPtr[t1]->size < 4) { + else if (DO_PTEX && VB->AttribPtr[_TNL_ATTRIB_TEX0 + t1]->size < 4) { rqcoordsnoswap |= (1<<1); } } else { @@ -94,14 +94,14 @@ static void TAG(emit)( GLcontext *ctx, } if (DO_TEX0) { - if (VB->TexCoordPtr[0]) { + if (VB->AttribPtr[_TNL_ATTRIB_TEX0]) { const GLuint t0 = GET_TEXSOURCE(0); - tc0_stride = VB->TexCoordPtr[t0]->stride; - tc0 = (GLuint (*)[4])VB->TexCoordPtr[t0]->data; - if (DO_PTEX && VB->TexCoordPtr[t0]->size < 3) { + tc0_stride = VB->AttribPtr[_TNL_ATTRIB_TEX0 + t0]->stride; + tc0 = (GLuint (*)[4])VB->AttribPtr[_TNL_ATTRIB_TEX0 + t0]->data; + if (DO_PTEX && VB->AttribPtr[_TNL_ATTRIB_TEX0 + t0]->size < 3) { fill_tex |= (1<<0); } - else if (DO_PTEX && VB->TexCoordPtr[t0]->size < 4) { + else if (DO_PTEX && VB->AttribPtr[_TNL_ATTRIB_TEX0 + t0]->size < 4) { rqcoordsnoswap |= (1<<0); } } else { @@ -112,9 +112,9 @@ static void TAG(emit)( GLcontext *ctx, } if (DO_NORM) { - if (VB->NormalPtr) { - norm_stride = VB->NormalPtr->stride; - norm = (GLuint (*)[4])VB->NormalPtr->data; + if (VB->AttribPtr[_TNL_ATTRIB_NORMAL]) { + norm_stride = VB->AttribPtr[_TNL_ATTRIB_NORMAL]->stride; + norm = (GLuint (*)[4])VB->AttribPtr[_TNL_ATTRIB_NORMAL]->data; } else { norm_stride = 0; norm = (GLuint (*)[4])&ctx->Current.Attrib[VERT_ATTRIB_NORMAL]; @@ -122,9 +122,9 @@ static void TAG(emit)( GLcontext *ctx, } if (DO_RGBA) { - if (VB->ColorPtr[0]) { - col = VB->ColorPtr[0]->data; - col_stride = VB->ColorPtr[0]->stride; + if (VB->AttribPtr[_TNL_ATTRIB_COLOR0]) { + col = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->data; + col_stride = VB->AttribPtr[_TNL_ATTRIB_COLOR0]->stride; } else { col = (GLfloat (*)[4])ctx->Current.Attrib[VERT_ATTRIB_COLOR0]; col_stride = 0; @@ -132,9 +132,9 @@ static void TAG(emit)( GLcontext *ctx, } if (DO_SPEC_OR_FOG) { - if (VB->SecondaryColorPtr[0]) { - spec = VB->SecondaryColorPtr[0]->data; - spec_stride = VB->SecondaryColorPtr[0]->stride; + if (VB->AttribPtr[_TNL_ATTRIB_COLOR1]) { + spec = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->data; + spec_stride = VB->AttribPtr[_TNL_ATTRIB_COLOR1]->stride; } else { spec = (GLfloat (*)[4])ctx->Current.Attrib[VERT_ATTRIB_COLOR1]; spec_stride = 0; @@ -142,9 +142,9 @@ static void TAG(emit)( GLcontext *ctx, } if (DO_SPEC_OR_FOG) { - if (VB->FogCoordPtr) { - fog = VB->FogCoordPtr->data; - fog_stride = VB->FogCoordPtr->stride; + if (VB->AttribPtr[_TNL_ATTRIB_FOG]) { + fog = VB->AttribPtr[_TNL_ATTRIB_FOG]->data; + fog_stride = VB->AttribPtr[_TNL_ATTRIB_FOG]->stride; } else { fog = (GLfloat (*)[4])ctx->Current.Attrib[VERT_ATTRIB_FOG]; fog_stride = 0; diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 78ec1193026..98f96ff2a76 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -326,7 +326,7 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) if (1) { req |= RADEON_CP_VC_FRMT_Z; - if (VB->ObjPtr->size == 4) { + if (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 4) { req |= RADEON_CP_VC_FRMT_W0; } } @@ -348,15 +348,15 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) req |= RADEON_ST_BIT(unit); /* assume we need the 3rd coord if texgen is active for r/q OR at least 3 coords are submitted. This may not be 100% correct */ - if (VB->TexCoordPtr[unit]->size >= 3) { + if (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) { req |= RADEON_Q_BIT(unit); vtx |= RADEON_Q_BIT(unit); } if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) vtx |= RADEON_Q_BIT(unit); - else if ((VB->TexCoordPtr[unit]->size >= 3) && + else if ((VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size >= 3) && ((ctx->Texture.Unit[unit]._ReallyEnabled & (TEXTURE_CUBE_BIT)) == 0)) { - GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3); + GLuint swaptexmatcol = (VB->AttribPtr[_TNL_ATTRIB_TEX0 + unit]->size - 3); if (((rmesa->NeedTexMatrix >> unit) & 1) && (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; @@ -390,19 +390,19 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) * this, add more vertex code (for obj-2, obj-3) or preferably move * to maos. */ - if (VB->ObjPtr->size < 3 || - (VB->ObjPtr->size == 3 && + if (VB->AttribPtr[_TNL_ATTRIB_POS]->size < 3 || + (VB->AttribPtr[_TNL_ATTRIB_POS]->size == 3 && (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) { _math_trans_4f( rmesa->tcl.ObjClean.data, - VB->ObjPtr->data, - VB->ObjPtr->stride, + VB->AttribPtr[_TNL_ATTRIB_POS]->data, + VB->AttribPtr[_TNL_ATTRIB_POS]->stride, GL_FLOAT, - VB->ObjPtr->size, + VB->AttribPtr[_TNL_ATTRIB_POS]->size, 0, VB->Count ); - switch (VB->ObjPtr->size) { + switch (VB->AttribPtr[_TNL_ATTRIB_POS]->size) { case 1: _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1); case 2: @@ -416,14 +416,14 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) break; } - VB->ObjPtr = &rmesa->tcl.ObjClean; + VB->AttribPtr[_TNL_ATTRIB_POS] = &rmesa->tcl.ObjClean; } - + radeon_bo_map(rmesa->radeon.tcl.aos[0].bo, 1); setup_tab[i].emit( ctx, 0, VB->Count, rmesa->radeon.tcl.aos[0].bo->ptr + rmesa->radeon.tcl.aos[0].offset); - + radeon_bo_unmap(rmesa->radeon.tcl.aos[0].bo); // rmesa->radeon.tcl.aos[0].size = setup_tab[i].vertex_size; rmesa->radeon.tcl.aos[0].stride = setup_tab[i].vertex_size; rmesa->tcl.vertex_format = setup_tab[i].vertex_format; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 38db305e2a7..bdbb9460bf0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2009 Maciej Cencora. * Copyright (C) 2008 Nicolai Haehnle. * * All Rights Reserved. @@ -32,51 +33,52 @@ #include "main/simple_list.h" #include "main/texcompress.h" -#include "main/texformat.h" - -static GLuint radeon_compressed_texture_size(GLcontext *ctx, - GLsizei width, GLsizei height, GLsizei depth, - GLuint mesaFormat) +#include "main/teximage.h" +#include "main/texobj.h" +#include "radeon_texture.h" + +static unsigned get_aligned_compressed_row_stride( + gl_format format, + unsigned width, + unsigned minStride) { - GLuint size = _mesa_compressed_texture_size(ctx, width, height, depth, mesaFormat); - - if (mesaFormat == MESA_FORMAT_RGB_DXT1 || - mesaFormat == MESA_FORMAT_RGBA_DXT1) { - if (width + 3 < 8) /* width one block */ - size = size * 4; - else if (width + 3 < 16) - size = size * 2; - } else { - /* DXT3/5, 16 bytes per block */ - // WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n"); - if (width + 3 < 8) - size = size * 2; + const unsigned blockSize = _mesa_get_format_bytes(format); + unsigned blockWidth, blockHeight, numXBlocks; + + _mesa_get_format_block_size(format, &blockWidth, &blockHeight); + numXBlocks = (width + blockWidth - 1) / blockWidth; + + while (numXBlocks * blockSize < minStride) + { + ++numXBlocks; } - return size; + return numXBlocks * blockSize; } +static unsigned get_compressed_image_size( + gl_format format, + unsigned rowStride, + unsigned height) +{ + unsigned blockWidth, blockHeight; + + _mesa_get_format_block_size(format, &blockWidth, &blockHeight); -static int radeon_compressed_num_bytes(GLuint mesaFormat) + return rowStride * ((height + blockHeight - 1) / blockHeight); +} + +static int find_next_power_of_two(GLuint value) { - int bytes = 0; - switch(mesaFormat) { - - case MESA_FORMAT_RGB_FXT1: - case MESA_FORMAT_RGBA_FXT1: - case MESA_FORMAT_RGB_DXT1: - case MESA_FORMAT_RGBA_DXT1: - bytes = 2; - break; - - case MESA_FORMAT_RGBA_DXT3: - case MESA_FORMAT_RGBA_DXT5: - bytes = 4; - default: - break; - } - - return bytes; + int i, tmp; + + i = 0; + tmp = value - 1; + while (tmp) { + tmp >>= 1; + i++; + } + return (1 << i); } /** @@ -91,28 +93,28 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree { radeon_mipmap_level *lvl = &mt->levels[level]; uint32_t row_align; + GLuint height; + + height = find_next_power_of_two(lvl->height); /* Find image size in bytes */ - if (mt->compressed) { - /* TODO: Is this correct? Need test cases for compressed textures! */ - row_align = rmesa->texture_compressed_row_align - 1; - lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; - lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx, - lvl->width, lvl->height, lvl->depth, mt->compressed); + if (_mesa_is_format_compressed(mt->mesaFormat)) { + lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align); + lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height); } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { row_align = rmesa->texture_rect_row_align - 1; - lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; - lvl->size = lvl->rowstride * lvl->height; + lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; + lvl->size = lvl->rowstride * height; } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, * though the actual offset may be different (if texture is less than * 32 bytes width) to the untiled case */ - lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31; - lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth; + lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31; + lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth; } else { row_align = rmesa->texture_row_align - 1; - lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align; - lvl->size = lvl->rowstride * lvl->height * lvl->depth; + lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; + lvl->size = lvl->rowstride * height * lvl->depth; } assert(lvl->size > 0); @@ -124,7 +126,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree if (RADEON_DEBUG & RADEON_TEXTURE) fprintf(stderr, "level %d, face %d: rs:%d %dx%d at %d\n", - level, face, lvl->rowstride, lvl->width, lvl->height, lvl->faces[face].offset); + level, face, lvl->rowstride, lvl->width, height, lvl->faces[face].offset); } static GLuint minify(GLuint size, GLuint levels) @@ -138,22 +140,19 @@ static GLuint minify(GLuint size, GLuint levels) static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { - GLuint curOffset; - GLuint numLevels; - GLuint i; - GLuint face; + GLuint curOffset, i, face, level; - numLevels = mt->lastLevel - mt->firstLevel + 1; - assert(numLevels <= rmesa->glCtx->Const.MaxTextureLevels); + assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); curOffset = 0; for(face = 0; face < mt->faces; face++) { - for(i = 0; i < numLevels; i++) { - mt->levels[i].width = minify(mt->width0, i); - mt->levels[i].height = minify(mt->height0, i); - mt->levels[i].depth = minify(mt->depth0, i); - compute_tex_image_offset(rmesa, mt, face, i, &curOffset); + for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) { + mt->levels[level].valid = 1; + mt->levels[level].width = minify(mt->width0, i); + mt->levels[level].height = minify(mt->height0, i); + mt->levels[level].depth = minify(mt->depth0, i); + compute_tex_image_offset(rmesa, mt, face, level, &curOffset); } } @@ -163,23 +162,21 @@ static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_ static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt) { - GLuint curOffset; - GLuint numLevels; - GLuint i; + GLuint curOffset, i, level; - numLevels = mt->lastLevel - mt->firstLevel + 1; - assert(numLevels <= rmesa->glCtx->Const.MaxTextureLevels); + assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); curOffset = 0; - for(i = 0; i < numLevels; i++) { + for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) { GLuint face; - mt->levels[i].width = minify(mt->width0, i); - mt->levels[i].height = minify(mt->height0, i); - mt->levels[i].depth = minify(mt->depth0, i); + mt->levels[level].valid = 1; + mt->levels[level].width = minify(mt->width0, i); + mt->levels[level].height = minify(mt->height0, i); + mt->levels[level].depth = minify(mt->depth0, i); for(face = 0; face < mt->faces; face++) - compute_tex_image_offset(rmesa, mt, face, i, &curOffset); + compute_tex_image_offset(rmesa, mt, face, level, &curOffset); } /* Note the required size in memory */ @@ -189,27 +186,22 @@ static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_ /** * Create a new mipmap tree, calculate its layout and allocate memory. */ -radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *t, - GLenum target, GLenum internal_format, GLuint firstLevel, GLuint lastLevel, - GLuint width0, GLuint height0, GLuint depth0, - GLuint bpp, GLuint tilebits, GLuint compressed) +static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, + GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, + GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) { radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree); - mt->radeon = rmesa; - mt->internal_format = internal_format; + mt->mesaFormat = mesaFormat; mt->refcount = 1; - mt->t = t; mt->target = target; mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; - mt->firstLevel = firstLevel; - mt->lastLevel = lastLevel; + mt->baseLevel = baseLevel; + mt->numLevels = numLevels; mt->width0 = width0; mt->height0 = height0; mt->depth0 = depth0; - mt->bpp = compressed ? radeon_compressed_num_bytes(compressed) : bpp; mt->tilebits = tilebits; - mt->compressed = compressed; if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300) calculate_miptree_layout_r300(rmesa, mt); @@ -224,53 +216,43 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj * return mt; } -void radeon_miptree_reference(radeon_mipmap_tree *mt) +void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr) { + assert(!*ptr); + mt->refcount++; assert(mt->refcount > 0); + + *ptr = mt; } -void radeon_miptree_unreference(radeon_mipmap_tree *mt) +void radeon_miptree_unreference(radeon_mipmap_tree **ptr) { + radeon_mipmap_tree *mt = *ptr; if (!mt) return; assert(mt->refcount > 0); + mt->refcount--; if (!mt->refcount) { radeon_bo_unref(mt->bo); free(mt); } -} + *ptr = 0; +} /** - * Calculate first and last mip levels for the given texture object, - * where the dimensions are taken from the given texture image at - * the given level. - * - * Note: level is the OpenGL level number, which is not necessarily the same - * as the first level that is actually present. - * - * The base level image of the given texture face must be non-null, - * or this will fail. + * Calculate min and max LOD for the given texture object. + * @param[in] tObj texture object whose LOD values to calculate + * @param[out] pminLod minimal LOD + * @param[out] pmaxLod maximal LOD */ -static void calculate_first_last_level(struct gl_texture_object *tObj, - GLuint *pfirstLevel, GLuint *plastLevel, - GLuint face, GLuint level) +static void calculate_min_max_lod(struct gl_texture_object *tObj, + unsigned *pminLod, unsigned *pmaxLod) { - const struct gl_texture_image * const baseImage = - tObj->Image[face][level]; - - assert(baseImage); - - /* These must be signed values. MinLod and MaxLod can be negative numbers, - * and having firstLevel and lastLevel as signed prevents the need for - * extra sign checks. - */ - int firstLevel; - int lastLevel; - + int minLod, maxLod; /* Yes, this looks overly complicated, but it's all needed. */ switch (tObj->Target) { @@ -281,32 +263,30 @@ static void calculate_first_last_level(struct gl_texture_object *tObj, if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) { /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL. */ - firstLevel = lastLevel = tObj->BaseLevel; + minLod = maxLod = tObj->BaseLevel; } else { - firstLevel = tObj->BaseLevel + (GLint)(tObj->MinLod + 0.5); - firstLevel = MAX2(firstLevel, tObj->BaseLevel); - firstLevel = MIN2(firstLevel, level + baseImage->MaxLog2); - lastLevel = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); - lastLevel = MAX2(lastLevel, tObj->BaseLevel); - lastLevel = MIN2(lastLevel, level + baseImage->MaxLog2); - lastLevel = MIN2(lastLevel, tObj->MaxLevel); - lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ + minLod = tObj->BaseLevel + (GLint)(tObj->MinLod); + minLod = MAX2(minLod, tObj->BaseLevel); + minLod = MIN2(minLod, tObj->MaxLevel); + maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); + maxLod = MIN2(maxLod, tObj->MaxLevel); + maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod); + maxLod = MAX2(maxLod, minLod); /* need at least one level */ } break; case GL_TEXTURE_RECTANGLE_NV: case GL_TEXTURE_4D_SGIS: - firstLevel = lastLevel = 0; + minLod = maxLod = 0; break; default: return; } /* save these values */ - *pfirstLevel = firstLevel; - *plastLevel = lastLevel; + *pminLod = minLod; + *pmaxLod = maxLod; } - /** * Checks whether the given miptree can hold the given texture image at the * given face and level. @@ -316,20 +296,15 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, { radeon_mipmap_level *lvl; - if (face >= mt->faces || level < mt->firstLevel || level > mt->lastLevel) + if (face >= mt->faces) return GL_FALSE; - if (texImage->InternalFormat != mt->internal_format || - texImage->IsCompressed != mt->compressed) + if (texImage->TexFormat != mt->mesaFormat) return GL_FALSE; - if (!texImage->IsCompressed && - !mt->compressed && - texImage->TexFormat->TexelBytes != mt->bpp) - return GL_FALSE; - - lvl = &mt->levels[level - mt->firstLevel]; - if (lvl->width != texImage->Width || + lvl = &mt->levels[level]; + if (!lvl->valid || + lvl->width != texImage->Width || lvl->height != texImage->Height || lvl->depth != texImage->Depth) return GL_FALSE; @@ -337,59 +312,72 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, return GL_TRUE; } - /** * Checks whether the given miptree has the right format to store the given texture object. */ -GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj) +static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj) { struct gl_texture_image *firstImage; - GLuint compressed; - GLuint numfaces = 1; - GLuint firstLevel, lastLevel; - - calculate_first_last_level(texObj, &firstLevel, &lastLevel, 0, texObj->BaseLevel); - if (texObj->Target == GL_TEXTURE_CUBE_MAP) - numfaces = 6; - - firstImage = texObj->Image[0][firstLevel]; - compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0; - - return (mt->firstLevel == firstLevel && - mt->lastLevel == lastLevel && - mt->width0 == firstImage->Width && - mt->height0 == firstImage->Height && - mt->depth0 == firstImage->Depth && - mt->compressed == compressed && - (!mt->compressed ? (mt->bpp == firstImage->TexFormat->TexelBytes) : 1)); -} + unsigned numLevels; + radeon_mipmap_level *mtBaseLevel; + if (texObj->BaseLevel < mt->baseLevel) + return GL_FALSE; + + mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel]; + firstImage = texObj->Image[0][texObj->BaseLevel]; + numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1); + + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj); + fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target); + fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat); + fprintf(stderr, "numLevels %d vs %d\n", mt->numLevels, numLevels); + fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width); + fprintf(stderr, "height0 %d vs %d\n", mtBaseLevel->height, firstImage->Height); + fprintf(stderr, "depth0 %d vs %d\n", mtBaseLevel->depth, firstImage->Depth); + if (mt->target == texObj->Target && + mt->mesaFormat == firstImage->TexFormat && + mt->numLevels >= numLevels && + mtBaseLevel->width == firstImage->Width && + mtBaseLevel->height == firstImage->Height && + mtBaseLevel->depth == firstImage->Depth) { + fprintf(stderr, "MATCHED\n"); + } else { + fprintf(stderr, "NOT MATCHED\n"); + } + } + + return (mt->target == texObj->Target && + mt->mesaFormat == firstImage->TexFormat && + mt->numLevels >= numLevels && + mtBaseLevel->width == firstImage->Width && + mtBaseLevel->height == firstImage->Height && + mtBaseLevel->depth == firstImage->Depth); +} /** - * Try to allocate a mipmap tree for the given texture that will fit the - * given image in the given position. + * Try to allocate a mipmap tree for the given texture object. + * @param[in] rmesa radeon context + * @param[in] t radeon texture object */ -void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, - radeon_texture_image *image, GLuint face, GLuint level) +void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) { - GLuint compressed = image->base.IsCompressed ? image->base.TexFormat->MesaFormat : 0; - GLuint numfaces = 1; - GLuint firstLevel, lastLevel; + struct gl_texture_object *texObj = &t->base; + struct gl_texture_image *texImg = texObj->Image[0][texObj->BaseLevel]; + GLuint numLevels; assert(!t->mt); - calculate_first_last_level(&t->base, &firstLevel, &lastLevel, face, level); - if (t->base.Target == GL_TEXTURE_CUBE_MAP) - numfaces = 6; - - if (level != firstLevel || face >= numfaces) + if (!texImg) return; - t->mt = radeon_miptree_create(rmesa, t, t->base.Target, - image->base.InternalFormat, - firstLevel, lastLevel, - image->base.Width, image->base.Height, image->base.Depth, - image->base.TexFormat->TexelBytes, t->tile_bits, compressed); + numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1); + + t->mt = radeon_miptree_create(rmesa, t->base.Target, + texImg->TexFormat, texObj->BaseLevel, + numLevels, texImg->Width, texImg->Height, + texImg->Depth, t->tile_bits); } /* Although we use the image_offset[] array to store relative offsets @@ -401,21 +389,233 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets) { - if (mt->target != GL_TEXTURE_3D || mt->faces == 1) - offsets[0] = 0; - else { - int i; - for (i = 0; i < 6; i++) - offsets[i] = mt->levels[level].faces[i].offset; - } + if (mt->target != GL_TEXTURE_3D || mt->faces == 1) { + offsets[0] = 0; + } else { + int i; + for (i = 0; i < 6; i++) { + offsets[i] = mt->levels[level].faces[i].offset; + } + } } GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt, GLuint face, GLuint level) { - if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) - return (mt->levels[level].faces[face].offset); - else - return mt->levels[level].faces[0].offset; + if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) + return (mt->levels[level].faces[face].offset); + else + return mt->levels[level].faces[0].offset; +} + +/** + * Ensure that the given image is stored in the given miptree from now on. + */ +static void migrate_image_to_miptree(radeon_mipmap_tree *mt, + radeon_texture_image *image, + int face, int level) +{ + radeon_mipmap_level *dstlvl = &mt->levels[level]; + unsigned char *dest; + + assert(image->mt != mt); + assert(dstlvl->valid); + assert(dstlvl->width == image->base.Width); + assert(dstlvl->height == image->base.Height); + assert(dstlvl->depth == image->base.Depth); + + radeon_bo_map(mt->bo, GL_TRUE); + dest = mt->bo->ptr + dstlvl->faces[face].offset; + + if (image->mt) { + /* Format etc. should match, so we really just need a memcpy(). + * In fact, that memcpy() could be done by the hardware in many + * cases, provided that we have a proper memory manager. + */ + assert(mt->mesaFormat == image->base.TexFormat); + + radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; + + assert(image->mtlevel == level); + assert(srclvl->size == dstlvl->size); + assert(srclvl->rowstride == dstlvl->rowstride); + + radeon_bo_map(image->mt->bo, GL_FALSE); + + memcpy(dest, + image->mt->bo->ptr + srclvl->faces[face].offset, + dstlvl->size); + radeon_bo_unmap(image->mt->bo); + + radeon_miptree_unreference(&image->mt); + } else { + /* need to confirm this value is correct */ + if (_mesa_is_format_compressed(image->base.TexFormat)) { + unsigned size = _mesa_format_image_size(image->base.TexFormat, + image->base.Width, + image->base.Height, + image->base.Depth); + memcpy(dest, image->base.Data, size); + } else { + uint32_t srcrowstride; + uint32_t height; + + height = image->base.Height * image->base.Depth; + srcrowstride = image->base.Width * _mesa_get_format_bytes(image->base.TexFormat); + copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, + height, srcrowstride); + } + + _mesa_free_texmemory(image->base.Data); + image->base.Data = 0; + } + + radeon_bo_unmap(mt->bo); + + radeon_miptree_reference(mt, &image->mt); + image->mtface = face; + image->mtlevel = level; +} + +/** + * Filter matching miptrees, and select one with the most of data. + * @param[in] texObj radeon texture object + * @param[in] firstLevel first texture level to check + * @param[in] lastLevel last texture level to check + */ +static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj, + unsigned firstLevel, + unsigned lastLevel) +{ + const unsigned numLevels = lastLevel - firstLevel + 1; + unsigned *mtSizes = calloc(numLevels, sizeof(unsigned)); + radeon_mipmap_tree **mts = calloc(numLevels, sizeof(radeon_mipmap_tree *)); + unsigned mtCount = 0; + unsigned maxMtIndex = 0; + radeon_mipmap_tree *tmp; + + for (unsigned level = firstLevel; level <= lastLevel; ++level) { + radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]); + unsigned found = 0; + // TODO: why this hack?? + if (!img) + break; + + if (!img->mt) + continue; + + for (int i = 0; i < mtCount; ++i) { + if (mts[i] == img->mt) { + found = 1; + mtSizes[i] += img->mt->levels[img->mtlevel].size; + break; + } + } + + if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) { + mtSizes[mtCount] = img->mt->levels[img->mtlevel].size; + mts[mtCount] = img->mt; + mtCount++; + } + } + + if (mtCount == 0) { + return NULL; + } + + for (int i = 1; i < mtCount; ++i) { + if (mtSizes[i] > mtSizes[maxMtIndex]) { + maxMtIndex = i; + } + } + + tmp = mts[maxMtIndex]; + free(mtSizes); + free(mts); + + return tmp; } + +/** + * Validate texture mipmap tree. + * If individual images are stored in different mipmap trees + * use the mipmap tree that has the most of the correct data. + */ +int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) +{ + radeonContextPtr rmesa = RADEON_CONTEXT(ctx); + radeonTexObj *t = radeon_tex_obj(texObj); + + if (t->validated || t->image_override) { + return GL_TRUE; + } + + if (texObj->Image[0][texObj->BaseLevel]->Border > 0) + return GL_FALSE; + + _mesa_test_texobj_completeness(rmesa->glCtx, texObj); + if (!texObj->_Complete) { + return GL_FALSE; + } + + calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod); + + if (RADEON_DEBUG & RADEON_TEXTURE) + fprintf(stderr, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n", + __FUNCTION__, texObj ,t->minLod, t->maxLod); + + radeon_mipmap_tree *dst_miptree; + dst_miptree = get_biggest_matching_miptree(t, t->minLod, t->maxLod); + + if (!dst_miptree) { + radeon_miptree_unreference(&t->mt); + radeon_try_alloc_miptree(rmesa, t); + dst_miptree = t->mt; + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__, t->mt); + } + } else if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "%s: Using miptree %p\n", __FUNCTION__, t->mt); + } + + const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1; + unsigned face, level; + radeon_texture_image *img; + /* Validate only the levels that will actually be used during rendering */ + for (face = 0; face < faces; ++face) { + for (level = t->minLod; level <= t->maxLod; ++level) { + img = get_radeon_texture_image(texObj->Image[face][level]); + + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "Checking image level %d, face %d, mt %p ... ", level, face, img->mt); + } + + if (img->mt != dst_miptree) { + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "MIGRATING\n"); + } + struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo; + if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) { + radeon_firevertices(rmesa); + } + migrate_image_to_miptree(dst_miptree, img, face, level); + } else if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "OK\n"); + } + } + } + + t->validated = GL_TRUE; + + return GL_TRUE; +} + +uint32_t get_base_teximage_offset(radeonTexObj *texObj) +{ + if (!texObj->mt) { + return 0; + } else { + return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod); + } +}
\ No newline at end of file diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h index db28252da37..a10649b5aea 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h @@ -44,6 +44,7 @@ struct _radeon_mipmap_level { GLuint depth; GLuint size; /** Size of each image, in bytes */ GLuint rowstride; /** in bytes */ + GLuint valid; radeon_mipmap_image faces[6]; }; @@ -59,43 +60,35 @@ struct _radeon_mipmap_level { * changed. */ struct _radeon_mipmap_tree { - radeonContextPtr radeon; - radeonTexObj *t; struct radeon_bo *bo; GLuint refcount; GLuint totalsize; /** total size of the miptree, in bytes */ GLenum target; /** GL_TEXTURE_xxx */ - GLenum internal_format; + GLenum mesaFormat; /** MESA_FORMAT_xxx */ GLuint faces; /** # of faces: 6 for cubemaps, 1 otherwise */ - GLuint firstLevel; /** First mip level stored in this mipmap tree */ - GLuint lastLevel; /** Last mip level stored in this mipmap tree */ + GLuint baseLevel; /** gl_texture_object->baseLevel it was created for */ + GLuint numLevels; /** Number of mip levels stored in this mipmap tree */ - GLuint width0; /** Width of firstLevel image */ - GLuint height0; /** Height of firstLevel image */ - GLuint depth0; /** Depth of firstLevel image */ + GLuint width0; /** Width of baseLevel image */ + GLuint height0; /** Height of baseLevel image */ + GLuint depth0; /** Depth of baseLevel image */ - GLuint bpp; /** Bytes per texel */ GLuint tilebits; /** RADEON_TXO_xxx_TILE */ - GLuint compressed; /** MESA_FORMAT_xxx indicating a compressed format, or 0 if uncompressed */ radeon_mipmap_level levels[RADEON_MIPTREE_MAX_TEXTURE_LEVELS]; }; -radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *t, - GLenum target, GLenum internal_format, GLuint firstLevel, GLuint lastLevel, - GLuint width0, GLuint height0, GLuint depth0, - GLuint bpp, GLuint tilebits, GLuint compressed); -void radeon_miptree_reference(radeon_mipmap_tree *mt); -void radeon_miptree_unreference(radeon_mipmap_tree *mt); +void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr); +void radeon_miptree_unreference(radeon_mipmap_tree **ptr); GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, struct gl_texture_image *texImage, GLuint face, GLuint level); -GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj); -void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, - radeon_texture_image *texImage, GLuint face, GLuint level); +void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t); GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt, GLuint face, GLuint level); void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets); + +uint32_t get_base_teximage_offset(radeonTexObj *texObj); #endif /* __RADEON_MIPMAP_TREE_H_ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c index b79d864ba29..98117cdfc14 100644 --- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c +++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c @@ -31,24 +31,11 @@ #include "main/imports.h" #include "main/simple_list.h" -static int radeonQueryIsFlushed(GLcontext *ctx, struct gl_query_object *q) -{ - radeonContextPtr radeon = RADEON_CONTEXT(ctx); - struct radeon_query_object *tmp, *query = (struct radeon_query_object *)q; - - foreach(tmp, &radeon->query.not_flushed_head) { - if (tmp == query) { - return 0; - } - } - - return 1; -} - static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = (struct radeon_query_object *)q; - uint32_t *result; + uint32_t *result; int i; radeon_print(RADEON_STATE, RADEON_VERBOSE, @@ -56,13 +43,35 @@ static void radeonQueryGetResult(GLcontext *ctx, struct gl_query_object *q) __FUNCTION__, query->Base.Id, (int) query->Base.Result); radeon_bo_map(query->bo, GL_FALSE); - - result = query->bo->ptr; + result = query->bo->ptr; query->Base.Result = 0; - for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) { - query->Base.Result += result[i]; - radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, result[i]); + if (IS_R600_CLASS(radeon->radeonScreen)) { + /* ZPASS EVENT writes alternating qwords + * At query start we set the start offset to 0 and + * hw writes zpass start counts to qwords 0, 2, 4, 6. + * At query end we set the start offset to 8 and + * hw writes zpass end counts to qwords 1, 3, 5, 7. + * then we substract. MSB is the valid bit. + */ + for (i = 0; i < 16; i += 4) { + uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) | + (uint64_t)LE32_TO_CPU(result[i + 1]) << 32; + uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) | + (uint64_t)LE32_TO_CPU(result[i + 3]) << 32; + if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) { + uint64_t query_count = end - start; + query->Base.Result += query_count; + + } + radeon_print(RADEON_STATE, RADEON_TRACE, + "%d start: %lx, end: %lx %ld\n", i, start, end, end - start); + } + } else { + for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) { + query->Base.Result += LE32_TO_CPU(result[i]); + radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i])); + } } radeon_bo_unmap(query->bo); @@ -99,10 +108,11 @@ static void radeonDeleteQuery(GLcontext *ctx, struct gl_query_object *q) static void radeonWaitQuery(GLcontext *ctx, struct gl_query_object *q) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); struct radeon_query_object *query = (struct radeon_query_object *)q; /* If the cmdbuf with packets for this query hasn't been flushed yet, do it now */ - if (!radeonQueryIsFlushed(ctx, q)) + if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) ctx->Driver.Flush(ctx); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s: query id %d, bo %p, offset %d\n", __FUNCTION__, q->Id, query->bo, query->curr_offset); @@ -134,8 +144,6 @@ static void radeonBeginQuery(GLcontext *ctx, struct gl_query_object *q) radeon->query.queryobj.dirty = GL_TRUE; radeon->hw.is_dirty = GL_TRUE; - insert_at_tail(&radeon->query.not_flushed_head, query); - } void radeonEmitQueryEnd(GLcontext *ctx) @@ -183,7 +191,7 @@ static void radeonCheckQuery(GLcontext *ctx, struct gl_query_object *q) uint32_t domain; /* Need to perform a flush, as per ARB_occlusion_query spec */ - if (!radeonQueryIsFlushed(ctx, q)) { + if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) { ctx->Driver.Flush(ctx); } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 573eb6c9c18..be2d8365ef5 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -141,12 +141,6 @@ DRI_CONF_BEGIN DRI_CONF_END; static const GLuint __driNConfigOptions = 17; -extern const struct dri_extension blend_extensions[]; -extern const struct dri_extension ARB_vp_extension[]; -extern const struct dri_extension NV_vp_extension[]; -extern const struct dri_extension ATI_fs_extension[]; -extern const struct dri_extension point_extensions[]; - #elif defined(RADEON_R300) || defined(RADEON_R600) #define DRI_CONF_FP_OPTIMIZATION_SPEED 0 @@ -218,13 +212,8 @@ DRI_CONF_BEGIN DRI_CONF_END; static const GLuint __driNConfigOptions = 17; -extern const struct dri_extension gl_20_extension[]; - #endif -extern const struct dri_extension card_extensions[]; -extern const struct dri_extension mm_extensions[]; - static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); static int @@ -401,12 +390,14 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) screen->device_id = device_id; screen->chip_flags = 0; switch ( device_id ) { + case PCI_CHIP_RN50_515E: + case PCI_CHIP_RN50_5969: + return -1; + case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: case PCI_CHIP_RADEON_QY: case PCI_CHIP_RADEON_QZ: - case PCI_CHIP_RN50_515E: - case PCI_CHIP_RN50_5969: screen->chip_family = CHIP_FAMILY_RV100; break; @@ -1480,7 +1471,7 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, const GLboolean swAccum = mesaVis->accumRedBits > 0; const GLboolean swStencil = mesaVis->stencilBits > 0 && mesaVis->depthBits != 24; - GLenum rgbFormat; + gl_format rgbFormat; struct radeon_framebuffer *rfb; if (isPixmap) @@ -1493,11 +1484,11 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, _mesa_initialize_framebuffer(&rfb->base, mesaVis); if (mesaVis->redBits == 5) - rgbFormat = GL_RGB5; + rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV; else if (mesaVis->alphaBits == 0) - rgbFormat = GL_RGB8; + rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV; else - rgbFormat = GL_RGBA8; + rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV; /* front color renderbuffer */ rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); @@ -1513,19 +1504,22 @@ radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, if (mesaVis->depthBits == 24) { if (mesaVis->stencilBits == 8) { - struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); + struct radeon_renderbuffer *depthStencilRb = + radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); depthStencilRb->has_surface = screen->depthHasSurface; } else { /* depth renderbuffer */ - struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); + struct radeon_renderbuffer *depth = + radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); depth->has_surface = screen->depthHasSurface; } } else if (mesaVis->depthBits == 16) { - /* just 16-bit depth buffer, no hw stencil */ - struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); + /* just 16-bit depth buffer, no hw stencil */ + struct radeon_renderbuffer *depth = + radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); depth->has_surface = screen->depthHasSurface; } @@ -1619,27 +1613,6 @@ radeonInitScreen(__DRIscreenPrivate *psp) return NULL; } - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create - * is called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); -#if defined(RADEON_R200) - driInitExtensions( NULL, blend_extensions, GL_FALSE ); - driInitSingleExtension( NULL, ARB_vp_extension ); - driInitSingleExtension( NULL, NV_vp_extension ); - driInitSingleExtension( NULL, ATI_fs_extension ); - driInitExtensions( NULL, point_extensions, GL_FALSE ); -#elif (defined(RADEON_R300) || defined(RADEON_R600)) - driInitSingleExtension( NULL, gl_20_extension ); -#endif - if (!radeonInitDriver(psp)) return NULL; @@ -1672,28 +1645,6 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) int color; __DRIconfig **configs = NULL; - /* Calling driInitExtensions here, with a NULL context pointer, - * does not actually enable the extensions. It just makes sure - * that all the dispatch offsets for all the extensions that - * *might* be enables are known. This is needed because the - * dispatch offsets need to be known when _mesa_context_create - * is called, but we can't enable the extensions until we have a - * context pointer. - * - * Hello chicken. Hello egg. How are you two today? - */ - driInitExtensions( NULL, card_extensions, GL_FALSE ); - driInitExtensions( NULL, mm_extensions, GL_FALSE ); -#if defined(RADEON_R200) - driInitExtensions( NULL, blend_extensions, GL_FALSE ); - driInitSingleExtension( NULL, ARB_vp_extension ); - driInitSingleExtension( NULL, NV_vp_extension ); - driInitSingleExtension( NULL, ATI_fs_extension ); - driInitExtensions( NULL, point_extensions, GL_FALSE ); -#elif (defined(RADEON_R300) || defined(RADEON_R600)) - driInitSingleExtension( NULL, gl_20_extension ); -#endif - if (!radeonInitDriver(psp)) { return NULL; } diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c index 0c49c3713af..37904dc8dc9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_span.c +++ b/src/mesa/drivers/dri/radeon/radeon_span.c @@ -41,6 +41,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "main/glheader.h" +#include "main/texformat.h" #include "swrast/swrast.h" #include "radeon_common.h" @@ -334,22 +335,6 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb, #endif -#ifndef RADEON_R300 -#ifndef RADEON_R600 -static uint32_t -z24s8_to_s8z24(uint32_t val) -{ - return (val << 24) | (val >> 8); -} - -static uint32_t -s8z24_to_z24s8(uint32_t val) -{ - return (val >> 24) | (val << 8); -} -#endif -#endif - /* * Note that all information needed to access pixels in a renderbuffer * should be obtained through the gl_renderbuffer parameter, not per-context @@ -416,6 +401,18 @@ s8z24_to_z24s8(uint32_t val) #endif #include "spantmp2.h" +#define SPANTMP_PIXEL_FMT GL_RGB +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5_REV + +#define TAG(x) radeon##x##_RGB565_REV +#define TAG2(x,y) radeon##x##_RGB565_REV##y +#if defined(RADEON_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else +#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off) +#endif +#include "spantmp2.h" + /* 16 bit, ARGB1555 color spanline and pixel functions */ #define SPANTMP_PIXEL_FMT GL_BGRA @@ -430,6 +427,18 @@ s8z24_to_z24s8(uint32_t val) #endif #include "spantmp2.h" +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_1_5_5_5 + +#define TAG(x) radeon##x##_ARGB1555_REV +#define TAG2(x,y) radeon##x##_ARGB1555_REV##y +#if defined(RADEON_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else +#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off) +#endif +#include "spantmp2.h" + /* 16 bit, RGBA4 color spanline and pixel functions */ #define SPANTMP_PIXEL_FMT GL_BGRA @@ -444,6 +453,18 @@ s8z24_to_z24s8(uint32_t val) #endif #include "spantmp2.h" +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_4_4_4_4 + +#define TAG(x) radeon##x##_ARGB4444_REV +#define TAG2(x,y) radeon##x##_ARGB4444_REV##y +#if defined(RADEON_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else +#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off) +#endif +#include "spantmp2.h" + /* 32 bit, xRGB8888 color spanline and pixel functions */ #define SPANTMP_PIXEL_FMT GL_BGRA @@ -488,6 +509,42 @@ s8z24_to_z24s8(uint32_t val) #endif #include "spantmp2.h" +/* 32 bit, BGRx8888 color spanline and pixel functions + */ +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8 + +#define TAG(x) radeon##x##_BGRx8888 +#define TAG2(x,y) radeon##x##_BGRx8888##y +#if defined(RADEON_R600) +#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0x000000ff)) +#define PUT_VALUE(_x, _y, d) { \ + GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \ + *_ptr = d; \ +} while (0) +#else +#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0x000000ff)) +#define PUT_VALUE(_x, _y, d) { \ + GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ + *_ptr = d; \ +} while (0) +#endif +#include "spantmp2.h" + +/* 32 bit, BGRA8888 color spanline and pixel functions + */ +#define SPANTMP_PIXEL_FMT GL_BGRA +#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8 + +#define TAG(x) radeon##x##_BGRA8888 +#define TAG2(x,y) radeon##x##_BGRA8888##y +#if defined(RADEON_R600) +#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off) +#else +#define GET_PTR(X,Y) radeon_ptr_4byte(rrb, (X) + x_off, (Y) + y_off) +#endif +#include "spantmp2.h" + /* ================================================================ * Depth buffer */ @@ -542,10 +599,10 @@ s8z24_to_z24s8(uint32_t val) #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ tmp &= 0x000000ff; \ tmp |= ((d << 8) & 0xffffff00); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(tmp); \ } while (0) #elif defined(RADEON_R600) #define WRITE_DEPTH( _x, _y, d ) \ @@ -560,26 +617,26 @@ do { \ #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(tmp); \ } while (0) #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ tmp &= 0xff000000; \ tmp |= ((d) & 0x00ffffff); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(tmp); \ } while (0) #endif #if defined(RADEON_R300) #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \ + d = (LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))) & 0xffffff00) >> 8; \ }while(0) #elif defined(RADEON_R600) #define READ_DEPTH( d, _x, _y ) \ @@ -589,11 +646,11 @@ do { \ #elif defined(RADEON_R200) #define READ_DEPTH( d, _x, _y ) \ do { \ - d = *(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off)) & 0x00ffffff; \ + d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; \ }while(0) #else #define READ_DEPTH( d, _x, _y ) \ - d = *(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) & 0x00ffffff; + d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; #endif #define TAG(x) radeon##x##_z24 @@ -611,7 +668,7 @@ do { \ #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ - *_ptr = d; \ + *_ptr = CPU_TO_LE32((((d) & 0xff000000) >> 24) | (((d) & 0x00ffffff) << 8)); \ } while (0) #elif defined(RADEON_R600) #define WRITE_DEPTH( _x, _y, d ) \ @@ -619,53 +676,52 @@ do { \ GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \ GLuint tmp = *_ptr; \ tmp &= 0xff000000; \ - tmp |= (((d) >> 8) & 0x00ffffff); \ + tmp |= ((d) & 0x00ffffff); \ *_ptr = tmp; \ _ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \ tmp = *_ptr; \ tmp &= 0xffffff00; \ - tmp |= (d) & 0xff; \ + tmp |= ((d) >> 24) & 0xff; \ *_ptr = tmp; \ } while (0) #elif defined(RADEON_R200) #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = z24s8_to_s8z24(d); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(d); \ } while (0) #else #define WRITE_DEPTH( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = z24s8_to_s8z24(d); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(d); \ } while (0) #endif #if defined(RADEON_R300) #define READ_DEPTH( d, _x, _y ) \ do { \ - d = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \ + GLuint tmp = (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \ + d = LE32_TO_CPU(((tmp & 0x000000ff) << 24) | ((tmp & 0xffffff00) >> 8)); \ }while(0) #elif defined(RADEON_R600) #define READ_DEPTH( d, _x, _y ) \ do { \ - d = ((*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) << 8) & 0xffffff00; \ - d |= (*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) & 0x000000ff; \ + d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; \ + d |= ((*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) << 24) & 0xff000000; \ }while(0) #elif defined(RADEON_R200) #define READ_DEPTH( d, _x, _y ) \ do { \ - d = s8z24_to_z24s8(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off))); \ + d = LE32_TO_CPU(*(GLuint*)(r200_depth_4byte(rrb, _x + x_off, _y + y_off))); \ }while(0) #else #define READ_DEPTH( d, _x, _y ) do { \ - d = s8z24_to_z24s8(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off ))); \ + d = LE32_TO_CPU(*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off))); \ } while (0) #endif -#define TAG(x) radeon##x##_z24_s8 +#define TAG(x) radeon##x##_s8_z24 #include "depthtmp.h" /* ================================================================ @@ -678,10 +734,10 @@ do { \ #define WRITE_STENCIL( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ tmp &= 0xffffff00; \ tmp |= (d) & 0xff; \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(tmp); \ } while (0) #elif defined(RADEON_R600) #define WRITE_STENCIL( _x, _y, d ) \ @@ -696,19 +752,19 @@ do { \ #define WRITE_STENCIL( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)r200_depth_4byte(rrb, _x + x_off, _y + y_off); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(tmp); \ } while (0) #else #define WRITE_STENCIL( _x, _y, d ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte(rrb, _x + x_off, _y + y_off); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ tmp &= 0x00ffffff; \ tmp |= (((d) & 0xff) << 24); \ - *_ptr = tmp; \ + *_ptr = CPU_TO_LE32(tmp); \ } while (0) #endif @@ -716,7 +772,7 @@ do { \ #define READ_STENCIL( d, _x, _y ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ d = tmp & 0x000000ff; \ } while (0) #elif defined(RADEON_R600) @@ -730,19 +786,19 @@ do { \ #define READ_STENCIL( d, _x, _y ) \ do { \ GLuint *_ptr = (GLuint*)r200_depth_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ d = (tmp & 0xff000000) >> 24; \ } while (0) #else #define READ_STENCIL( d, _x, _y ) \ do { \ GLuint *_ptr = (GLuint*)radeon_ptr_4byte( rrb, _x + x_off, _y + y_off ); \ - GLuint tmp = *_ptr; \ + GLuint tmp = LE32_TO_CPU(*_ptr); \ d = (tmp & 0xff000000) >> 24; \ } while (0) #endif -#define TAG(x) radeon##x##_z24_s8 +#define TAG(x) radeon##x##_s8_z24 #include "stenciltmp.h" @@ -864,25 +920,35 @@ void radeonInitSpanFuncs(GLcontext * ctx) */ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb) { - if (rrb->base._ActualFormat == GL_RGB5) { + if (rrb->base.Format == MESA_FORMAT_RGB565) { radeonInitPointers_RGB565(&rrb->base); - } else if (rrb->base._ActualFormat == GL_RGB8) { + } else if (rrb->base.Format == MESA_FORMAT_RGB565_REV) { + radeonInitPointers_RGB565_REV(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_XRGB8888) { radeonInitPointers_xRGB8888(&rrb->base); - } else if (rrb->base._ActualFormat == GL_RGBA8) { + } else if (rrb->base.Format == MESA_FORMAT_XRGB8888_REV) { + radeonInitPointers_BGRx8888(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_ARGB8888) { radeonInitPointers_ARGB8888(&rrb->base); - } else if (rrb->base._ActualFormat == GL_RGBA4) { + } else if (rrb->base.Format == MESA_FORMAT_ARGB8888_REV) { + radeonInitPointers_BGRA8888(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_ARGB4444) { radeonInitPointers_ARGB4444(&rrb->base); - } else if (rrb->base._ActualFormat == GL_RGB5_A1) { + } else if (rrb->base.Format == MESA_FORMAT_ARGB4444_REV) { + radeonInitPointers_ARGB4444_REV(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_ARGB1555) { radeonInitPointers_ARGB1555(&rrb->base); - } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT16) { + } else if (rrb->base.Format == MESA_FORMAT_ARGB1555_REV) { + radeonInitPointers_ARGB1555_REV(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_Z16) { radeonInitDepthPointers_z16(&rrb->base); - } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) { + } else if (rrb->base.Format == MESA_FORMAT_X8_Z24) { radeonInitDepthPointers_z24(&rrb->base); - } else if (rrb->base._ActualFormat == GL_DEPTH24_STENCIL8_EXT) { - radeonInitDepthPointers_z24_s8(&rrb->base); - } else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) { - radeonInitStencilPointers_z24_s8(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_S8_Z24) { + radeonInitDepthPointers_s8_z24(&rrb->base); + } else if (rrb->base.Format == MESA_FORMAT_S8) { + radeonInitStencilPointers_s8_z24(&rrb->base); } else { - fprintf(stderr, "radeonSetSpanFunctions: bad actual format: 0x%04X\n", rrb->base._ActualFormat); + fprintf(stderr, "radeonSetSpanFunctions: bad format: 0x%04X\n", rrb->base.Format); } } diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index f3ad0dd17af..dd828882543 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -440,16 +440,18 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); if (rrb->cpp == 4) atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else switch (rrb->base._ActualFormat) { - case GL_RGB5: + else switch (rrb->base.Format) { + case MESA_FORMAT_RGB565: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; break; - case GL_RGBA4: + case MESA_FORMAT_ARGB4444: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; break; - case GL_RGB5_A1: + case MESA_FORMAT_ARGB1555: atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; break; + default: + _mesa_problem(ctx, "unexpected format in ctx_emit_cs()"); } cbpitch = (rrb->pitch / rrb->cpp); @@ -643,11 +645,11 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0)); if (t->mt && !t->image_override) { if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) { - lvl = &t->mt->levels[0]; + lvl = &t->mt->levels[t->minLod]; OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } else { - OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, + OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); } } else { diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c index e61f59eaeaf..8bf1bfbc575 100644 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c @@ -179,7 +179,7 @@ static void radeonSetVertexFormat( GLcontext *ctx ) for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) { - GLuint sz = VB->TexCoordPtr[i]->size; + GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size; switch (sz) { case 1: @@ -309,7 +309,7 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset) radeonEmitState(&rmesa->radeon); radeonEmitVertexAOS( rmesa, rmesa->radeon.swtcl.vertex_size, - first_elem(&rmesa->radeon.dma.reserved)->bo, + rmesa->radeon.swtcl.bo, current_offset); diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 99865fff27b..749ab75f201 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "main/image.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" @@ -349,17 +348,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_MAX_LEVEL: case GL_TEXTURE_MIN_LOD: case GL_TEXTURE_MAX_LOD: - - /* This isn't the most efficient solution but there doesn't appear to - * be a nice alternative. Since there's no LOD clamping, - * we just have to rely on loading the right subset of mipmap levels - * to simulate a clamped LOD. - */ - if (t->mt) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - t->validated = GL_FALSE; - } + t->validated = GL_FALSE; break; default: @@ -389,10 +378,8 @@ static void radeonDeleteTexture( GLcontext *ctx, } } - if (t->mt) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - } + radeon_miptree_unreference(&t->mt); + /* Free mipmap images and the texture object itself */ _mesa_delete_texture_object(ctx, texObj); } diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index ae41b90efe5..3cbe3b47254 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -38,8 +38,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" +#include "main/texstate.h" #include "main/texobj.h" #include "main/enums.h" @@ -81,8 +81,10 @@ struct tx_table { GLuint format, filter; }; +/* XXX verify this table against MESA_FORMAT_x values */ static const struct tx_table tx_table[] = { + _INVALID(NONE), /* MESA_FORMAT_NONE */ _ALPHA(RGBA8888), _ALPHA_REV(RGBA8888), _ALPHA(ARGB8888), @@ -660,7 +662,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ rmesa = pDRICtx->driverPrivate; rfb = dPriv->driverPrivate; - texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit]; + texUnit = _mesa_get_current_tex_unit(radeon->glCtx); texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target); texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0); @@ -697,20 +699,14 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ radeon_bo_unref(rImage->bo); rImage->bo = NULL; } - if (t->mt) { - radeon_miptree_unreference(t->mt); - t->mt = NULL; - } - if (rImage->mt) { - radeon_miptree_unreference(rImage->mt); - rImage->mt = NULL; - } + + radeon_miptree_unreference(&t->mt); + radeon_miptree_unreference(&rImage->mt); + _mesa_init_teximage_fields(radeon->glCtx, target, texImage, rb->base.Width, rb->base.Height, 1, 0, rb->cpp); texImage->RowStride = rb->pitch / rb->cpp; - texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx, - internalFormat, - type, format, 0); + rImage->bo = rb->bo; radeon_bo_ref(rImage->bo); t->bo = rb->bo; @@ -718,8 +714,6 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ t->tile_bits = 0; t->image_override = GL_TRUE; t->override_offset = 0; - t->pp_txpitch &= (1 << 13) -1; - pitch_val = rb->pitch; switch (rb->cpp) { case 4: if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) @@ -738,12 +732,17 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter; break; } - t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT) - | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT); - t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; - t->pp_txpitch = pitch_val; - t->pp_txpitch -= 32; + t->pp_txpitch &= (1 << 13) -1; + pitch_val = rb->pitch; + + t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT) + | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT); + if (target == GL_TEXTURE_RECTANGLE_NV) { + t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2; + t->pp_txpitch = pitch_val; + t->pp_txpitch -= 32; + } t->validated = GL_TRUE; _mesa_unlock_texture(radeon->glCtx, texObj); return; @@ -1021,7 +1020,7 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int return GL_TRUE; } - firstImage = t->base.Image[0][t->mt->firstLevel]; + firstImage = t->base.Image[0][t->minLod]; if (firstImage->Border > 0) { fprintf(stderr, "%s: border\n", __FUNCTION__); @@ -1031,27 +1030,27 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; - texelBytes = firstImage->TexFormat->TexelBytes; + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); if (!t->image_override) { - if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + if (VALID_FORMAT(firstImage->TexFormat)) { const struct tx_table *table = tx_table; t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | RADEON_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + t->pp_txformat |= table[ firstImage->TexFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat ].filter; } else { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); return GL_FALSE; } } - + t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; - t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << RADEON_MAX_MIP_LEVEL_SHIFT; + t->pp_txfilter |= (t->maxLod - t->minLod) << RADEON_MAX_MIP_LEVEL_SHIFT; t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK | RADEON_TXFORMAT_HEIGHT_MASK | @@ -1060,9 +1059,9 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int RADEON_TXFORMAT_F5_HEIGHT_MASK); t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) | (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT)); - + t->tile_bits = 0; - + if (t->base.Target == GL_TEXTURE_CUBE_MAP) { ASSERT(log2Width == log2Height); t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) | @@ -1083,7 +1082,7 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT)); if ( !t->image_override ) { - if (firstImage->IsCompressed) + if (_mesa_is_format_compressed(firstImage->TexFormat)) t->pp_txpitch = (firstImage->Width + 63) & ~(63); else t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63); diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 7b7392b2179..0390d376ba2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2009 Maciej Cencora. * Copyright (C) 2008 Nicolai Haehnle. * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. * @@ -34,7 +35,6 @@ #include "main/convolve.h" #include "main/mipmap.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" @@ -47,7 +47,7 @@ #include "radeon_mipmap_tree.h" -static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, +void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, GLuint numrows, GLuint rowsize) { assert(rowsize <= dststride); @@ -82,8 +82,7 @@ void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage) radeon_texture_image* image = get_radeon_texture_image(timage); if (image->mt) { - radeon_miptree_unreference(image->mt); - image->mt = 0; + radeon_miptree_unreference(&image->mt); assert(!image->base.Data); } else { _mesa_free_texture_image_data(ctx, timage); @@ -109,7 +108,7 @@ static void teximage_set_map_data(radeon_texture_image *image) lvl = &image->mt->levels[image->mtlevel]; image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset; - image->base.RowStride = lvl->rowstride / image->mt->bpp; + image->base.RowStride = lvl->rowstride / _mesa_get_format_bytes(image->base.TexFormat); } @@ -144,7 +143,6 @@ static void map_override(GLcontext *ctx, radeonTexObj *t) radeon_bo_map(t->bo, GL_FALSE); img->base.Data = t->bo->ptr; - _mesa_set_fetch_functions(&img->base, 2); } static void unmap_override(GLcontext *ctx, radeonTexObj *t) @@ -176,7 +174,7 @@ void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj) radeon_bo_map(t->mt->bo, GL_FALSE); for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + for(level = t->minLod; level <= t->maxLod; ++level) teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level])); } } @@ -193,7 +191,7 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj) return; for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) + for(level = t->minLod; level <= t->maxLod; ++level) texObj->Image[face][level]->Data = 0; } radeon_bo_unmap(t->mt->bo); @@ -242,8 +240,7 @@ static void radeon_generate_mipmap(GLcontext *ctx, GLenum target, image->mtlevel = i; image->mtface = face; - radeon_miptree_unreference(image->mt); - image->mt = NULL; + radeon_miptree_unreference(&image->mt); } } @@ -261,9 +258,9 @@ void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_objec /* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, - GLenum srcFormat, - GLenum srcType, GLboolean fbo) +static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, + GLenum srcFormat, + GLenum srcType, GLboolean fbo) { const GLuint ui = 1; const GLubyte littleEndian = *((const GLubyte *)&ui); @@ -276,37 +273,37 @@ static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPt (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { - return &_mesa_texformat_rgba8888; + return MESA_FORMAT_RGBA8888; } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { - return &_mesa_texformat_rgba8888_rev; + return MESA_FORMAT_RGBA8888_REV; } else if (IS_R200_CLASS(rmesa->radeonScreen)) { return _dri_texformat_argb8888; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8)) { - return &_mesa_texformat_argb8888_rev; + return MESA_FORMAT_ARGB8888_REV; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else return _dri_texformat_argb8888; } -const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type) +gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type) { return radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); } -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type, GLboolean fbo) +gl_format radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); const GLboolean do32bpt = @@ -430,50 +427,50 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; + return MESA_FORMAT_ALPHA_FLOAT16; case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; + return MESA_FORMAT_ALPHA_FLOAT32; case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; + return MESA_FORMAT_LUMINANCE_FLOAT16; case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; + return MESA_FORMAT_LUMINANCE_FLOAT32; case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16; case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32; case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; + return MESA_FORMAT_INTENSITY_FLOAT16; case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; + return MESA_FORMAT_INTENSITY_FLOAT32; case GL_RGB16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGB32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT16: @@ -481,7 +478,7 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_DEPTH_COMPONENT32: case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; /* EXT_texture_sRGB */ case GL_SRGB: @@ -490,26 +487,190 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_SRGB8_ALPHA8: case GL_COMPRESSED_SRGB: case GL_COMPRESSED_SRGB_ALPHA: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case GL_SLUMINANCE: case GL_SLUMINANCE8: case GL_COMPRESSED_SLUMINANCE: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_SLUMINANCE_ALPHA: case GL_SLUMINANCE8_ALPHA8: case GL_COMPRESSED_SLUMINANCE_ALPHA: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; default: _mesa_problem(ctx, "unexpected internalFormat 0x%x in %s", (int)internalFormat, __func__); + return MESA_FORMAT_NONE; + } + + return MESA_FORMAT_NONE; /* never get here */ +} + +/** Check if given image is valid within current texture object. + */ +static int image_matches_texture_obj(struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + unsigned level) +{ + const struct gl_texture_image *baseImage = texObj->Image[0][level]; + + if (level < texObj->BaseLevel || level > texObj->MaxLevel) + return 0; + + const unsigned levelDiff = level - texObj->BaseLevel; + const unsigned refWidth = baseImage->Width >> levelDiff; + const unsigned refHeight = baseImage->Height >> levelDiff; + const unsigned refDepth = baseImage->Depth >> levelDiff; + + return (texImage->Width == refWidth && + texImage->Height == refHeight && + texImage->Depth == refDepth); +} + +static void teximage_assign_miptree(radeonContextPtr rmesa, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + unsigned face, + unsigned level) +{ + radeonTexObj *t = radeon_tex_obj(texObj); + radeon_texture_image* image = get_radeon_texture_image(texImage); + + /* Since miptree holds only images for levels <BaseLevel..MaxLevel> + * don't allocate the miptree if the teximage won't fit. + */ + if (!image_matches_texture_obj(texObj, texImage, level)) + return; + + /* Try using current miptree, or create new if there isn't any */ + if (!t->mt || !radeon_miptree_matches_image(t->mt, texImage, face, level)) { + radeon_miptree_unreference(&t->mt); + radeon_try_alloc_miptree(rmesa, t); + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "%s: texObj %p, texImage %p, face %d, level %d, " + "texObj miptree doesn't match, allocated new miptree %p\n", + __FUNCTION__, texObj, texImage, face, level, t->mt); + } + } + + /* Miptree alocation may have failed, + * when there was no image for baselevel specified */ + if (t->mt) { + image->mtface = face; + image->mtlevel = level; + radeon_miptree_reference(t->mt, &image->mt); + } +} + +static GLuint * allocate_image_offsets(GLcontext *ctx, + unsigned alignedWidth, + unsigned height, + unsigned depth) +{ + int i; + GLuint *offsets; + + offsets = _mesa_malloc(depth * sizeof(GLuint)) ; + if (!offsets) { + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTex[Sub]Image"); return NULL; } - return NULL; /* never get here */ + for (i = 0; i < depth; ++i) { + offsets[i] = alignedWidth * height * i; + } + + return offsets; +} + +/** + * Update a subregion of the given texture image. + */ +static void radeon_store_teximage(GLcontext* ctx, int dims, + GLint xoffset, GLint yoffset, GLint zoffset, + GLsizei width, GLsizei height, GLsizei depth, + GLsizei imageSize, + GLenum format, GLenum type, + const GLvoid * pixels, + const struct gl_pixelstore_attrib *packing, + struct gl_texture_object *texObj, + struct gl_texture_image *texImage, + int compressed) +{ + radeonTexObj *t = radeon_tex_obj(texObj); + radeon_texture_image* image = get_radeon_texture_image(texImage); + + GLuint dstRowStride; + GLuint *dstImageOffsets; + + if (image->mt) { + dstRowStride = image->mt->levels[image->mtlevel].rowstride; + } else if (t->bo) { + /* TFP case */ + /* TODO */ + assert(0); + } else { + dstRowStride = _mesa_format_row_stride(texImage->TexFormat, texImage->Width); + } + + assert(dstRowStride); + + if (dims == 3) { + unsigned alignedWidth = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat); + dstImageOffsets = allocate_image_offsets(ctx, alignedWidth, texImage->Height, texImage->Depth); + if (!dstImageOffsets) { + return; + } + } else { + dstImageOffsets = texImage->ImageOffsets; + } + + radeon_teximage_map(image, GL_TRUE); + + if (compressed) { + uint32_t srcRowStride, bytesPerRow, rows, block_width, block_height; + GLubyte *img_start; + + _mesa_get_format_block_size(texImage->TexFormat, &block_width, &block_height); + + if (!image->mt) { + dstRowStride = _mesa_format_row_stride(texImage->TexFormat, texImage->Width); + img_start = _mesa_compressed_image_address(xoffset, yoffset, 0, + texImage->TexFormat, + texImage->Width, texImage->Data); + } + else { + uint32_t offset; + offset = dstRowStride / _mesa_get_format_bytes(texImage->TexFormat) * yoffset / block_height + xoffset / block_width; + offset *= _mesa_get_format_bytes(texImage->TexFormat); + img_start = texImage->Data + offset; + } + srcRowStride = _mesa_format_row_stride(texImage->TexFormat, width); + bytesPerRow = srcRowStride; + rows = (height + block_height - 1) / block_height; + + copy_rows(img_start, dstRowStride, pixels, srcRowStride, rows, bytesPerRow); + } + else { + if (!_mesa_texstore(ctx, dims, texImage->_BaseFormat, + texImage->TexFormat, texImage->Data, + xoffset, yoffset, zoffset, + dstRowStride, + dstImageOffsets, + width, height, depth, + format, type, pixels, packing)) { + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); + } + } + + if (dims == 3) { + _mesa_free(dstImageOffsets); + } + + radeon_teximage_unmap(image); } /** @@ -530,13 +691,22 @@ static void radeon_teximage( radeonContextPtr rmesa = RADEON_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); - GLuint dstRowStride; GLint postConvWidth = width; GLint postConvHeight = height; - GLuint texelBytes; GLuint face = radeon_face_for_target(target); - radeon_firevertices(rmesa); + { + struct radeon_bo *bo; + bo = !image->mt ? image->bo : image->mt->bo; + if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) { + radeon_firevertices(rmesa); + } + } + + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "radeon_teximage%dd: texObj %p, texImage %p, face %d, level %d\n", + dims, texObj, texImage, face, level); + } t->validated = GL_FALSE; @@ -545,62 +715,35 @@ static void radeon_teximage( &postConvHeight); } - /* Choose and fill in the texture format for this image */ - texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); - _mesa_set_fetch_functions(texImage, dims); - - if (texImage->TexFormat->TexelBytes == 0) { - texelBytes = 0; - texImage->IsCompressed = GL_TRUE; - texImage->CompressedSize = - ctx->Driver.CompressedTextureSize(ctx, texImage->Width, - texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); - } else { - texImage->IsCompressed = GL_FALSE; - texImage->CompressedSize = 0; - - texelBytes = texImage->TexFormat->TexelBytes; + if (!_mesa_is_format_compressed(texImage->TexFormat)) { + GLuint texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { - postConvWidth = 32 / texelBytes; - texImage->RowStride = postConvWidth; + postConvWidth = 32 / texelBytes; + texImage->RowStride = postConvWidth; } - if (!image->mt) { + if (!image->mt) { assert(texImage->RowStride == postConvWidth); } } - /* Allocate memory for image */ - radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */ - - if (t->mt && - t->mt->firstLevel == level && - t->mt->lastLevel == level && - t->mt->target != GL_TEXTURE_CUBE_MAP_ARB && - !radeon_miptree_matches_image(t->mt, texImage, face, level)) { - radeon_miptree_unreference(t->mt); - t->mt = NULL; - } - - if (!t->mt) - radeon_try_alloc_miptree(rmesa, t, image, face, level); - if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) { - radeon_mipmap_level *lvl; - image->mt = t->mt; - image->mtlevel = level - t->mt->firstLevel; - image->mtface = face; - radeon_miptree_reference(t->mt); - lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - int size; - if (texImage->IsCompressed) { - size = texImage->CompressedSize; - } else { - size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes; + /* Mesa core only clears texImage->Data but not image->mt */ + radeonFreeTexImageData(ctx, texImage); + + if (!t->bo) { + teximage_assign_miptree(rmesa, texObj, texImage, face, level); + if (!image->mt) { + int size = _mesa_format_image_size(texImage->TexFormat, + texImage->Width, + texImage->Height, + texImage->Depth); + texImage->Data = _mesa_alloc_texmemory(size); + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "radeon_teximage%dd: texObj %p, texImage %p, " + " no miptree assigned, using local memory %p\n", + dims, texObj, texImage, texImage->Data); + } } - texImage->Data = _mesa_alloc_texmemory(size); } /* Upload texture image; note that the spec allows pixels to be NULL */ @@ -614,64 +757,16 @@ static void radeon_teximage( } if (pixels) { - radeon_teximage_map(image, GL_TRUE); - if (compressed) { - if (image->mt) { - uint32_t srcRowStride, bytesPerRow, rows; - srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); - bytesPerRow = srcRowStride; - rows = (height + 3) / 4; - copy_rows(texImage->Data, image->mt->levels[level].rowstride, - pixels, srcRowStride, rows, bytesPerRow); - } else { - memcpy(texImage->Data, pixels, imageSize); - } - } else { - GLuint dstRowStride; - GLuint *dstImageOffsets; - - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes; - } - - if (dims == 3) { - int i; - - dstImageOffsets = _mesa_malloc(depth * sizeof(GLuint)) ; - if (!dstImageOffsets) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); - - for (i = 0; i < depth; ++i) { - dstImageOffsets[i] = dstRowStride/texImage->TexFormat->TexelBytes * height * i; - } - } else { - dstImageOffsets = texImage->ImageOffsets; - } - - if (!texImage->TexFormat->StoreImage(ctx, dims, - texImage->_BaseFormat, - texImage->TexFormat, - texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */ - dstRowStride, - dstImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); - - if (dims == 3) - _mesa_free(dstImageOffsets); - } + radeon_store_teximage(ctx, dims, + 0, 0, 0, + width, height, depth, + imageSize, format, type, + pixels, packing, + texObj, texImage, + compressed); } _mesa_unmap_teximage_pbo(ctx, packing); - - if (pixels) - radeon_teximage_unmap(image); - - } void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, @@ -724,7 +819,7 @@ void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level, } /** - * Update a subregion of the given texture image. + * All glTexSubImage calls go through this function. */ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int level, GLint xoffset, GLint yoffset, GLint zoffset, @@ -741,64 +836,39 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int leve radeonTexObj* t = radeon_tex_obj(texObj); radeon_texture_image* image = get_radeon_texture_image(texImage); - radeon_firevertices(rmesa); + { + struct radeon_bo *bo; + bo = !image->mt ? image->bo : image->mt->bo; + if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) { + radeon_firevertices(rmesa); + } + } + + if (RADEON_DEBUG & RADEON_TEXTURE) { + fprintf(stderr, "radeon_texsubimage%dd: texObj %p, texImage %p, face %d, level %d\n", + dims, texObj, texImage, radeon_face_for_target(target), level); + } t->validated = GL_FALSE; if (compressed) { pixels = _mesa_validate_pbo_compressed_teximage( - ctx, imageSize, pixels, packing, "glCompressedTexImage"); + ctx, imageSize, pixels, packing, "glCompressedTexSubImage"); } else { pixels = _mesa_validate_pbo_teximage(ctx, dims, - width, height, depth, format, type, pixels, packing, "glTexSubImage1D"); + width, height, depth, format, type, pixels, packing, "glTexSubImage"); } if (pixels) { - GLint dstRowStride; - radeon_teximage_map(image, GL_TRUE); - - if (image->mt) { - radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; - dstRowStride = lvl->rowstride; - } else { - dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes; - } - - if (compressed) { - uint32_t srcRowStride, bytesPerRow, rows; - GLubyte *img_start; - if (!image->mt) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width); - img_start = _mesa_compressed_image_address(xoffset, yoffset, 0, - texImage->TexFormat->MesaFormat, - texImage->Width, texImage->Data); - } - else { - uint32_t blocks_x = dstRowStride / (image->mt->bpp * 4); - img_start = texImage->Data + image->mt->bpp * 4 * (blocks_x * (yoffset / 4) + xoffset / 4); - } - srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); - bytesPerRow = srcRowStride; - rows = (height + 3) / 4; - - copy_rows(img_start, dstRowStride, pixels, srcRowStride, rows, bytesPerRow); - - } else { - if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat, - texImage->TexFormat, texImage->Data, - xoffset, yoffset, zoffset, - dstRowStride, - texImage->ImageOffsets, - width, height, depth, - format, type, pixels, packing)) - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage"); - } + radeon_store_teximage(ctx, dims, + xoffset, yoffset, zoffset, + width, height, depth, + imageSize, format, type, + pixels, packing, + texObj, texImage, + compressed); } - radeon_teximage_unmap(image); - _mesa_unmap_teximage_pbo(ctx, packing); - - } void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level, @@ -854,143 +924,6 @@ void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level, format, type, pixels, packing, texObj, texImage, 0); } - - -/** - * Ensure that the given image is stored in the given miptree from now on. - */ -static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level) -{ - radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel]; - unsigned char *dest; - - assert(image->mt != mt); - assert(dstlvl->width == image->base.Width); - assert(dstlvl->height == image->base.Height); - assert(dstlvl->depth == image->base.Depth); - - - radeon_bo_map(mt->bo, GL_TRUE); - dest = mt->bo->ptr + dstlvl->faces[face].offset; - - if (image->mt) { - /* Format etc. should match, so we really just need a memcpy(). - * In fact, that memcpy() could be done by the hardware in many - * cases, provided that we have a proper memory manager. - */ - radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel-image->mt->firstLevel]; - - assert(srclvl->size == dstlvl->size); - assert(srclvl->rowstride == dstlvl->rowstride); - - radeon_bo_map(image->mt->bo, GL_FALSE); - - memcpy(dest, - image->mt->bo->ptr + srclvl->faces[face].offset, - dstlvl->size); - radeon_bo_unmap(image->mt->bo); - - radeon_miptree_unreference(image->mt); - } else { - uint32_t srcrowstride; - uint32_t height; - /* need to confirm this value is correct */ - if (mt->compressed) { - height = (image->base.Height + 3) / 4; - srcrowstride = _mesa_compressed_row_stride(image->base.TexFormat->MesaFormat, image->base.Width); - } else { - height = image->base.Height * image->base.Depth; - srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes; - } - -// if (mt->tilebits) -// WARN_ONCE("%s: tiling not supported yet", __FUNCTION__); - - copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, - height, srcrowstride); - - _mesa_free_texmemory(image->base.Data); - image->base.Data = 0; - } - - radeon_bo_unmap(mt->bo); - - image->mt = mt; - image->mtface = face; - image->mtlevel = level; - radeon_miptree_reference(image->mt); -} - -int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) -{ - radeonContextPtr rmesa = RADEON_CONTEXT(ctx); - radeonTexObj *t = radeon_tex_obj(texObj); - radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]); - int face, level; - - if (t->validated || t->image_override) - return GL_TRUE; - - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj); - - if (baseimage->base.Border > 0) - return GL_FALSE; - - /* Ensure a matching miptree exists. - * - * Differing mipmap trees can result when the app uses TexImage to - * change texture dimensions. - * - * Prefer to use base image's miptree if it - * exists, since that most likely contains more valid data (remember - * that the base level is usually significantly larger than the rest - * of the miptree, so cubemaps are the only possible exception). - */ - if (baseimage->mt && - baseimage->mt != t->mt && - radeon_miptree_matches_texture(baseimage->mt, &t->base)) { - radeon_miptree_unreference(t->mt); - t->mt = baseimage->mt; - radeon_miptree_reference(t->mt); - } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) { - radeon_miptree_unreference(t->mt); - t->mt = 0; - } - - if (!t->mt) { - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, " Allocate new miptree\n"); - radeon_try_alloc_miptree(rmesa, t, baseimage, 0, texObj->BaseLevel); - if (!t->mt) { - _mesa_problem(ctx, "radeon_validate_texture failed to alloc miptree"); - return GL_FALSE; - } - } - - /* Ensure all images are stored in the single main miptree */ - for(face = 0; face < t->mt->faces; ++face) { - for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) { - radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]); - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, " face %i, level %i... %p vs %p ", face, level, t->mt, image->mt); - if (t->mt == image->mt || (!image->mt && !image->base.Data)) { - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, "OK\n"); - - continue; - } - - if (RADEON_DEBUG & RADEON_TEXTURE) - fprintf(stderr, "migrating\n"); - migrate_image_to_miptree(t->mt, image, face, level); - } - } - - return GL_TRUE; -} - - /** * Need to map texture image into memory before copying image data, * then unmap it. diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h index 888a55ba911..906daf12d0a 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.h +++ b/src/mesa/drivers/dri/radeon/radeon_texture.h @@ -30,6 +30,11 @@ #ifndef RADEON_TEXTURE_H #define RADEON_TEXTURE_H + +#include "main/formats.h" + +void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride, + GLuint numrows, GLuint rowsize); struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx); void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage); @@ -40,14 +45,16 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); GLuint radeon_face_for_target(GLenum target); -const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type); -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type, GLboolean fbo); + +gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type); + +gl_format radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo); void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, GLint internalFormat, |