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path: root/src/mesa/drivers/dri/i965/brw_eu_emit.c
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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu_emit.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6b97f8b170c..0bfbec9d140 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -513,6 +513,8 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.predicate_control = BRW_PREDICATE_NORMAL;
insn->header.mask_control = BRW_MASK_ENABLE;
+ if (!p->single_program_flow)
+ insn->header.thread_control = BRW_THREAD_SWITCH;
p->current->header.predicate_control = BRW_PREDICATE_NONE;
@@ -538,6 +540,8 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = if_insn->header.execution_size;
insn->header.mask_control = BRW_MASK_ENABLE;
+ if (!p->single_program_flow)
+ insn->header.thread_control = BRW_THREAD_SWITCH;
/* Patch the if instruction to point at this instruction.
*/
@@ -579,6 +583,7 @@ void brw_ENDIF(struct brw_compile *p,
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = patch_insn->header.execution_size;
insn->header.mask_control = BRW_MASK_ENABLE;
+ insn->header.thread_control = BRW_THREAD_SWITCH;
assert(patch_insn->bits3.if_else.jump_count == 0);
@@ -617,7 +622,7 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p)
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
insn->bits3.if_else.pad0 = 0;
return insn;
}
@@ -631,7 +636,7 @@ struct brw_instruction *brw_CONT(struct brw_compile *p)
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
insn->bits3.if_else.pad0 = 0;
return insn;
}
@@ -655,7 +660,7 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
insn->header.execution_size = execute_size;
insn->header.predicate_control = BRW_PREDICATE_NONE;
/* insn->header.mask_control = BRW_MASK_ENABLE; */
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
return insn;
}
@@ -694,7 +699,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
/* insn->header.mask_control = BRW_MASK_ENABLE; */
- insn->header.mask_control = BRW_MASK_DISABLE;
+ /* insn->header.mask_control = BRW_MASK_DISABLE; */
p->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}