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-rw-r--r--src/gallium/drivers/r600/r600_llvm.c10
-rw-r--r--src/gallium/drivers/radeon/AMDGPU.h1
-rw-r--r--src/gallium/drivers/radeon/AMDGPUInstructions.td7
-rw-r--r--src/gallium/drivers/radeon/AMDGPUIntrinsics.td3
-rw-r--r--src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp1
-rw-r--r--src/gallium/drivers/radeon/AMDGPUUtil.cpp1
-rw-r--r--src/gallium/drivers/radeon/Makefile.sources1
-rw-r--r--src/gallium/drivers/radeon/R600ISelLowering.cpp5
-rw-r--r--src/gallium/drivers/radeon/R600Instructions.td6
-rw-r--r--src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp90
10 files changed, 8 insertions, 117 deletions
diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c
index b01cb7a161d..f916604db7b 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -115,7 +115,6 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
unsigned chan;
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
LLVMValueRef output;
- LLVMValueRef store_output;
unsigned adjusted_reg_idx = i +
ctx->reserved_reg_count;
LLVMValueRef reg_index = lp_build_const_int32(
@@ -125,16 +124,11 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
output = LLVMBuildLoad(base->gallivm->builder,
ctx->soa.outputs[i][chan], "");
- store_output = lp_build_intrinsic_binary(
+ lp_build_intrinsic_binary(
base->gallivm->builder,
"llvm.AMDGPU.store.output",
- base->elem_type,
- output, reg_index);
-
- lp_build_intrinsic_unary(base->gallivm->builder,
- "llvm.AMDGPU.export.reg",
LLVMVoidTypeInContext(base->gallivm->context),
- store_output);
+ output, reg_index);
}
}
}
diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index babcf6e8a4c..7aeb3a8e625 100644
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -23,7 +23,6 @@ namespace llvm {
class AMDGPUTargetMachine;
FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
- FunctionPass *createR600LowerShaderInstructionsPass(TargetMachine &tm);
FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index a5ac9cdd409..ec7175a6510 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -35,13 +35,6 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
let isCodeGenOnly = 1 in {
- def EXPORT_REG : AMDGPUShaderInst <
- (outs),
- (ins GPRF32:$src),
- "EXPORT_REG $src",
- [(int_AMDGPU_export_reg GPRF32:$src)]
- >;
-
def MASK_WRITE : AMDGPUShaderInst <
(outs),
(ins GPRF32:$src),
diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index 09bddb58e17..b2aeaee4121 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -13,11 +13,10 @@
let TargetPrefix = "AMDGPU", isTarget = 1 in {
- def int_AMDGPU_export_reg : Intrinsic<[], [llvm_float_ty], []>;
def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], []>;
def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], []>;
def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], []>;
- def int_AMDGPU_store_output : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_i32_ty], []>;
+ def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], []>;
def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], []>;
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index 4f650dbaa46..5621d58e0d3 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -128,7 +128,6 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
- PM->add(createR600LowerShaderInstructionsPass(*TM));
PM->add(createR600LowerInstructionsPass(*TM));
} else {
PM->add(createSILowerShaderInstructionsPass(*TM));
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index 2d15e21ce36..f53800d9c73 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -30,7 +30,6 @@ bool llvm::isPlaceHolderOpcode(unsigned opcode)
{
switch (opcode) {
default: return false;
- case AMDIL::EXPORT_REG:
case AMDIL::RETURN:
case AMDIL::LOAD_INPUT:
case AMDIL::LAST:
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index a1fafbbb685..b2e70939eeb 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -50,7 +50,6 @@ CPP_SOURCES := \
R600InstrInfo.cpp \
R600KernelParameters.cpp \
R600LowerInstructions.cpp \
- R600LowerShaderInstructions.cpp \
R600MachineFunctionInfo.cpp \
R600RegisterInfo.cpp \
SIAssignInterpRegs.cpp \
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 7e1c17dfcaf..bee59cc0d7b 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -100,13 +100,12 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
case AMDIL::STORE_OUTPUT:
{
MachineBasicBlock::iterator I = *MI;
- int64_t OutputIndex = MI->getOperand(2).getImm();
+ int64_t OutputIndex = MI->getOperand(1).getImm();
unsigned OutputReg = AMDIL::R600_TReg32RegClass.getRegister(OutputIndex);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::COPY), OutputReg)
- .addOperand(MI->getOperand(1));
+ .addOperand(MI->getOperand(0));
- MRI.replaceRegWith(MI->getOperand(0).getReg(), OutputReg);
if (!MRI.isLiveOut(OutputReg)) {
MRI.addLiveOut(OutputReg);
}
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index a9d04db9ad9..fce5f90b66f 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -1006,10 +1006,10 @@ def RESERVE_REG : AMDGPUShaderInst <
>;
def STORE_OUTPUT: AMDGPUShaderInst <
- (outs R600_Reg32:$dst),
+ (outs),
(ins R600_Reg32:$src0, i32imm:$src1),
- "STORE_OUTPUT $dst, $src0, $src1",
- [(set R600_Reg32:$dst, (int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1))]
+ "STORE_OUTPUT $src0, $src1",
+ [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
>;
} // End usesCustomInserter = 1, isPseudo = 1
diff --git a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
deleted file mode 100644
index edbc6f7a4e6..00000000000
--- a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//===-- R600LowerShaderInstructions.cpp - TODO: Add brief description -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "AMDGPUUtil.h"
-#include "AMDIL.h"
-#include "AMDILInstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-using namespace llvm;
-
-namespace {
- class R600LowerShaderInstructionsPass : public MachineFunctionPass {
-
- private:
- static char ID;
- TargetMachine &TM;
- MachineRegisterInfo * MRI;
-
- void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I);
-
- public:
- R600LowerShaderInstructionsPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
-
- bool runOnMachineFunction(MachineFunction &MF);
-
- const char *getPassName() const { return "R600 Lower Shader Instructions"; }
- };
-} /* End anonymous namespace */
-
-char R600LowerShaderInstructionsPass::ID = 0;
-
-FunctionPass *llvm::createR600LowerShaderInstructionsPass(TargetMachine &tm) {
- return new R600LowerShaderInstructionsPass(tm);
-}
-
-#define INSTR_CASE_FLOAT_V(inst) \
- case AMDIL:: inst##_v4f32: \
-
-#define INSTR_CASE_FLOAT_S(inst) \
- case AMDIL:: inst##_f32:
-
-#define INSTR_CASE_FLOAT(inst) \
- INSTR_CASE_FLOAT_V(inst) \
- INSTR_CASE_FLOAT_S(inst)
-bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
-{
- MRI = &MF.getRegInfo();
-
-
- for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
- BB != BB_E; ++BB) {
- MachineBasicBlock &MBB = *BB;
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end();) {
- MachineInstr &MI = *I;
- bool deleteInstr = false;
- switch (MI.getOpcode()) {
-
- default: break;
-
- case AMDIL::EXPORT_REG:
- deleteInstr = true;
- break;
-
- }
-
- ++I;
-
- if (deleteInstr) {
- MI.eraseFromParent();
- }
- }
- }
-
- return false;
-}
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-17 12:33:54 +0000