diff options
Diffstat (limited to 'src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c b/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c new file mode 100644 index 00000000000..a1d5a964a75 --- /dev/null +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c @@ -0,0 +1,107 @@ +/************************************************************************** + * + * Copyright 2020 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#include <stdio.h> + +#include "pipe/p_video_codec.h" + +#include "util/u_video.h" + +#include "si_pipe.h" +#include "radeon_video.h" +#include "radeon_vcn_enc.h" + +#define RENCODE_FW_INTERFACE_MAJOR_VERSION 0 +#define RENCODE_FW_INTERFACE_MINOR_VERSION 0 + +static void radeon_enc_spec_misc(struct radeon_encoder *enc) +{ + enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0; + enc->enc_pic.spec_misc.cabac_enable = 0; + enc->enc_pic.spec_misc.cabac_init_idc = 0; + enc->enc_pic.spec_misc.half_pel_enabled = 1; + enc->enc_pic.spec_misc.quarter_pel_enabled = 1; + enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile); + enc->enc_pic.spec_misc.level_idc = enc->base.level; + enc->enc_pic.spec_misc.b_picture_enabled = 0; + enc->enc_pic.spec_misc.weighted_bipred_idc = 0; + + RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264); + RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag); + RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable); + RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc); + RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled); + RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled); + RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc); + RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc); + RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled); + RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc); + RADEON_ENC_END(); +} + +static void radeon_enc_encode_params_h264(struct radeon_encoder *enc) +{ + enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; + enc->enc_pic.h264_enc_params.input_pic_order_cnt = 0; + enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE; + enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xFFFFFFFF; + enc->enc_pic.h264_enc_params.l1_reference_picture0_index= 0xFFFFFFFF; + + RADEON_ENC_BEGIN(enc->cmd.enc_params_h264); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_type); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.is_long_term); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.picture_structure); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_order_cnt); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l0_reference_picture1_index); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_type); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.is_long_term); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.picture_structure); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_order_cnt); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l1_reference_picture0_index); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_type); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.is_long_term); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.picture_structure); + RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_order_cnt); + RADEON_ENC_END(); +} + +void radeon_enc_3_0_init(struct radeon_encoder *enc) +{ + radeon_enc_2_0_init(enc); + + if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) { + enc->spec_misc = radeon_enc_spec_misc; + enc->encode_params_codec_spec = radeon_enc_encode_params_h264; + } + + enc->enc_pic.session_info.interface_version = + ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) | + (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT)); +} |