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path: root/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
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Diffstat (limited to 'src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c')
-rw-r--r--src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 8302e3ffb3b..5f2400b9a9d 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -982,10 +982,15 @@ static void radeon_enc_encode_params(struct radeon_encoder *enc)
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
}
+ if (enc->luma->meta_offset) {
+ RVID_ERR("DCC surfaces not supported.\n");
+ return;
+ }
+
enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
- enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
+ enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
@@ -1027,10 +1032,15 @@ static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
}
+ if (enc->luma->meta_offset) {
+ RVID_ERR("DCC surfaces not supported.\n");
+ return;
+ }
+
enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
- enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
+ enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;