diff options
Diffstat (limited to 'src/gallium/drivers/ilo/genhw/gen_render_media.xml.h')
| -rw-r--r-- | src/gallium/drivers/ilo/genhw/gen_render_media.xml.h | 175 |
1 files changed, 131 insertions, 44 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h index 3590c795a38..55d830bad32 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h @@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository https://github.com/olvaffe/envytools/ git clone https://github.com/olvaffe/envytools.git -Copyright (C) 2014 by the following authors: +Copyright (C) 2014-2015 by the following authors: - Chia-I Wu <olvaffe@gmail.com> (olv) Permission is hereby granted, free of charge, to any person obtaining @@ -45,15 +45,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_IDRT_DW1_MASK_STACK_EXCEPTION (0x1 << 11) #define GEN6_IDRT_DW1_SOFTWARE_EXCEPTION (0x1 << 7) +#define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK 0x0000001c +#define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT 2 #define GEN6_IDRT_DW2_SAMPLER_ADDR__MASK 0xffffffe0 #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHIFT 5 #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHR 5 -#define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK 0x0000001c -#define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT 2 -#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__MASK 0x0000ffe0 -#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__SHIFT 5 -#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__SHR 5 #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__MASK 0x0000001f #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT 0 @@ -85,16 +82,61 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0 -#define GEN6_MEDIA_VFE_STATE__SIZE 8 + +#define GEN8_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN8_IDRT_DW0_KERNEL_ADDR__SHIFT 6 +#define GEN8_IDRT_DW0_KERNEL_ADDR__SHR 6 + + +#define GEN8_IDRT_DW2_THREAD_PREEMPTION_DISABLE (0x1 << 20) +#define GEN8_IDRT_DW2_DENORM__MASK 0x00080000 +#define GEN8_IDRT_DW2_DENORM__SHIFT 19 +#define GEN8_IDRT_DW2_DENORM_FTZ (0x0 << 19) +#define GEN8_IDRT_DW2_DENORM_RET (0x1 << 19) +#define GEN8_IDRT_DW2_SPF (0x1 << 18) +#define GEN8_IDRT_DW2_PRIORITY_HIGH (0x1 << 17) +#define GEN8_IDRT_DW2_FP_MODE_ALT (0x1 << 16) +#define GEN8_IDRT_DW2_ILLEGAL_CODE_EXCEPTION (0x1 << 13) +#define GEN8_IDRT_DW2_MASK_STACK_EXCEPTION (0x1 << 11) +#define GEN8_IDRT_DW2_SOFTWARE_EXCEPTION (0x1 << 7) + +#define GEN8_IDRT_DW3_SAMPLER_COUNT__MASK 0x0000001c +#define GEN8_IDRT_DW3_SAMPLER_COUNT__SHIFT 2 +#define GEN8_IDRT_DW3_SAMPLER_ADDR__MASK 0xffffffe0 +#define GEN8_IDRT_DW3_SAMPLER_ADDR__SHIFT 5 +#define GEN8_IDRT_DW3_SAMPLER_ADDR__SHR 5 + +#define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__MASK 0x0000001f +#define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__SHIFT 0 + +#define GEN8_IDRT_DW5_CURBE_READ_LEN__MASK 0xffff0000 +#define GEN8_IDRT_DW5_CURBE_READ_LEN__SHIFT 16 + +#define GEN8_IDRT_DW6_ROUNDING_MODE__MASK 0x00c00000 +#define GEN8_IDRT_DW6_ROUNDING_MODE__SHIFT 22 +#define GEN8_IDRT_DW6_ROUNDING_MODE_RTNE (0x0 << 22) +#define GEN8_IDRT_DW6_ROUNDING_MODE_RU (0x1 << 22) +#define GEN8_IDRT_DW6_ROUNDING_MODE_RD (0x2 << 22) +#define GEN8_IDRT_DW6_ROUNDING_MODE_RTZ (0x3 << 22) +#define GEN8_IDRT_DW6_BARRIER_ENABLE (0x1 << 21) +#define GEN8_IDRT_DW6_SLM_SIZE__MASK 0x001f0000 +#define GEN8_IDRT_DW6_SLM_SIZE__SHIFT 16 +#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK 0x000000ff +#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__SHIFT 0 + +#define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff +#define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0 + +#define GEN6_MEDIA_VFE_STATE__SIZE 9 -#define GEN6_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 -#define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT 10 -#define GEN6_VFE_DW1_SCRATCH_ADDR__SHR 10 #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0 #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4 #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0 +#define GEN6_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 +#define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT 10 +#define GEN6_VFE_DW1_SCRATCH_ADDR__SHR 10 #define GEN6_VFE_DW2_MAX_THREADS__MASK 0xffff0000 #define GEN6_VFE_DW2_MAX_THREADS__SHIFT 16 @@ -128,39 +170,44 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_VFE_DW5_SCOREBOARD_MASK__MASK 0x000000ff #define GEN6_VFE_DW5_SCOREBOARD_MASK__SHIFT 0 -#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_Y__MASK 0xf0000000 -#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_Y__SHIFT 28 -#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_X__MASK 0x0f000000 -#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_X__SHIFT 24 -#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_Y__MASK 0x00f00000 -#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_Y__SHIFT 20 -#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_X__MASK 0x000f0000 -#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_X__SHIFT 16 -#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_Y__MASK 0x0000f000 -#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_Y__SHIFT 12 -#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_X__MASK 0x00000f00 -#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_X__SHIFT 8 -#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_Y__MASK 0x000000f0 -#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_Y__SHIFT 4 -#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_X__MASK 0x0000000f -#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_X__SHIFT 0 - -#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_Y__MASK 0xf0000000 -#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_Y__SHIFT 28 -#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_X__MASK 0x0f000000 -#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_X__SHIFT 24 -#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_Y__MASK 0x00f00000 -#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_Y__SHIFT 20 -#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_X__MASK 0x000f0000 -#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_X__SHIFT 16 -#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_Y__MASK 0x0000f000 -#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_Y__SHIFT 12 -#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_X__MASK 0x00000f00 -#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_X__SHIFT 8 -#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_Y__MASK 0x000000f0 -#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_Y__SHIFT 4 -#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_X__MASK 0x0000000f -#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_X__SHIFT 0 + + + +#define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0 +#define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4 +#define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f +#define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0 +#define GEN8_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00 +#define GEN8_VFE_DW1_SCRATCH_ADDR__SHIFT 10 +#define GEN8_VFE_DW1_SCRATCH_ADDR__SHR 10 + + +#define GEN8_VFE_DW3_MAX_THREADS__MASK 0xffff0000 +#define GEN8_VFE_DW3_MAX_THREADS__SHIFT 16 +#define GEN8_VFE_DW3_URB_ENTRY_COUNT__MASK 0x0000ff00 +#define GEN8_VFE_DW3_URB_ENTRY_COUNT__SHIFT 8 +#define GEN8_VFE_DW3_RESET_GATEWAY_TIMER (0x1 << 7) +#define GEN8_VFE_DW3_BYPASS_GATEWAY_CONTROL (0x1 << 6) + +#define GEN8_VFE_DW4_HALF_SLICE_DISABLE__MASK 0x00000003 +#define GEN8_VFE_DW4_HALF_SLICE_DISABLE__SHIFT 0 +#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_NONE 0x0 +#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_23 0x1 +#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_123 0x3 + +#define GEN8_VFE_DW5_URB_ENTRY_SIZE__MASK 0xffff0000 +#define GEN8_VFE_DW5_URB_ENTRY_SIZE__SHIFT 16 +#define GEN8_VFE_DW5_CURBE_SIZE__MASK 0x0000ffff +#define GEN8_VFE_DW5_CURBE_SIZE__SHIFT 0 + +#define GEN8_VFE_DW6_SCOREBOARD_ENABLE (0x1 << 31) +#define GEN8_VFE_DW6_SCOREBOARD_TYPE__MASK 0x40000000 +#define GEN8_VFE_DW6_SCOREBOARD_TYPE__SHIFT 30 +#define GEN8_VFE_DW6_SCOREBOARD_TYPE_STALLING (0x0 << 30) +#define GEN8_VFE_DW6_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30) +#define GEN8_VFE_DW6_SCOREBOARD_MASK__MASK 0x000000ff +#define GEN8_VFE_DW6_SCOREBOARD_MASK__SHIFT 0 + #define GEN6_MEDIA_CURBE_LOAD__SIZE 4 @@ -169,6 +216,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_CURBE_LOAD_DW2_LEN__MASK 0x0001ffff #define GEN6_CURBE_LOAD_DW2_LEN__SHIFT 0 +#define GEN6_CURBE_LOAD_DW3_ADDR__MASK 0xffffffe0 +#define GEN6_CURBE_LOAD_DW3_ADDR__SHIFT 5 +#define GEN6_CURBE_LOAD_DW3_ADDR__SHR 5 #define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE 4 @@ -177,6 +227,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_IDRT_LOAD_DW2_LEN__MASK 0x0001ffff #define GEN6_IDRT_LOAD_DW2_LEN__SHIFT 0 +#define GEN6_IDRT_LOAD_DW3_ADDR__MASK 0xffffffe0 +#define GEN6_IDRT_LOAD_DW3_ADDR__SHIFT 5 +#define GEN6_IDRT_LOAD_DW3_ADDR__SHR 5 #define GEN6_MEDIA_STATE_FLUSH__SIZE 2 @@ -192,7 +245,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__MASK 0x0000003f #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__SHIFT 0 -#define GEN7_GPGPU_WALKER__SIZE 11 +#define GEN7_GPGPU_WALKER__SIZE 15 #define GEN7_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) #define GEN7_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8) @@ -221,4 +274,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +#define GEN8_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) +#define GEN8_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8) + +#define GEN8_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f +#define GEN8_GPGPU_DW1_IDRT_OFFSET__SHIFT 0 + + +#define GEN8_GPGPU_DW3_INDIRECT_ADDR__MASK 0xffffffe0 +#define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHIFT 5 +#define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHR 5 + +#define GEN8_GPGPU_DW4_SIMD_SIZE__MASK 0xc0000000 +#define GEN8_GPGPU_DW4_SIMD_SIZE__SHIFT 30 +#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD8 (0x0 << 30) +#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD16 (0x1 << 30) +#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD32 (0x2 << 30) +#define GEN8_GPGPU_DW4_THREAD_MAX_Z__MASK 0x003f0000 +#define GEN8_GPGPU_DW4_THREAD_MAX_Z__SHIFT 16 +#define GEN8_GPGPU_DW4_THREAD_MAX_Y__MASK 0x00003f00 +#define GEN8_GPGPU_DW4_THREAD_MAX_Y__SHIFT 8 +#define GEN8_GPGPU_DW4_THREAD_MAX_X__MASK 0x0000003f +#define GEN8_GPGPU_DW4_THREAD_MAX_X__SHIFT 0 + + + + + + + + + + + + #endif /* GEN_RENDER_MEDIA_XML */ |