diff options
Diffstat (limited to 'src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h')
| -rw-r--r-- | src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h | 944 |
1 files changed, 711 insertions, 233 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h index 2ddc0e56a29..9de3df641c7 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h @@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository https://github.com/olvaffe/envytools/ git clone https://github.com/olvaffe/envytools.git -Copyright (C) 2014 by the following authors: +Copyright (C) 2014-2015 by the following authors: - Chia-I Wu <olvaffe@gmail.com> (olv) Permission is hereby granted, free of charge, to any person obtaining @@ -94,9 +94,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_ALIGNMENT_CC_VIEWPORT 0x20 #define GEN6_ALIGNMENT_SCISSOR_RECT 0x20 #define GEN6_ALIGNMENT_BINDING_TABLE_STATE 0x20 -#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR 0x20 +#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE 0x20 +#define GEN8_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE 0x40 #define GEN6_ALIGNMENT_SAMPLER_STATE 0x20 #define GEN6_ALIGNMENT_SURFACE_STATE 0x20 +#define GEN8_ALIGNMENT_SURFACE_STATE 0x40 #define GEN6_VFCOMP_NOSTORE 0x0 #define GEN6_VFCOMP_STORE_SRC 0x1 #define GEN6_VFCOMP_STORE_0 0x2 @@ -115,6 +117,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_INTERP_PERSPECTIVE_SAMPLE (0x1 << 2) #define GEN6_INTERP_PERSPECTIVE_CENTROID (0x1 << 1) #define GEN6_INTERP_PERSPECTIVE_PIXEL (0x1 << 0) +#define GEN6_PS_DISPATCH_32 (0x1 << 2) +#define GEN6_PS_DISPATCH_16 (0x1 << 1) +#define GEN6_PS_DISPATCH_8 (0x1 << 0) #define GEN6_THREADDISP_SPF (0x1 << 31) #define GEN6_THREADDISP_VME (0x1 << 30) #define GEN6_THREADDISP_SAMPLER_COUNT__MASK 0x38000000 @@ -148,39 +153,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE 4 -#define GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED (0x1 << 12) -#define GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED (0x1 << 9) -#define GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED (0x1 << 8) +#define GEN6_BINDING_TABLE_PTR_DW0_PS_CHANGED (0x1 << 12) +#define GEN6_BINDING_TABLE_PTR_DW0_GS_CHANGED (0x1 << 9) +#define GEN6_BINDING_TABLE_PTR_DW0_VS_CHANGED (0x1 << 8) -#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__SHIFT 5 -#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__SHR 5 -#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__SHIFT 5 -#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__SHR 5 -#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__SHIFT 5 -#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__SHR 5 #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE 4 -#define GEN6_PTR_SAMPLER_DW0_PS_CHANGED (0x1 << 12) -#define GEN6_PTR_SAMPLER_DW0_GS_CHANGED (0x1 << 9) -#define GEN6_PTR_SAMPLER_DW0_VS_CHANGED (0x1 << 8) +#define GEN6_SAMPLER_PTR_DW0_PS_CHANGED (0x1 << 12) +#define GEN6_SAMPLER_PTR_DW0_GS_CHANGED (0x1 << 9) +#define GEN6_SAMPLER_PTR_DW0_VS_CHANGED (0x1 << 8) -#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__SHIFT 5 -#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__SHR 5 +#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__MASK 0xffffffe0 +#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHIFT 5 +#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHR 5 -#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__SHIFT 5 -#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__SHR 5 +#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__MASK 0xffffffe0 +#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHIFT 5 +#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHR 5 -#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__SHIFT 5 -#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__SHR 5 +#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__MASK 0xffffffe0 +#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHIFT 5 +#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHR 5 #define GEN6_3DSTATE_URB__SIZE 3 @@ -200,42 +196,48 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_3DSTATE_URB_ANY__SIZE 2 -#define GEN7_URB_ANY_DW1_OFFSET__MASK 0x3e000000 -#define GEN7_URB_ANY_DW1_OFFSET__SHIFT 25 -#define GEN7_URB_ANY_DW1_ENTRY_SIZE__MASK 0x01ff0000 -#define GEN7_URB_ANY_DW1_ENTRY_SIZE__SHIFT 16 -#define GEN7_URB_ANY_DW1_ENTRY_COUNT__MASK 0x0000ffff -#define GEN7_URB_ANY_DW1_ENTRY_COUNT__SHIFT 0 +#define GEN7_URB_DW1_OFFSET__MASK 0x3e000000 +#define GEN7_URB_DW1_OFFSET__SHIFT 25 +#define GEN7_URB_DW1_ENTRY_SIZE__MASK 0x01ff0000 +#define GEN7_URB_DW1_ENTRY_SIZE__SHIFT 16 +#define GEN7_URB_DW1_ENTRY_COUNT__MASK 0x0000ffff +#define GEN7_URB_DW1_ENTRY_COUNT__SHIFT 0 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE 2 -#define GEN7_PCB_ALLOC_ANY_DW1_OFFSET__MASK 0x000f0000 -#define GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT 16 -#define GEN7_PCB_ALLOC_ANY_DW1_SIZE__MASK 0x0000001f -#define GEN7_PCB_ALLOC_ANY_DW1_SIZE__SHIFT 0 +#define GEN7_PCB_ALLOC_DW1_OFFSET__MASK 0x000f0000 +#define GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT 16 +#define GEN7_PCB_ALLOC_DW1_SIZE__MASK 0x0000001f +#define GEN7_PCB_ALLOC_DW1_SIZE__SHIFT 0 -#define GEN75_PCB_ALLOC_ANY_DW1_OFFSET__MASK 0x001f0000 -#define GEN75_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT 16 -#define GEN75_PCB_ALLOC_ANY_DW1_SIZE__MASK 0x0000003f -#define GEN75_PCB_ALLOC_ANY_DW1_SIZE__SHIFT 0 +#define GEN75_PCB_ALLOC_DW1_OFFSET__MASK 0x001f0000 +#define GEN75_PCB_ALLOC_DW1_OFFSET__SHIFT 16 +#define GEN75_PCB_ALLOC_DW1_SIZE__MASK 0x0000003f +#define GEN75_PCB_ALLOC_DW1_SIZE__SHIFT 0 #define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE 133 -#define GEN6_VB_STATE_DW0_INDEX__MASK 0xfc000000 -#define GEN6_VB_STATE_DW0_INDEX__SHIFT 26 -#define GEN6_VB_STATE_DW0_ACCESS__MASK 0x00100000 -#define GEN6_VB_STATE_DW0_ACCESS__SHIFT 20 -#define GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA (0x0 << 20) -#define GEN6_VB_STATE_DW0_ACCESS_INSTANCEDATA (0x1 << 20) -#define GEN6_VB_STATE_DW0_MOCS__MASK 0x000f0000 -#define GEN6_VB_STATE_DW0_MOCS__SHIFT 16 -#define GEN7_VB_STATE_DW0_ADDR_MODIFIED (0x1 << 14) -#define GEN6_VB_STATE_DW0_IS_NULL (0x1 << 13) -#define GEN6_VB_STATE_DW0_CACHE_INVALIDATE (0x1 << 12) -#define GEN6_VB_STATE_DW0_PITCH__MASK 0x00000fff -#define GEN6_VB_STATE_DW0_PITCH__SHIFT 0 + +#define GEN6_VB_DW0_INDEX__MASK 0xfc000000 +#define GEN6_VB_DW0_INDEX__SHIFT 26 +#define GEN8_VB_DW0_MOCS__MASK 0x007f0000 +#define GEN8_VB_DW0_MOCS__SHIFT 16 +#define GEN6_VB_DW0_ACCESS__MASK 0x00100000 +#define GEN6_VB_DW0_ACCESS__SHIFT 20 +#define GEN6_VB_DW0_ACCESS_VERTEXDATA (0x0 << 20) +#define GEN6_VB_DW0_ACCESS_INSTANCEDATA (0x1 << 20) +#define GEN6_VB_DW0_MOCS__MASK 0x000f0000 +#define GEN6_VB_DW0_MOCS__SHIFT 16 +#define GEN7_VB_DW0_ADDR_MODIFIED (0x1 << 14) +#define GEN6_VB_DW0_IS_NULL (0x1 << 13) +#define GEN6_VB_DW0_CACHE_INVALIDATE (0x1 << 12) +#define GEN6_VB_DW0_PITCH__MASK 0x00000fff +#define GEN6_VB_DW0_PITCH__SHIFT 0 + + + @@ -243,27 +245,28 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE 69 -#define GEN6_VE_STATE_DW0_VB_INDEX__MASK 0xfc000000 -#define GEN6_VE_STATE_DW0_VB_INDEX__SHIFT 26 -#define GEN6_VE_STATE_DW0_VALID (0x1 << 25) -#define GEN6_VE_STATE_DW0_FORMAT__MASK 0x01ff0000 -#define GEN6_VE_STATE_DW0_FORMAT__SHIFT 16 -#define GEN6_VE_STATE_DW0_EDGE_FLAG_ENABLE (0x1 << 15) -#define GEN6_VE_STATE_DW0_VB_OFFSET__MASK 0x000007ff -#define GEN6_VE_STATE_DW0_VB_OFFSET__SHIFT 0 -#define GEN75_VE_STATE_DW0_VB_OFFSET__MASK 0x00000fff -#define GEN75_VE_STATE_DW0_VB_OFFSET__SHIFT 0 - -#define GEN6_VE_STATE_DW1_COMP0__MASK 0x70000000 -#define GEN6_VE_STATE_DW1_COMP0__SHIFT 28 -#define GEN6_VE_STATE_DW1_COMP1__MASK 0x07000000 -#define GEN6_VE_STATE_DW1_COMP1__SHIFT 24 -#define GEN6_VE_STATE_DW1_COMP2__MASK 0x00700000 -#define GEN6_VE_STATE_DW1_COMP2__SHIFT 20 -#define GEN6_VE_STATE_DW1_COMP3__MASK 0x00070000 -#define GEN6_VE_STATE_DW1_COMP3__SHIFT 16 - -#define GEN6_3DSTATE_INDEX_BUFFER__SIZE 3 + +#define GEN6_VE_DW0_VB_INDEX__MASK 0xfc000000 +#define GEN6_VE_DW0_VB_INDEX__SHIFT 26 +#define GEN6_VE_DW0_VALID (0x1 << 25) +#define GEN6_VE_DW0_FORMAT__MASK 0x01ff0000 +#define GEN6_VE_DW0_FORMAT__SHIFT 16 +#define GEN6_VE_DW0_EDGE_FLAG_ENABLE (0x1 << 15) +#define GEN6_VE_DW0_VB_OFFSET__MASK 0x000007ff +#define GEN6_VE_DW0_VB_OFFSET__SHIFT 0 +#define GEN75_VE_DW0_VB_OFFSET__MASK 0x00000fff +#define GEN75_VE_DW0_VB_OFFSET__SHIFT 0 + +#define GEN6_VE_DW1_COMP0__MASK 0x70000000 +#define GEN6_VE_DW1_COMP0__SHIFT 28 +#define GEN6_VE_DW1_COMP1__MASK 0x07000000 +#define GEN6_VE_DW1_COMP1__SHIFT 24 +#define GEN6_VE_DW1_COMP2__MASK 0x00700000 +#define GEN6_VE_DW1_COMP2__SHIFT 20 +#define GEN6_VE_DW1_COMP3__MASK 0x00070000 +#define GEN6_VE_DW1_COMP3__SHIFT 16 + +#define GEN6_3DSTATE_INDEX_BUFFER__SIZE 5 #define GEN6_IB_DW0_MOCS__MASK 0x0000f000 #define GEN6_IB_DW0_MOCS__SHIFT 12 @@ -276,62 +279,100 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +#define GEN8_IB_DW1_FORMAT__MASK 0x00000300 +#define GEN8_IB_DW1_FORMAT__SHIFT 8 +#define GEN8_IB_DW1_FORMAT_BYTE (0x0 << 8) +#define GEN8_IB_DW1_FORMAT_WORD (0x1 << 8) +#define GEN8_IB_DW1_FORMAT_DWORD (0x2 << 8) +#define GEN8_IB_DW1_MOCS__MASK 0x0000007f +#define GEN8_IB_DW1_MOCS__SHIFT 0 + + + + #define GEN75_3DSTATE_VF__SIZE 2 #define GEN75_VF_DW0_CUT_INDEX_ENABLE (0x1 << 8) +#define GEN8_3DSTATE_VF_INSTANCING__SIZE 3 + + +#define GEN8_INSTANCING_DW1_ENABLE (0x1 << 8) +#define GEN8_INSTANCING_DW1_VB_INDEX__MASK 0x0000003f +#define GEN8_INSTANCING_DW1_VB_INDEX__SHIFT 0 + + +#define GEN8_3DSTATE_VF_SGVS__SIZE 2 + + +#define GEN8_SGVS_DW1_IID_ENABLE (0x1 << 31) +#define GEN8_SGVS_DW1_IID_VE_COMP__MASK 0x60000000 +#define GEN8_SGVS_DW1_IID_VE_COMP__SHIFT 29 +#define GEN8_SGVS_DW1_IID_VE_INDEX__MASK 0x003f0000 +#define GEN8_SGVS_DW1_IID_VE_INDEX__SHIFT 16 +#define GEN8_SGVS_DW1_VID_ENABLE (0x1 << 15) +#define GEN8_SGVS_DW1_VID_VE_COMP__MASK 0x00006000 +#define GEN8_SGVS_DW1_VID_VE_COMP__SHIFT 13 +#define GEN8_SGVS_DW1_VID_VE_INDEX__MASK 0x0000003f +#define GEN8_SGVS_DW1_VID_VE_INDEX__SHIFT 0 + +#define GEN8_3DSTATE_VF_TOPOLOGY__SIZE 2 + + +#define GEN8_TOPOLOGY_DW1_TYPE__MASK 0x0000003f +#define GEN8_TOPOLOGY_DW1_TYPE__SHIFT 0 + #define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE 4 -#define GEN6_PTR_VP_DW0_CC_CHANGED (0x1 << 12) -#define GEN6_PTR_VP_DW0_SF_CHANGED (0x1 << 11) -#define GEN6_PTR_VP_DW0_CLIP_CHANGED (0x1 << 10) +#define GEN6_VP_PTR_DW0_CC_CHANGED (0x1 << 12) +#define GEN6_VP_PTR_DW0_SF_CHANGED (0x1 << 11) +#define GEN6_VP_PTR_DW0_CLIP_CHANGED (0x1 << 10) -#define GEN6_PTR_VP_DW1_CLIP_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_VP_DW1_CLIP_ADDR__SHIFT 5 -#define GEN6_PTR_VP_DW1_CLIP_ADDR__SHR 5 +#define GEN6_VP_PTR_DW1_CLIP_ADDR__MASK 0xffffffe0 +#define GEN6_VP_PTR_DW1_CLIP_ADDR__SHIFT 5 +#define GEN6_VP_PTR_DW1_CLIP_ADDR__SHR 5 -#define GEN6_PTR_VP_DW2_SF_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_VP_DW2_SF_ADDR__SHIFT 5 -#define GEN6_PTR_VP_DW2_SF_ADDR__SHR 5 +#define GEN6_VP_PTR_DW2_SF_ADDR__MASK 0xffffffe0 +#define GEN6_VP_PTR_DW2_SF_ADDR__SHIFT 5 +#define GEN6_VP_PTR_DW2_SF_ADDR__SHR 5 -#define GEN6_PTR_VP_DW3_CC_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_VP_DW3_CC_ADDR__SHIFT 5 -#define GEN6_PTR_VP_DW3_CC_ADDR__SHR 5 +#define GEN6_VP_PTR_DW3_CC_ADDR__MASK 0xffffffe0 +#define GEN6_VP_PTR_DW3_CC_ADDR__SHIFT 5 +#define GEN6_VP_PTR_DW3_CC_ADDR__SHR 5 #define GEN6_3DSTATE_CC_STATE_POINTERS__SIZE 4 -#define GEN6_PTR_CC_DW1_BLEND_CHANGED (0x1 << 0) -#define GEN6_PTR_CC_DW1_BLEND_ADDR__MASK 0xffffffc0 -#define GEN6_PTR_CC_DW1_BLEND_ADDR__SHIFT 6 -#define GEN6_PTR_CC_DW1_BLEND_ADDR__SHR 6 +#define GEN6_CC_PTR_DW1_BLEND_CHANGED (0x1 << 0) +#define GEN6_CC_PTR_DW1_BLEND_ADDR__MASK 0xffffffc0 +#define GEN6_CC_PTR_DW1_BLEND_ADDR__SHIFT 6 +#define GEN6_CC_PTR_DW1_BLEND_ADDR__SHR 6 -#define GEN6_PTR_CC_DW2_ZS_CHANGED (0x1 << 0) -#define GEN6_PTR_CC_DW2_ZS_ADDR__MASK 0xffffffc0 -#define GEN6_PTR_CC_DW2_ZS_ADDR__SHIFT 6 -#define GEN6_PTR_CC_DW2_ZS_ADDR__SHR 6 +#define GEN6_CC_PTR_DW2_ZS_CHANGED (0x1 << 0) +#define GEN6_CC_PTR_DW2_ZS_ADDR__MASK 0xffffffc0 +#define GEN6_CC_PTR_DW2_ZS_ADDR__SHIFT 6 +#define GEN6_CC_PTR_DW2_ZS_ADDR__SHR 6 -#define GEN6_PTR_CC_DW3_CC_CHANGED (0x1 << 0) -#define GEN6_PTR_CC_DW3_CC_ADDR__MASK 0xffffffc0 -#define GEN6_PTR_CC_DW3_CC_ADDR__SHIFT 6 -#define GEN6_PTR_CC_DW3_CC_ADDR__SHR 6 +#define GEN6_CC_PTR_DW3_CC_CHANGED (0x1 << 0) +#define GEN6_CC_PTR_DW3_CC_ADDR__MASK 0xffffffc0 +#define GEN6_CC_PTR_DW3_CC_ADDR__SHIFT 6 +#define GEN6_CC_PTR_DW3_CC_ADDR__SHR 6 #define GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE 2 -#define GEN6_PTR_SCISSOR_DW1_ADDR__MASK 0xffffffe0 -#define GEN6_PTR_SCISSOR_DW1_ADDR__SHIFT 5 -#define GEN6_PTR_SCISSOR_DW1_ADDR__SHR 5 +#define GEN6_SCISSOR_PTR_DW1_ADDR__MASK 0xffffffe0 +#define GEN6_SCISSOR_PTR_DW1_ADDR__SHIFT 5 +#define GEN6_SCISSOR_PTR_DW1_ADDR__SHR 5 #define GEN7_3DSTATE_POINTERS_ANY__SIZE 2 -#define GEN7_PTR_ANY_DW1_ADDR__MASK 0xffffffe0 -#define GEN7_PTR_ANY_DW1_ADDR__SHIFT 5 -#define GEN7_PTR_ANY_DW1_ADDR__SHR 5 -#define GEN6_3DSTATE_VS__SIZE 6 +#define GEN6_3DSTATE_VS__SIZE 9 #define GEN6_VS_DW1_KERNEL_ADDR__MASK 0xffffffc0 @@ -355,7 +396,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_VS_DW5_CACHE_DISABLE (0x1 << 1) #define GEN6_VS_DW5_VS_ENABLE (0x1 << 0) -#define GEN7_3DSTATE_HS__SIZE 7 + + +#define GEN8_VS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN8_VS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN8_VS_DW1_KERNEL_ADDR__SHR 6 + + + + + +#define GEN8_VS_DW6_URB_GRF_START__MASK 0x01f00000 +#define GEN8_VS_DW6_URB_GRF_START__SHIFT 20 +#define GEN8_VS_DW6_URB_READ_LEN__MASK 0x0001f800 +#define GEN8_VS_DW6_URB_READ_LEN__SHIFT 11 +#define GEN8_VS_DW6_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN8_VS_DW6_URB_READ_OFFSET__SHIFT 4 + +#define GEN8_VS_DW7_MAX_THREADS__MASK 0xff800000 +#define GEN8_VS_DW7_MAX_THREADS__SHIFT 23 +#define GEN8_VS_DW7_STATISTICS (0x1 << 10) +#define GEN8_VS_DW7_SIMD8_ENABLE (0x1 << 2) +#define GEN8_VS_DW7_CACHE_DISABLE (0x1 << 1) +#define GEN8_VS_DW7_VS_ENABLE (0x1 << 0) + +#define GEN8_VS_DW8_URB_WRITE_OFFSET__MASK 0x03e00000 +#define GEN8_VS_DW8_URB_WRITE_OFFSET__SHIFT 21 +#define GEN8_VS_DW8_URB_WRITE_LEN__MASK 0x001f0000 +#define GEN8_VS_DW8_URB_WRITE_LEN__SHIFT 16 +#define GEN8_VS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00 +#define GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT 8 + +#define GEN7_3DSTATE_HS__SIZE 9 #define GEN7_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x0000007f @@ -391,6 +463,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0 #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHR 6 + + +#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__MASK 0x000000ff +#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__SHIFT 0 + +#define GEN8_HS_DW2_HS_ENABLE (0x1 << 31) +#define GEN8_HS_DW2_STATISTICS (0x1 << 29) +#define GEN8_HS_DW2_INSTANCE_COUNT__MASK 0x0000000f +#define GEN8_HS_DW2_INSTANCE_COUNT__SHIFT 0 + +#define GEN8_HS_DW3_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN8_HS_DW3_KERNEL_ADDR__SHIFT 6 +#define GEN8_HS_DW3_KERNEL_ADDR__SHR 6 + + + + +#define GEN8_HS_DW7_SPF (0x1 << 27) +#define GEN8_HS_DW7_VME (0x1 << 26) +#define GEN8_HS_DW7_ACCESS_UAV (0x1 << 25) +#define GEN8_HS_DW7_INCLUDE_VERTEX_HANDLES (0x1 << 24) +#define GEN8_HS_DW7_URB_GRF_START__MASK 0x00f80000 +#define GEN8_HS_DW7_URB_GRF_START__SHIFT 19 +#define GEN8_HS_DW7_URB_READ_LEN__MASK 0x0001f800 +#define GEN8_HS_DW7_URB_READ_LEN__SHIFT 11 +#define GEN8_HS_DW7_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN8_HS_DW7_URB_READ_OFFSET__SHIFT 4 + +#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__MASK 0x00001fff +#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHIFT 0 +#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHR 6 + #define GEN7_3DSTATE_TE__SIZE 4 @@ -418,7 +522,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -#define GEN7_3DSTATE_DS__SIZE 6 +#define GEN7_3DSTATE_DS__SIZE 11 #define GEN7_DS_DW1_KERNEL_ADDR__MASK 0xffffffc0 @@ -443,7 +547,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_DS_DW5_CACHE_DISABLE (0x1 << 1) #define GEN7_DS_DW5_DS_ENABLE (0x1 << 0) -#define GEN6_3DSTATE_GS__SIZE 7 + + +#define GEN8_DS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN8_DS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN8_DS_DW1_KERNEL_ADDR__SHR 6 + + + + + +#define GEN8_DS_DW6_URB_GRF_START__MASK 0x01f00000 +#define GEN8_DS_DW6_URB_GRF_START__SHIFT 20 +#define GEN8_DS_DW6_URB_READ_LEN__MASK 0x0003f800 +#define GEN8_DS_DW6_URB_READ_LEN__SHIFT 11 +#define GEN8_DS_DW6_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN8_DS_DW6_URB_READ_OFFSET__SHIFT 4 + +#define GEN8_DS_DW7_MAX_THREADS__MASK 0x3fe00000 +#define GEN8_DS_DW7_MAX_THREADS__SHIFT 21 +#define GEN8_DS_DW7_STATISTICS (0x1 << 10) +#define GEN8_DS_DW7_COMPUTE_W (0x1 << 2) +#define GEN8_DS_DW7_CACHE_DISABLE (0x1 << 1) +#define GEN8_DS_DW7_DS_ENABLE (0x1 << 0) + +#define GEN8_DS_DW8_URB_WRITE_OFFSET__MASK 0x03e00000 +#define GEN8_DS_DW8_URB_WRITE_OFFSET__SHIFT 21 +#define GEN8_DS_DW8_URB_WRITE_LEN__MASK 0x001f0000 +#define GEN8_DS_DW8_URB_WRITE_LEN__SHIFT 16 +#define GEN8_DS_DW8_UCP_CLIP_ENABLES__MASK 0x0000ff00 +#define GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT 8 + + + +#define GEN6_3DSTATE_GS__SIZE 10 #define GEN6_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0 @@ -536,7 +673,73 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT 0 #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHR 6 -#define GEN7_3DSTATE_STREAMOUT__SIZE 3 + + +#define GEN8_GS_DW1_KERNEL_ADDR__MASK 0xffffffc0 +#define GEN8_GS_DW1_KERNEL_ADDR__SHIFT 6 +#define GEN8_GS_DW1_KERNEL_ADDR__SHR 6 + + +#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK 0x0000007f +#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__SHIFT 0 + + + +#define GEN8_GS_DW6_OUTPUT_SIZE__MASK 0x1f800000 +#define GEN8_GS_DW6_OUTPUT_SIZE__SHIFT 23 +#define GEN8_GS_DW6_OUTPUT_TOPO__MASK 0x007e0000 +#define GEN8_GS_DW6_OUTPUT_TOPO__SHIFT 17 +#define GEN8_GS_DW6_URB_READ_LEN__MASK 0x0001f800 +#define GEN8_GS_DW6_URB_READ_LEN__SHIFT 11 +#define GEN8_GS_DW6_INCLUDE_VERTEX_HANDLES (0x1 << 10) +#define GEN8_GS_DW6_URB_READ_OFFSET__MASK 0x000003f0 +#define GEN8_GS_DW6_URB_READ_OFFSET__SHIFT 4 +#define GEN8_GS_DW6_URB_GRF_START__MASK 0x0000000f +#define GEN8_GS_DW6_URB_GRF_START__SHIFT 0 + +#define GEN8_GS_DW7_MAX_THREADS__MASK 0xff000000 +#define GEN8_GS_DW7_MAX_THREADS__SHIFT 24 +#define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__MASK 0x00f00000 +#define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__SHIFT 20 +#define GEN8_GS_DW7_INSTANCE_CONTROL__MASK 0x000f8000 +#define GEN8_GS_DW7_INSTANCE_CONTROL__SHIFT 15 +#define GEN8_GS_DW7_DEFAULT_STREAM_ID__MASK 0x00006000 +#define GEN8_GS_DW7_DEFAULT_STREAM_ID__SHIFT 13 +#define GEN8_GS_DW7_DISPATCH_MODE__MASK 0x00001800 +#define GEN8_GS_DW7_DISPATCH_MODE__SHIFT 11 +#define GEN8_GS_DW7_DISPATCH_MODE_SINGLE (0x0 << 11) +#define GEN8_GS_DW7_DISPATCH_MODE_DUAL_INSTANCE (0x1 << 11) +#define GEN8_GS_DW7_DISPATCH_MODE_DUAL_OBJECT (0x2 << 11) +#define GEN8_GS_DW7_STATISTICS (0x1 << 10) +#define GEN8_GS_DW7_INVOCATION_INCR__MASK 0x000003e0 +#define GEN8_GS_DW7_INVOCATION_INCR__SHIFT 5 +#define GEN8_GS_DW7_INCLUDE_PRIMITIVE_ID (0x1 << 4) +#define GEN8_GS_DW7_HINT (0x1 << 3) +#define GEN8_GS_DW7_REORDER__MASK 0x00000004 +#define GEN8_GS_DW7_REORDER__SHIFT 2 +#define GEN8_GS_DW7_REORDER_LEADING (0x0 << 2) +#define GEN8_GS_DW7_REORDER_TRAILING (0x1 << 2) +#define GEN8_GS_DW7_DISCARD_ADJACENCY (0x1 << 1) +#define GEN8_GS_DW7_GS_ENABLE (0x1 << 0) + +#define GEN8_GS_DW8_GSCTRL__MASK 0x80000000 +#define GEN8_GS_DW8_GSCTRL__SHIFT 31 +#define GEN8_GS_DW8_GSCTRL_CUT (0x0 << 31) +#define GEN8_GS_DW8_GSCTRL_SID (0x1 << 31) +#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__MASK 0x00001fff +#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHIFT 0 +#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHR 6 +#define GEN9_GS_DW8_MAX_THREADS__MASK 0x00001fff +#define GEN9_GS_DW8_MAX_THREADS__SHIFT 0 + +#define GEN8_GS_DW9_URB_WRITE_OFFSET__MASK 0x03e00000 +#define GEN8_GS_DW9_URB_WRITE_OFFSET__SHIFT 21 +#define GEN8_GS_DW9_URB_WRITE_LEN__MASK 0x001f0000 +#define GEN8_GS_DW9_URB_WRITE_LEN__SHIFT 16 +#define GEN8_GS_DW9_UCP_CLIP_ENABLES__MASK 0x0000ff00 +#define GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT 8 + +#define GEN7_3DSTATE_STREAMOUT__SIZE 5 #define GEN7_SO_DW1_SO_ENABLE (0x1 << 31) @@ -568,6 +771,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_SO_DW2_STREAM0_READ_LEN__MASK 0x0000001f #define GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT 0 +#define GEN8_SO_DW3_BUFFER1_PITCH__MASK 0x0fff0000 +#define GEN8_SO_DW3_BUFFER1_PITCH__SHIFT 16 +#define GEN8_SO_DW3_BUFFER0_PITCH__MASK 0x00000fff +#define GEN8_SO_DW3_BUFFER0_PITCH__SHIFT 0 + +#define GEN8_SO_DW4_BUFFER3_PITCH__MASK 0x0fff0000 +#define GEN8_SO_DW4_BUFFER3_PITCH__SHIFT 16 +#define GEN8_SO_DW4_BUFFER2_PITCH__MASK 0x00000fff +#define GEN8_SO_DW4_BUFFER2_PITCH__SHIFT 0 + #define GEN7_3DSTATE_SO_DECL_LIST__SIZE 259 @@ -599,13 +812,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_SO_DECL_COMPONENT_MASK__MASK 0x0000000f #define GEN7_SO_DECL_COMPONENT_MASK__SHIFT 0 -#define GEN7_3DSTATE_SO_BUFFER__SIZE 4 +#define GEN7_3DSTATE_SO_BUFFER__SIZE 8 +#define GEN8_SO_BUF_DW1_ENABLE (0x1 << 31) #define GEN7_SO_BUF_DW1_INDEX__MASK 0x60000000 #define GEN7_SO_BUF_DW1_INDEX__SHIFT 29 #define GEN7_SO_BUF_DW1_MOCS__MASK 0x1e000000 #define GEN7_SO_BUF_DW1_MOCS__SHIFT 25 +#define GEN8_SO_BUF_DW1_MOCS__MASK 0x1fc00000 +#define GEN8_SO_BUF_DW1_MOCS__SHIFT 22 +#define GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE (0x1 << 21) +#define GEN8_SO_BUF_DW1_OFFSET_ENABLE (0x1 << 20) #define GEN7_SO_BUF_DW1_PITCH__MASK 0x00000fff #define GEN7_SO_BUF_DW1_PITCH__SHIFT 0 @@ -617,6 +835,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_SO_BUF_DW3_END_ADDR__SHIFT 2 #define GEN7_SO_BUF_DW3_END_ADDR__SHR 2 +#define GEN8_SO_BUF_DW2_ADDR__MASK 0xfffffffc +#define GEN8_SO_BUF_DW2_ADDR__SHIFT 2 +#define GEN8_SO_BUF_DW2_ADDR__SHR 2 + + + +#define GEN8_SO_BUF_DW5_OFFSET_ADDR__MASK 0xfffffffc +#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHIFT 2 +#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHR 2 + + + #define GEN6_3DSTATE_CLIP__SIZE 4 @@ -673,10 +903,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_CLIP_DW3_MAX_VPINDEX__MASK 0x0000000f #define GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT 0 -#define GEN6_3DSTATE_SFBODY__SIZE 6 +#define GEN6_3DSTATE_SF_DW1_DW3__SIZE 3 #define GEN7_SF_DW1_DEPTH_FORMAT__MASK 0x00007000 #define GEN7_SF_DW1_DEPTH_FORMAT__SHIFT 12 +#define GEN9_SF_DW1_LINE_WIDTH__MASK 0x3ffff000 +#define GEN9_SF_DW1_LINE_WIDTH__SHIFT 12 +#define GEN9_SF_DW1_LINE_WIDTH__RADIX 7 #define GEN7_SF_DW1_LEGACY_DEPTH_OFFSET (0x1 << 11) #define GEN7_SF_DW1_STATISTICS (0x1 << 10) #define GEN7_SF_DW1_DEPTH_OFFSET_SOLID (0x1 << 9) @@ -740,11 +973,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_SF_DW3_POINT_WIDTH__SHIFT 0 #define GEN7_SF_DW3_POINT_WIDTH__RADIX 3 +#define GEN7_3DSTATE_SBE_DW1__SIZE 13 - - -#define GEN6_3DSTATE_SBEBODY__SIZE 13 - +#define GEN8_SBE_DW1_USE_URB_READ_LEN (0x1 << 29) +#define GEN8_SBE_DW1_USE_URB_READ_OFFSET (0x1 << 28) #define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK 0x10000000 #define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT 28 #define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15 (0x0 << 28) @@ -760,32 +992,49 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_SBE_DW1_URB_READ_LEN__SHIFT 11 #define GEN7_SBE_DW1_URB_READ_OFFSET__MASK 0x000003f0 #define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT 4 +#define GEN8_SBE_DW1_URB_READ_OFFSET__MASK 0x000007e0 +#define GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT 5 + +#define GEN8_3DSTATE_SBE_SWIZ_DW1_DW8__SIZE 8 + +#define GEN8_SBE_SWIZ_HIGH__MASK 0xffff0000 +#define GEN8_SBE_SWIZ_HIGH__SHIFT 16 +#define GEN8_SBE_SWIZ_OVERRIDE_W (0x1 << 15) +#define GEN8_SBE_SWIZ_OVERRIDE_Z (0x1 << 14) +#define GEN8_SBE_SWIZ_OVERRIDE_Y (0x1 << 13) +#define GEN8_SBE_SWIZ_OVERRIDE_X (0x1 << 12) +#define GEN8_SBE_SWIZ_CONST__MASK 0x00000600 +#define GEN8_SBE_SWIZ_CONST__SHIFT 9 +#define GEN8_SBE_SWIZ_CONST_0000 (0x0 << 9) +#define GEN8_SBE_SWIZ_CONST_0001_FLOAT (0x1 << 9) +#define GEN8_SBE_SWIZ_CONST_1111_FLOAT (0x2 << 9) +#define GEN8_SBE_SWIZ_CONST_PRIM_ID (0x3 << 9) +#define GEN8_SBE_SWIZ_INPUTATTR__MASK 0x000000c0 +#define GEN8_SBE_SWIZ_INPUTATTR__SHIFT 6 +#define GEN8_SBE_SWIZ_INPUTATTR_NORMAL (0x0 << 6) +#define GEN8_SBE_SWIZ_INPUTATTR_FACING (0x1 << 6) +#define GEN8_SBE_SWIZ_INPUTATTR_W (0x2 << 6) +#define GEN8_SBE_SWIZ_INPUTATTR_FACING_W (0x3 << 6) +#define GEN8_SBE_SWIZ_URB_ENTRY_OFFSET__MASK 0x0000001f +#define GEN8_SBE_SWIZ_URB_ENTRY_OFFSET__SHIFT 0 + +#define GEN6_3DSTATE_SF__SIZE 20 + + + + + + + + + + + -#define GEN7_SBE_ATTR_HIGH__MASK 0xffff0000 -#define GEN7_SBE_ATTR_HIGH__SHIFT 16 -#define GEN7_SBE_ATTR_OVERRIDE_W (0x1 << 15) -#define GEN7_SBE_ATTR_OVERRIDE_Z (0x1 << 14) -#define GEN7_SBE_ATTR_OVERRIDE_Y (0x1 << 13) -#define GEN7_SBE_ATTR_OVERRIDE_X (0x1 << 12) -#define GEN7_SBE_ATTR_CONST__MASK 0x00000600 -#define GEN7_SBE_ATTR_CONST__SHIFT 9 -#define GEN7_SBE_ATTR_CONST_0000 (0x0 << 9) -#define GEN7_SBE_ATTR_CONST_0001_FLOAT (0x1 << 9) -#define GEN7_SBE_ATTR_CONST_1111_FLOAT (0x2 << 9) -#define GEN7_SBE_ATTR_CONST_PRIM_ID (0x3 << 9) -#define GEN7_SBE_ATTR_INPUTATTR__MASK 0x000000c0 -#define GEN7_SBE_ATTR_INPUTATTR__SHIFT 6 -#define GEN7_SBE_ATTR_INPUTATTR_NORMAL (0x0 << 6) -#define GEN7_SBE_ATTR_INPUTATTR_FACING (0x1 << 6) -#define GEN7_SBE_ATTR_INPUTATTR_W (0x2 << 6) -#define GEN7_SBE_ATTR_INPUTATTR_FACING_W (0x3 << 6) -#define GEN7_SBE_ATTR_URB_ENTRY_OFFSET__MASK 0x0000001f -#define GEN7_SBE_ATTR_URB_ENTRY_OFFSET__SHIFT 0 -#define GEN6_3DSTATE_SF__SIZE 20 @@ -794,6 +1043,64 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + + + + + + + + +#define GEN9_SBE_DW_ACTIVE_COMPONENT__MASK 0x00000003 +#define GEN9_SBE_DW_ACTIVE_COMPONENT__SHIFT 0 +#define GEN9_SBE_DW_ACTIVE_COMPONENT_NONE 0x0 +#define GEN9_SBE_DW_ACTIVE_COMPONENT_XY 0x1 +#define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZ 0x2 +#define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZW 0x3 + +#define GEN8_3DSTATE_SBE_SWIZ__SIZE 11 + + + + +#define GEN8_3DSTATE_RASTER__SIZE 5 + + +#define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE (0x1 << 26) +#define GEN8_RASTER_DW1_FRONTWINDING__MASK 0x00200000 +#define GEN8_RASTER_DW1_FRONTWINDING__SHIFT 21 +#define GEN8_RASTER_DW1_FRONTWINDING_CW (0x0 << 21) +#define GEN8_RASTER_DW1_FRONTWINDING_CCW (0x1 << 21) +#define GEN8_RASTER_DW1_CULLMODE__MASK 0x00030000 +#define GEN8_RASTER_DW1_CULLMODE__SHIFT 16 +#define GEN8_RASTER_DW1_CULLMODE_BOTH (0x0 << 16) +#define GEN8_RASTER_DW1_CULLMODE_NONE (0x1 << 16) +#define GEN8_RASTER_DW1_CULLMODE_FRONT (0x2 << 16) +#define GEN8_RASTER_DW1_CULLMODE_BACK (0x3 << 16) +#define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE (0x1 << 13) +#define GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE (0x1 << 12) +#define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID (0x1 << 9) +#define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME (0x1 << 8) +#define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT (0x1 << 7) +#define GEN8_RASTER_DW1_FRONTFACE__MASK 0x00000060 +#define GEN8_RASTER_DW1_FRONTFACE__SHIFT 5 +#define GEN8_RASTER_DW1_FRONTFACE_SOLID (0x0 << 5) +#define GEN8_RASTER_DW1_FRONTFACE_WIREFRAME (0x1 << 5) +#define GEN8_RASTER_DW1_FRONTFACE_POINT (0x2 << 5) +#define GEN8_RASTER_DW1_BACKFACE__MASK 0x00000018 +#define GEN8_RASTER_DW1_BACKFACE__SHIFT 3 +#define GEN8_RASTER_DW1_BACKFACE_SOLID (0x0 << 3) +#define GEN8_RASTER_DW1_BACKFACE_WIREFRAME (0x1 << 3) +#define GEN8_RASTER_DW1_BACKFACE_POINT (0x2 << 3) +#define GEN8_RASTER_DW1_AA_LINE_ENABLE (0x1 << 2) +#define GEN8_RASTER_DW1_SCISSOR_ENABLE (0x1 << 1) +#define GEN8_RASTER_DW1_Z_TEST_ENABLE (0x1 << 0) +#define GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE (0x1 << 0) + + + + #define GEN6_3DSTATE_WM__SIZE 9 @@ -817,10 +1124,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_WM_DW5_MAX_THREADS__MASK 0xfe000000 #define GEN6_WM_DW5_MAX_THREADS__SHIFT 25 #define GEN6_WM_DW5_LEGACY_LINE_RAST (0x1 << 23) -#define GEN6_WM_DW5_PS_KILL (0x1 << 22) +#define GEN6_WM_DW5_PS_KILL_PIXEL (0x1 << 22) #define GEN6_WM_DW5_PS_COMPUTE_DEPTH (0x1 << 21) #define GEN6_WM_DW5_PS_USE_DEPTH (0x1 << 20) -#define GEN6_WM_DW5_PS_ENABLE (0x1 << 19) +#define GEN6_WM_DW5_PS_DISPATCH_ENABLE (0x1 << 19) #define GEN6_WM_DW5_AA_LINE_CAP__MASK 0x00030000 #define GEN6_WM_DW5_AA_LINE_CAP__SHIFT 16 #define GEN6_WM_DW5_AA_LINE_CAP_0_5 (0x0 << 16) @@ -837,18 +1144,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_WM_DW5_LINE_STIPPLE_ENABLE (0x1 << 11) #define GEN6_WM_DW5_PS_COMPUTE_OMASK (0x1 << 9) #define GEN6_WM_DW5_PS_USE_W (0x1 << 8) -#define GEN6_WM_DW5_DUAL_SOURCE_BLEND (0x1 << 7) -#define GEN6_WM_DW5_32_PIXEL_DISPATCH (0x1 << 2) -#define GEN6_WM_DW5_16_PIXEL_DISPATCH (0x1 << 1) -#define GEN6_WM_DW5_8_PIXEL_DISPATCH (0x1 << 0) +#define GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND (0x1 << 7) +#define GEN6_WM_DW5_PS_DISPATCH_MODE__MASK 0x00000007 +#define GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT 0 #define GEN6_WM_DW6_SF_ATTR_COUNT__MASK 0x03f00000 #define GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT 20 -#define GEN6_WM_DW6_POSOFFSET__MASK 0x000c0000 -#define GEN6_WM_DW6_POSOFFSET__SHIFT 18 -#define GEN6_WM_DW6_POSOFFSET_NONE (0x0 << 18) -#define GEN6_WM_DW6_POSOFFSET_CENTROID (0x2 << 18) -#define GEN6_WM_DW6_POSOFFSET_SAMPLE (0x3 << 18) +#define GEN6_WM_DW6_PS_POSOFFSET__MASK 0x000c0000 +#define GEN6_WM_DW6_PS_POSOFFSET__SHIFT 18 +#define GEN6_WM_DW6_PS_POSOFFSET_NONE (0x0 << 18) +#define GEN6_WM_DW6_PS_POSOFFSET_CENTROID (0x2 << 18) +#define GEN6_WM_DW6_PS_POSOFFSET_SAMPLE (0x3 << 18) #define GEN6_WM_DW6_ZW_INTERP__MASK 0x00030000 #define GEN6_WM_DW6_ZW_INTERP__SHIFT 16 #define GEN6_WM_DW6_ZW_INTERP_PIXEL (0x0 << 16) @@ -882,11 +1188,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_WM_DW1_STATISTICS (0x1 << 31) #define GEN7_WM_DW1_DEPTH_CLEAR (0x1 << 30) -#define GEN7_WM_DW1_PS_ENABLE (0x1 << 29) +#define GEN7_WM_DW1_PS_DISPATCH_ENABLE (0x1 << 29) #define GEN7_WM_DW1_DEPTH_RESOLVE (0x1 << 28) #define GEN7_WM_DW1_HIZ_RESOLVE (0x1 << 27) #define GEN7_WM_DW1_LEGACY_LINE_RAST (0x1 << 26) -#define GEN7_WM_DW1_PS_KILL (0x1 << 25) +#define GEN7_WM_DW1_PS_KILL_PIXEL (0x1 << 25) #define GEN7_WM_DW1_PSCDEPTH__MASK 0x01800000 #define GEN7_WM_DW1_PSCDEPTH__SHIFT 23 #define GEN7_WM_DW1_PSCDEPTH_OFF (0x0 << 23) @@ -907,7 +1213,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_WM_DW1_ZW_INTERP_SAMPLE (0x3 << 17) #define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK 0x0001f800 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT 11 -#define GEN7_WM_DW1_PS_USE_COVERAGE (0x1 << 10) +#define GEN7_WM_DW1_PS_USE_COVERAGE_MASK (0x1 << 10) #define GEN7_WM_DW1_AA_LINE_CAP__MASK 0x00000300 #define GEN7_WM_DW1_AA_LINE_CAP__SHIFT 8 #define GEN7_WM_DW1_AA_LINE_CAP_0_5 (0x0 << 8) @@ -920,6 +1226,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_WM_DW1_AA_LINE_WIDTH_1_0 (0x1 << 6) #define GEN7_WM_DW1_AA_LINE_WIDTH_2_0 (0x2 << 6) #define GEN7_WM_DW1_AA_LINE_WIDTH_4_0 (0x3 << 6) +#define GEN75_WM_DW1_RT_INDEPENDENT_RAST (0x1 << 5) #define GEN7_WM_DW1_POLY_STIPPLE_ENABLE (0x1 << 4) #define GEN7_WM_DW1_LINE_STIPPLE_ENABLE (0x1 << 3) #define GEN7_WM_DW1_POINT_RASTRULE__MASK 0x00000004 @@ -937,8 +1244,86 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_WM_DW2_MSDISPMODE__SHIFT 31 #define GEN7_WM_DW2_MSDISPMODE_PERSAMPLE (0x0 << 31) #define GEN7_WM_DW2_MSDISPMODE_PERPIXEL (0x1 << 31) - -#define GEN7_3DSTATE_PS__SIZE 8 +#define GEN75_WM_DW2_PS_UAV_ONLY (0x1 << 30) + +#define GEN8_3DSTATE_WM_CHROMAKEY__SIZE 2 + + + +#define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE 4 + + +#define GEN8_ZS_DW1_STENCIL0_FAIL_OP__MASK 0xe0000000 +#define GEN8_ZS_DW1_STENCIL0_FAIL_OP__SHIFT 29 +#define GEN8_ZS_DW1_STENCIL0_ZFAIL_OP__MASK 0x1c000000 +#define GEN8_ZS_DW1_STENCIL0_ZFAIL_OP__SHIFT 26 +#define GEN8_ZS_DW1_STENCIL0_ZPASS_OP__MASK 0x03800000 +#define GEN8_ZS_DW1_STENCIL0_ZPASS_OP__SHIFT 23 +#define GEN8_ZS_DW1_STENCIL1_FUNC__MASK 0x00700000 +#define GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT 20 +#define GEN8_ZS_DW1_STENCIL1_FAIL_OP__MASK 0x000e0000 +#define GEN8_ZS_DW1_STENCIL1_FAIL_OP__SHIFT 17 +#define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__MASK 0x0001c000 +#define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT 14 +#define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__MASK 0x00003800 +#define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT 11 +#define GEN8_ZS_DW1_STENCIL0_FUNC__MASK 0x00000700 +#define GEN8_ZS_DW1_STENCIL0_FUNC__SHIFT 8 +#define GEN8_ZS_DW1_DEPTH_FUNC__MASK 0x000000e0 +#define GEN8_ZS_DW1_DEPTH_FUNC__SHIFT 5 +#define GEN8_ZS_DW1_STENCIL1_ENABLE (0x1 << 4) +#define GEN8_ZS_DW1_STENCIL_TEST_ENABLE (0x1 << 3) +#define GEN8_ZS_DW1_STENCIL_WRITE_ENABLE (0x1 << 2) +#define GEN8_ZS_DW1_DEPTH_TEST_ENABLE (0x1 << 1) +#define GEN8_ZS_DW1_DEPTH_WRITE_ENABLE (0x1 << 0) + +#define GEN8_ZS_DW2_STENCIL0_VALUEMASK__MASK 0xff000000 +#define GEN8_ZS_DW2_STENCIL0_VALUEMASK__SHIFT 24 +#define GEN8_ZS_DW2_STENCIL0_WRITEMASK__MASK 0x00ff0000 +#define GEN8_ZS_DW2_STENCIL0_WRITEMASK__SHIFT 16 +#define GEN8_ZS_DW2_STENCIL1_VALUEMASK__MASK 0x0000ff00 +#define GEN8_ZS_DW2_STENCIL1_VALUEMASK__SHIFT 8 +#define GEN8_ZS_DW2_STENCIL1_WRITEMASK__MASK 0x000000ff +#define GEN8_ZS_DW2_STENCIL1_WRITEMASK__SHIFT 0 + +#define GEN9_ZS_DW3_STENCIL0_REF__MASK 0x0000ff00 +#define GEN9_ZS_DW3_STENCIL0_REF__SHIFT 8 +#define GEN9_ZS_DW3_STENCIL1_REF__MASK 0x000000ff +#define GEN9_ZS_DW3_STENCIL1_REF__SHIFT 0 + +#define GEN8_3DSTATE_WM_HZ_OP__SIZE 5 + + +#define GEN8_WM_HZ_DW1_STENCIL_CLEAR (0x1 << 31) +#define GEN8_WM_HZ_DW1_DEPTH_CLEAR (0x1 << 30) +#define GEN8_WM_HZ_DW1_DEPTH_RESOLVE (0x1 << 28) +#define GEN8_WM_HZ_DW1_HIZ_RESOLVE (0x1 << 27) +#define GEN8_WM_HZ_DW1_PIXEL_OFFSET_ENABLE (0x1 << 26) +#define GEN8_WM_HZ_DW1_FULL_SURFACE_DEPTH_CLEAR (0x1 << 25) +#define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__MASK 0x00ff0000 +#define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__SHIFT 16 +#define GEN8_WM_HZ_DW1_NUMSAMPLES__MASK 0x0000e000 +#define GEN8_WM_HZ_DW1_NUMSAMPLES__SHIFT 13 +#define GEN8_WM_HZ_DW1_NUMSAMPLES_1 (0x0 << 13) +#define GEN8_WM_HZ_DW1_NUMSAMPLES_2 (0x1 << 13) +#define GEN8_WM_HZ_DW1_NUMSAMPLES_4 (0x2 << 13) +#define GEN8_WM_HZ_DW1_NUMSAMPLES_8 (0x3 << 13) +#define GEN8_WM_HZ_DW1_NUMSAMPLES_16 (0x4 << 13) + +#define GEN8_WM_HZ_DW2_RECT_MIN_Y__MASK 0xffff0000 +#define GEN8_WM_HZ_DW2_RECT_MIN_Y__SHIFT 16 +#define GEN8_WM_HZ_DW2_RECT_MIN_X__MASK 0x0000ffff +#define GEN8_WM_HZ_DW2_RECT_MIN_X__SHIFT 0 + +#define GEN8_WM_HZ_DW3_RECT_MAX_Y__MASK 0xffff0000 +#define GEN8_WM_HZ_DW3_RECT_MAX_Y__SHIFT 16 +#define GEN8_WM_HZ_DW3_RECT_MAX_X__MASK 0x0000ffff +#define GEN8_WM_HZ_DW3_RECT_MAX_X__SHIFT 0 + +#define GEN8_WM_HZ_DW4_SAMPLE_MASK__MASK 0x0000ffff +#define GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT 0 + +#define GEN7_3DSTATE_PS__SIZE 12 #define GEN7_PS_DW1_KERNEL0_ADDR__MASK 0xffffffc0 @@ -955,19 +1340,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN75_PS_DW4_SAMPLE_MASK__SHIFT 12 #define GEN7_PS_DW4_PUSH_CONSTANT_ENABLE (0x1 << 11) #define GEN7_PS_DW4_ATTR_ENABLE (0x1 << 10) -#define GEN7_PS_DW4_PS_COMPUTE_OMASK (0x1 << 9) +#define GEN7_PS_DW4_COMPUTE_OMASK (0x1 << 9) #define GEN7_PS_DW4_RT_FAST_CLEAR (0x1 << 8) #define GEN7_PS_DW4_DUAL_SOURCE_BLEND (0x1 << 7) #define GEN7_PS_DW4_RT_RESOLVE (0x1 << 6) -#define GEN75_PS_DW4_PS_ACCESS_UAV (0x1 << 5) +#define GEN75_PS_DW4_ACCESS_UAV (0x1 << 5) #define GEN7_PS_DW4_POSOFFSET__MASK 0x00000018 #define GEN7_PS_DW4_POSOFFSET__SHIFT 3 #define GEN7_PS_DW4_POSOFFSET_NONE (0x0 << 3) #define GEN7_PS_DW4_POSOFFSET_CENTROID (0x2 << 3) #define GEN7_PS_DW4_POSOFFSET_SAMPLE (0x3 << 3) -#define GEN7_PS_DW4_32_PIXEL_DISPATCH (0x1 << 2) -#define GEN7_PS_DW4_16_PIXEL_DISPATCH (0x1 << 1) -#define GEN7_PS_DW4_8_PIXEL_DISPATCH (0x1 << 0) +#define GEN7_PS_DW4_DISPATCH_MODE__MASK 0x00000007 +#define GEN7_PS_DW4_DISPATCH_MODE__SHIFT 0 #define GEN7_PS_DW5_URB_GRF_START0__MASK 0x007f0000 #define GEN7_PS_DW5_URB_GRF_START0__SHIFT 16 @@ -984,38 +1368,120 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_PS_DW7_KERNEL2_ADDR__SHIFT 6 #define GEN7_PS_DW7_KERNEL2_ADDR__SHR 6 -#define GEN6_3DSTATE_CONSTANT_ANY__SIZE 7 -#define GEN6_PCB_ANY_DW0_PCB3_VALID (0x1 << 15) -#define GEN6_PCB_ANY_DW0_PCB2_VALID (0x1 << 14) -#define GEN6_PCB_ANY_DW0_PCB1_VALID (0x1 << 13) -#define GEN6_PCB_ANY_DW0_PCB0_VALID (0x1 << 12) -#define GEN6_PCB_ANY_DW0_MOCS__MASK 0x00000f00 -#define GEN6_PCB_ANY_DW0_MOCS__SHIFT 8 -#define GEN6_PCB_ANY_SIZE__MASK 0x0000001f -#define GEN6_PCB_ANY_SIZE__SHIFT 0 -#define GEN6_PCB_ANY_ADDR__MASK 0xffffffe0 -#define GEN6_PCB_ANY_ADDR__SHIFT 5 -#define GEN6_PCB_ANY_ADDR__SHR 5 +#define GEN8_PS_DW1_KERNEL0_ADDR__MASK 0xffffffc0 +#define GEN8_PS_DW1_KERNEL0_ADDR__SHIFT 6 +#define GEN8_PS_DW1_KERNEL0_ADDR__SHR 6 + + + + +#define GEN8_PS_DW6_MAX_THREADS__MASK 0xff800000 +#define GEN8_PS_DW6_MAX_THREADS__SHIFT 23 +#define GEN8_PS_DW6_PUSH_CONSTANT_ENABLE (0x1 << 11) +#define GEN8_PS_DW6_RT_FAST_CLEAR (0x1 << 8) +#define GEN8_PS_DW6_RT_RESOLVE (0x1 << 6) +#define GEN8_PS_DW6_POSOFFSET__MASK 0x00000018 +#define GEN8_PS_DW6_POSOFFSET__SHIFT 3 +#define GEN8_PS_DW6_POSOFFSET_NONE (0x0 << 3) +#define GEN8_PS_DW6_POSOFFSET_CENTROID (0x2 << 3) +#define GEN8_PS_DW6_POSOFFSET_SAMPLE (0x3 << 3) +#define GEN8_PS_DW6_DISPATCH_MODE__MASK 0x00000007 +#define GEN8_PS_DW6_DISPATCH_MODE__SHIFT 0 +#define GEN8_PS_DW7_URB_GRF_START0__MASK 0x007f0000 +#define GEN8_PS_DW7_URB_GRF_START0__SHIFT 16 +#define GEN8_PS_DW7_URB_GRF_START1__MASK 0x00007f00 +#define GEN8_PS_DW7_URB_GRF_START1__SHIFT 8 +#define GEN8_PS_DW7_URB_GRF_START2__MASK 0x0000007f +#define GEN8_PS_DW7_URB_GRF_START2__SHIFT 0 -#define GEN7_PCB_ANY_DW1_PCB1_SIZE__MASK 0xffff0000 -#define GEN7_PCB_ANY_DW1_PCB1_SIZE__SHIFT 16 -#define GEN7_PCB_ANY_DW1_PCB0_SIZE__MASK 0x0000ffff -#define GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT 0 +#define GEN8_PS_DW8_KERNEL1_ADDR__MASK 0xffffffc0 +#define GEN8_PS_DW8_KERNEL1_ADDR__SHIFT 6 +#define GEN8_PS_DW8_KERNEL1_ADDR__SHR 6 -#define GEN7_PCB_ANY_DW2_PCB3_SIZE__MASK 0xffff0000 -#define GEN7_PCB_ANY_DW2_PCB3_SIZE__SHIFT 16 -#define GEN7_PCB_ANY_DW2_PCB2_SIZE__MASK 0x0000ffff -#define GEN7_PCB_ANY_DW2_PCB2_SIZE__SHIFT 0 -#define GEN7_PCB_ANY_MOCS__MASK 0x0000001f -#define GEN7_PCB_ANY_MOCS__SHIFT 0 -#define GEN7_PCB_ANY_ADDR__MASK 0xffffffe0 -#define GEN7_PCB_ANY_ADDR__SHIFT 5 -#define GEN7_PCB_ANY_ADDR__SHR 5 +#define GEN8_PS_DW10_KERNEL2_ADDR__MASK 0xffffffc0 +#define GEN8_PS_DW10_KERNEL2_ADDR__SHIFT 6 +#define GEN8_PS_DW10_KERNEL2_ADDR__SHR 6 + + +#define GEN8_3DSTATE_PS_EXTRA__SIZE 2 + + +#define GEN8_PSX_DW1_DISPATCH_ENABLE (0x1 << 31) +#define GEN8_PSX_DW1_UAV_ONLY (0x1 << 30) +#define GEN8_PSX_DW1_COMPUTE_OMASK (0x1 << 29) +#define GEN8_PSX_DW1_KILL_PIXEL (0x1 << 28) +#define GEN8_PSX_DW1_PSCDEPTH__MASK 0x0c000000 +#define GEN8_PSX_DW1_PSCDEPTH__SHIFT 26 +#define GEN8_PSX_DW1_PSCDEPTH_OFF (0x0 << 26) +#define GEN8_PSX_DW1_PSCDEPTH_ON (0x1 << 26) +#define GEN8_PSX_DW1_PSCDEPTH_ON_GE (0x2 << 26) +#define GEN8_PSX_DW1_PSCDEPTH_ON_LE (0x3 << 26) +#define GEN8_PSX_DW1_FORCE_COMPUTE_DEPTH (0x1 << 25) +#define GEN8_PSX_DW1_USE_DEPTH (0x1 << 24) +#define GEN8_PSX_DW1_USE_W (0x1 << 23) +#define GEN8_PSX_DW1_ATTR_ENABLE (0x1 << 8) +#define GEN8_PSX_DW1_DISABLE_ALPHA_TO_COVERAGE (0x1 << 7) +#define GEN8_PSX_DW1_PER_SAMPLE (0x1 << 6) +#define GEN8_PSX_DW1_COMPUTE_STENCIL (0x1 << 5) +#define GEN8_PSX_DW1_ACCESS_UAV (0x1 << 2) +#define GEN8_PSX_DW1_USE_COVERAGE_MASK (0x1 << 1) + +#define GEN8_3DSTATE_PS_BLEND__SIZE 2 + + +#define GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE (0x1 << 31) +#define GEN8_PS_BLEND_DW1_WRITABLE_RT (0x1 << 30) +#define GEN8_PS_BLEND_DW1_BLEND_ENABLE (0x1 << 29) +#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__MASK 0x1f000000 +#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__SHIFT 24 +#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__MASK 0x00f80000 +#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__SHIFT 19 +#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__MASK 0x0007c000 +#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__SHIFT 14 +#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__MASK 0x00003e00 +#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__SHIFT 9 +#define GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE (0x1 << 8) +#define GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE (0x1 << 7) + +#define GEN6_3DSTATE_CONSTANT_ANY__SIZE 11 + +#define GEN6_CONSTANT_DW0_BUFFER_ENABLES__MASK 0x0000f000 +#define GEN6_CONSTANT_DW0_BUFFER_ENABLES__SHIFT 12 +#define GEN6_CONSTANT_DW0_MOCS__MASK 0x00000f00 +#define GEN6_CONSTANT_DW0_MOCS__SHIFT 8 + +#define GEN6_CONSTANT_DW_ADDR_READ_LEN__MASK 0x0000001f +#define GEN6_CONSTANT_DW_ADDR_READ_LEN__SHIFT 0 +#define GEN6_CONSTANT_DW_ADDR_ADDR__MASK 0xffffffe0 +#define GEN6_CONSTANT_DW_ADDR_ADDR__SHIFT 5 +#define GEN6_CONSTANT_DW_ADDR_ADDR__SHR 5 + + + +#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__MASK 0xffff0000 +#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__SHIFT 16 +#define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__MASK 0x0000ffff +#define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__SHIFT 0 + +#define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__MASK 0xffff0000 +#define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__SHIFT 16 +#define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__MASK 0x0000ffff +#define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__SHIFT 0 + +#define GEN7_CONSTANT_DW_ADDR_MOCS__MASK 0x0000001f +#define GEN7_CONSTANT_DW_ADDR_MOCS__SHIFT 0 +#define GEN7_CONSTANT_DW_ADDR_ADDR__MASK 0xffffffe0 +#define GEN7_CONSTANT_DW_ADDR_ADDR__SHIFT 5 +#define GEN7_CONSTANT_DW_ADDR_ADDR__SHR 5 + +#define GEN8_CONSTANT_DW_ADDR_ADDR__MASK 0xffffffe0 +#define GEN8_CONSTANT_DW_ADDR_ADDR__SHIFT 5 +#define GEN8_CONSTANT_DW_ADDR_ADDR__SHR 5 #define GEN6_3DSTATE_SAMPLE_MASK__SIZE 2 @@ -1024,6 +1490,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_SAMPLE_MASK_DW1_VAL__SHIFT 0 #define GEN7_SAMPLE_MASK_DW1_VAL__MASK 0x000000ff #define GEN7_SAMPLE_MASK_DW1_VAL__SHIFT 0 +#define GEN8_SAMPLE_MASK_DW1_VAL__MASK 0x0000ffff +#define GEN8_SAMPLE_MASK_DW1_VAL__SHIFT 0 #define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE 4 @@ -1043,7 +1511,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__MASK 0x0000ffff #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__SHIFT 0 -#define GEN6_3DSTATE_DEPTH_BUFFER__SIZE 7 +#define GEN6_3DSTATE_DEPTH_BUFFER__SIZE 8 #define GEN6_DEPTH_DW1_TYPE__MASK 0xe0000000 @@ -1121,6 +1589,44 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__MASK 0xffe00000 #define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT 21 + + +#define GEN8_DEPTH_DW1_TYPE__MASK 0xe0000000 +#define GEN8_DEPTH_DW1_TYPE__SHIFT 29 +#define GEN8_DEPTH_DW1_DEPTH_WRITE_ENABLE (0x1 << 28) +#define GEN8_DEPTH_DW1_STENCIL_WRITE_ENABLE (0x1 << 27) +#define GEN8_DEPTH_DW1_HIZ_ENABLE (0x1 << 22) +#define GEN8_DEPTH_DW1_FORMAT__MASK 0x001c0000 +#define GEN8_DEPTH_DW1_FORMAT__SHIFT 18 +#define GEN8_DEPTH_DW1_PITCH__MASK 0x0003ffff +#define GEN8_DEPTH_DW1_PITCH__SHIFT 0 + + + +#define GEN8_DEPTH_DW4_HEIGHT__MASK 0xfffc0000 +#define GEN8_DEPTH_DW4_HEIGHT__SHIFT 18 +#define GEN8_DEPTH_DW4_WIDTH__MASK 0x0003fff0 +#define GEN8_DEPTH_DW4_WIDTH__SHIFT 4 +#define GEN8_DEPTH_DW4_LOD__MASK 0x0000000f +#define GEN8_DEPTH_DW4_LOD__SHIFT 0 + +#define GEN8_DEPTH_DW5_DEPTH__MASK 0xffe00000 +#define GEN8_DEPTH_DW5_DEPTH__SHIFT 21 +#define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__MASK 0x001ffc00 +#define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__SHIFT 10 +#define GEN8_DEPTH_DW5_MOCS__MASK 0x0000007f +#define GEN8_DEPTH_DW5_MOCS__SHIFT 0 + +#define GEN8_DEPTH_DW6_OFFSET_Y__MASK 0xffff0000 +#define GEN8_DEPTH_DW6_OFFSET_Y__SHIFT 16 +#define GEN8_DEPTH_DW6_OFFSET_X__MASK 0x0000ffff +#define GEN8_DEPTH_DW6_OFFSET_X__SHIFT 0 + +#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__MASK 0xffe00000 +#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__SHIFT 21 +#define GEN8_DEPTH_DW7_QPITCH__MASK 0x00007fff +#define GEN8_DEPTH_DW7_QPITCH__SHIFT 0 + #define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE 2 @@ -1185,22 +1691,41 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__MASK 0x0000000e #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__SHIFT 1 #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1 (0x0 << 1) +#define GEN8_MULTISAMPLE_DW1_NUMSAMPLES_2 (0x1 << 1) #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4 (0x2 << 1) #define GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8 (0x3 << 1) +#define GEN8_MULTISAMPLE_DW1_NUMSAMPLES_16 (0x4 << 1) + + + +#define GEN8_3DSTATE_SAMPLE_PATTERN__SIZE 9 + -#define GEN6_3DSTATE_STENCIL_BUFFER__SIZE 3 + +#define GEN8_SAMPLE_PATTERN_DW8_1X__MASK 0x00ff0000 +#define GEN8_SAMPLE_PATTERN_DW8_1X__SHIFT 16 +#define GEN8_SAMPLE_PATTERN_DW8_2X__MASK 0x0000ffff +#define GEN8_SAMPLE_PATTERN_DW8_2X__SHIFT 0 + +#define GEN6_3DSTATE_STENCIL_BUFFER__SIZE 5 #define GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE (0x1 << 31) #define GEN6_STENCIL_DW1_MOCS__MASK 0x1e000000 #define GEN6_STENCIL_DW1_MOCS__SHIFT 25 +#define GEN8_STENCIL_DW1_MOCS__MASK 0x1fc00000 +#define GEN8_STENCIL_DW1_MOCS__SHIFT 22 #define GEN6_STENCIL_DW1_PITCH__MASK 0x0001ffff #define GEN6_STENCIL_DW1_PITCH__SHIFT 0 -#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE 3 + +#define GEN8_STENCIL_DW4_QPITCH__MASK 0x00007fff +#define GEN8_STENCIL_DW4_QPITCH__SHIFT 0 + +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE 5 #define GEN6_HIZ_DW1_MOCS__MASK 0x1e000000 @@ -1215,56 +1740,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - #define GEN7_CLEAR_PARAMS_DW2_VALID (0x1 << 0) -#define GEN6_PIPE_CONTROL__SIZE 5 - - -#define GEN7_PIPE_CONTROL_USE_GGTT (0x1 << 24) -#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK 0x00800000 -#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT 23 -#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE (0x0 << 23) -#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM (0x1 << 23) -#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE (0x1 << 22) -#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX (0x1 << 21) -#define GEN6_PIPE_CONTROL_CS_STALL (0x1 << 20) -#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (0x1 << 19) -#define GEN6_PIPE_CONTROL_TLB_INVALIDATE (0x1 << 18) -#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE (0x1 << 17) -#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR (0x1 << 16) -#define GEN6_PIPE_CONTROL_WRITE__MASK 0x0000c000 -#define GEN6_PIPE_CONTROL_WRITE__SHIFT 14 -#define GEN6_PIPE_CONTROL_WRITE_NONE (0x0 << 14) -#define GEN6_PIPE_CONTROL_WRITE_IMM (0x1 << 14) -#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT (0x2 << 14) -#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP (0x3 << 14) -#define GEN6_PIPE_CONTROL_DEPTH_STALL (0x1 << 13) -#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH (0x1 << 12) -#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (0x1 << 11) -#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (0x1 << 10) -#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE (0x1 << 9) -#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE (0x1 << 8) -#define GEN7_PIPE_CONTROL_FLUSH_ENABLE (0x1 << 7) -#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK 0x00000040 -#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT 6 -#define GEN7_PIPE_CONTROL_DC_FLUSH_ENABLE (0x1 << 5) -#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE (0x1 << 4) -#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE (0x1 << 3) -#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE (0x1 << 2) -#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL (0x1 << 1) -#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (0x1 << 0) - -#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffff8 -#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT 3 -#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR 3 -#define GEN6_PIPE_CONTROL_DW2_USE_GGTT (0x1 << 2) -#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc -#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT 2 -#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR 2 - - #define GEN6_3DPRIMITIVE__SIZE 7 #define GEN6_3DPRIM_DW0_ACCESS__MASK 0x00008000 @@ -1282,6 +1759,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_3DPRIM_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10) +#define GEN75_3DPRIM_DW0_UAV_COHERENCY_REQUIRED (0x1 << 9) #define GEN7_3DPRIM_DW0_PREDICATE_ENABLE (0x1 << 8) #define GEN7_3DPRIM_DW1_END_OFFSET_ENABLE (0x1 << 9) |