diff options
Diffstat (limited to 'src/gallium/drivers/ilo/genhw/gen_render.xml.h')
| -rw-r--r-- | src/gallium/drivers/ilo/genhw/gen_render.xml.h | 136 |
1 files changed, 124 insertions, 12 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_render.xml.h b/src/gallium/drivers/ilo/genhw/gen_render.xml.h index 9009437e40f..8a535d8e9f2 100644 --- a/src/gallium/drivers/ilo/genhw/gen_render.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_render.xml.h @@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository https://github.com/olvaffe/envytools/ git clone https://github.com/olvaffe/envytools.git -Copyright (C) 2014 by the following authors: +Copyright (C) 2014-2015 by the following authors: - Chia-I Wu <olvaffe@gmail.com> (olv) Permission is hereby granted, free of charge, to any person obtaining @@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER (0xa << 16) #define GEN75_RENDER_OPCODE_3DSTATE_VF (0xc << 16) #define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS (0xd << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0xd << 16) #define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS (0xe << 16) #define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS (0xf << 16) #define GEN6_RENDER_OPCODE_3DSTATE_VS (0x10 << 16) @@ -101,6 +102,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_VF_INSTANCING (0x49 << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_VF_SGVS (0x4a << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_VF_TOPOLOGY (0x4b << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_WM_CHROMAKEY (0x4c << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_PS_BLEND (0x4d << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_WM_DEPTH_STENCIL (0x4e << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_PS_EXTRA (0x4f << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_RASTER (0x50 << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_SBE_SWIZ (0x51 << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_WM_HZ_OP (0x52 << 16) #define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE (0x100 << 16) #define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x105 << 16) #define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET (0x106 << 16) @@ -119,6 +130,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16) #define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16) +#define GEN8_RENDER_OPCODE_3DSTATE_SAMPLE_PATTERN (0x11c << 16) #define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16) #define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16) #define GEN6_RENDER_LENGTH__MASK 0x000000ff @@ -142,18 +154,39 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_MOCS_L3__SHIFT 0 #define GEN7_MOCS_L3_UC 0x0 #define GEN7_MOCS_L3_ON 0x1 -#define GEN6_BASE_ADDR__MASK 0xfffff000 -#define GEN6_BASE_ADDR__SHIFT 12 -#define GEN6_BASE_ADDR__SHR 12 -#define GEN6_BASE_ADDR_MOCS__MASK 0x00000f00 -#define GEN6_BASE_ADDR_MOCS__SHIFT 8 -#define GEN6_BASE_ADDR_MODIFIED (0x1 << 0) -#define GEN6_STATE_BASE_ADDRESS__SIZE 10 +#define GEN8_MOCS_LLC__MASK 0x00000060 +#define GEN8_MOCS_LLC__SHIFT 5 +#define GEN8_MOCS_LLC_PTE (0x0 << 5) +#define GEN8_MOCS_LLC_UC (0x1 << 5) +#define GEN8_MOCS_LLC_WT (0x2 << 5) +#define GEN8_MOCS_LLC_WB (0x3 << 5) +#define GEN8_MOCS_L3__MASK 0x00000018 +#define GEN8_MOCS_L3__SHIFT 3 +#define GEN8_MOCS_L3_ELLC_ONLY (0x0 << 3) +#define GEN8_MOCS_L3_LLC_ONLY (0x1 << 3) +#define GEN8_MOCS_L3_LLC (0x2 << 3) +#define GEN8_MOCS_L3_ON (0x3 << 3) +#define GEN9_MOCS__MASK 0x0000007f +#define GEN9_MOCS__SHIFT 0 +#define GEN9_MOCS_WT 0x5 +#define GEN9_MOCS_WB 0x9 +#define GEN6_SBA_ADDR__MASK 0xfffff000 +#define GEN6_SBA_ADDR__SHIFT 12 +#define GEN6_SBA_ADDR__SHR 12 +#define GEN6_SBA_MOCS__MASK 0x00000f00 +#define GEN6_SBA_MOCS__SHIFT 8 +#define GEN8_SBA_MOCS__MASK 0x000007f0 +#define GEN8_SBA_MOCS__SHIFT 4 +#define GEN6_SBA_ADDR_MODIFIED (0x1 << 0) +#define GEN6_BINDING_TABLE_ADDR__MASK 0x0000ffe0 +#define GEN6_BINDING_TABLE_ADDR__SHIFT 5 +#define GEN6_BINDING_TABLE_ADDR__SHR 5 +#define GEN6_STATE_BASE_ADDRESS__SIZE 19 -#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0 -#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__SHIFT 4 -#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3) +#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0 +#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__SHIFT 4 +#define GEN6_SBA_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3) @@ -163,13 +196,36 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -#define GEN6_STATE_SIP__SIZE 2 + + + + +#define GEN8_SBA_DW3_STATELESS_MOCS__MASK 0x007f0000 +#define GEN8_SBA_DW3_STATELESS_MOCS__SHIFT 16 + + + + + + + + + + + + + + + + +#define GEN6_STATE_SIP__SIZE 3 #define GEN6_SIP_DW1_KERNEL_ADDR__MASK 0xfffffff0 #define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT 4 #define GEN6_SIP_DW1_KERNEL_ADDR__SHR 4 + #define GEN6_PIPELINE_SELECT__SIZE 1 #define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000003 @@ -177,6 +233,62 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_PIPELINE_SELECT_DW0_SELECT_3D 0x0 #define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA 0x1 #define GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU 0x2 +#define GEN9_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000700 +#define GEN9_PIPELINE_SELECT_DW0_SELECT__SHIFT 8 +#define GEN9_PIPELINE_SELECT_DW0_SELECT_3D (0x3 << 8) + +#define GEN6_PIPE_CONTROL__SIZE 6 + + +#define GEN7_PIPE_CONTROL_USE_GGTT (0x1 << 24) +#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK 0x00800000 +#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT 23 +#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE (0x0 << 23) +#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM (0x1 << 23) +#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE (0x1 << 22) +#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX (0x1 << 21) +#define GEN6_PIPE_CONTROL_CS_STALL (0x1 << 20) +#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (0x1 << 19) +#define GEN6_PIPE_CONTROL_TLB_INVALIDATE (0x1 << 18) +#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE (0x1 << 17) +#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR (0x1 << 16) +#define GEN6_PIPE_CONTROL_WRITE__MASK 0x0000c000 +#define GEN6_PIPE_CONTROL_WRITE__SHIFT 14 +#define GEN6_PIPE_CONTROL_WRITE_NONE (0x0 << 14) +#define GEN6_PIPE_CONTROL_WRITE_IMM (0x1 << 14) +#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT (0x2 << 14) +#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP (0x3 << 14) +#define GEN6_PIPE_CONTROL_DEPTH_STALL (0x1 << 13) +#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH (0x1 << 12) +#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (0x1 << 11) +#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (0x1 << 10) +#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE (0x1 << 9) +#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE (0x1 << 8) +#define GEN7_PIPE_CONTROL_WRITE_IMM_FLUSH (0x1 << 7) +#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK 0x00000040 +#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT 6 +#define GEN7_PIPE_CONTROL_DC_FLUSH (0x1 << 5) +#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE (0x1 << 4) +#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE (0x1 << 3) +#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE (0x1 << 2) +#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL (0x1 << 1) +#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (0x1 << 0) + +#define GEN6_PIPE_CONTROL_DW2_USE_GGTT (0x1 << 2) +#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffff8 +#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT 3 +#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR 3 + +#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc +#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT 2 +#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR 2 + +#define GEN8_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc +#define GEN8_PIPE_CONTROL_DW2_ADDR__SHIFT 2 +#define GEN8_PIPE_CONTROL_DW2_ADDR__SHR 2 + + + #endif /* GEN_RENDER_XML */ |