diff options
Diffstat (limited to 'src/gallium/drivers/ilo/genhw/gen_mi.xml.h')
| -rw-r--r-- | src/gallium/drivers/ilo/genhw/gen_mi.xml.h | 149 |
1 files changed, 142 insertions, 7 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h index 219ddab2653..7995869a185 100644 --- a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h +++ b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h @@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository https://github.com/olvaffe/envytools/ git clone https://github.com/olvaffe/envytools.git -Copyright (C) 2014 by the following authors: +Copyright (C) 2014-2015 by the following authors: - Chia-I Wu <olvaffe@gmail.com> (olv) Permission is hereby granted, free of charge, to any person obtaining @@ -32,34 +32,131 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ +#define GEN75_MI_ALU_NOOP 0x0 +#define GEN75_MI_ALU_LOAD 0x80 +#define GEN75_MI_ALU_LOADINV 0x480 +#define GEN75_MI_ALU_LOAD0 0x81 +#define GEN75_MI_ALU_LOAD1 0x481 +#define GEN75_MI_ALU_ADD 0x100 +#define GEN75_MI_ALU_SUB 0x101 +#define GEN75_MI_ALU_AND 0x102 +#define GEN75_MI_ALU_OR 0x103 +#define GEN75_MI_ALU_XOR 0x104 +#define GEN75_MI_ALU_STORE 0x180 +#define GEN75_MI_ALU_STOREINV 0x580 +#define GEN75_MI_ALU_R0 0x0 +#define GEN75_MI_ALU_R1 0x1 +#define GEN75_MI_ALU_R2 0x2 +#define GEN75_MI_ALU_R3 0x3 +#define GEN75_MI_ALU_R4 0x4 +#define GEN75_MI_ALU_R5 0x5 +#define GEN75_MI_ALU_R6 0x6 +#define GEN75_MI_ALU_R7 0x7 +#define GEN75_MI_ALU_R8 0x8 +#define GEN75_MI_ALU_R9 0x9 +#define GEN75_MI_ALU_R10 0xa +#define GEN75_MI_ALU_R11 0xb +#define GEN75_MI_ALU_R12 0xc +#define GEN75_MI_ALU_R13 0xd +#define GEN75_MI_ALU_R14 0xe +#define GEN75_MI_ALU_R15 0xf +#define GEN75_MI_ALU_SRCA 0x20 +#define GEN75_MI_ALU_SRCB 0x21 +#define GEN75_MI_ALU_ACCU 0x31 +#define GEN75_MI_ALU_ZF 0x32 +#define GEN75_MI_ALU_CF 0x33 #define GEN6_MI_TYPE__MASK 0xe0000000 #define GEN6_MI_TYPE__SHIFT 29 #define GEN6_MI_TYPE_MI (0x0 << 29) #define GEN6_MI_OPCODE__MASK 0x1f800000 #define GEN6_MI_OPCODE__SHIFT 23 #define GEN6_MI_OPCODE_MI_NOOP (0x0 << 23) +#define GEN75_MI_OPCODE_MI_SET_PREDICATE (0x1 << 23) +#define GEN75_MI_OPCODE_MI_RS_CONTROL (0x6 << 23) +#define GEN75_MI_OPCODE_MI_URB_ATOMIC_ALLOC (0x9 << 23) #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END (0xa << 23) +#define GEN7_MI_OPCODE_MI_PREDICATE (0xc << 23) +#define GEN7_MI_OPCODE_MI_URB_CLEAR (0x19 << 23) +#define GEN75_MI_OPCODE_MI_MATH (0x1a << 23) #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23) #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23) #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23) #define GEN6_MI_OPCODE_MI_FLUSH_DW (0x26 << 23) #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23) #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23) +#define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG (0x2a << 23) +#define GEN75_MI_OPCODE_MI_LOAD_URB_MEM (0x2c << 23) +#define GEN75_MI_OPCODE_MI_STORE_URB_MEM (0x2d << 23) #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23) #define GEN6_MI_LENGTH__MASK 0x0000003f #define GEN6_MI_LENGTH__SHIFT 0 #define GEN6_MI_NOOP__SIZE 1 +#define GEN75_MI_SET_PREDICATE__SIZE 1 +#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__MASK 0x00000003 +#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__SHIFT 0 +#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ALWAYS 0x0 +#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_CLEAR 0x1 +#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_SET 0x2 +#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_DISABLE 0x3 + +#define GEN75_MI_RS_CONTROL__SIZE 1 +#define GEN75_MI_RS_CONTROL_DW0_ENABLE (0x1 << 0) + +#define GEN75_MI_URB_ATOMIC_ALLOC__SIZE 1 +#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__MASK 0x000ff000 +#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__SHIFT 12 +#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__MASK 0x000001ff +#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__SHIFT 0 + #define GEN6_MI_BATCH_BUFFER_END__SIZE 1 -#define GEN6_MI_STORE_DATA_IMM__SIZE 5 +#define GEN7_MI_PREDICATE__SIZE 1 +#define GEN7_MI_PREDICATE_DW0_LOADOP__MASK 0x000000c0 +#define GEN7_MI_PREDICATE_DW0_LOADOP__SHIFT 6 +#define GEN7_MI_PREDICATE_DW0_LOADOP_KEEP (0x0 << 6) +#define GEN7_MI_PREDICATE_DW0_LOADOP_LOAD (0x2 << 6) +#define GEN7_MI_PREDICATE_DW0_LOADOP_LOADINV (0x3 << 6) +#define GEN7_MI_PREDICATE_DW0_COMBINEOP__MASK 0x00000018 +#define GEN7_MI_PREDICATE_DW0_COMBINEOP__SHIFT 3 +#define GEN7_MI_PREDICATE_DW0_COMBINEOP_SET (0x0 << 3) +#define GEN7_MI_PREDICATE_DW0_COMBINEOP_AND (0x1 << 3) +#define GEN7_MI_PREDICATE_DW0_COMBINEOP_OR (0x2 << 3) +#define GEN7_MI_PREDICATE_DW0_COMBINEOP_XOR (0x3 << 3) +#define GEN7_MI_PREDICATE_DW0_COMPAREOP__MASK 0x00000003 +#define GEN7_MI_PREDICATE_DW0_COMPAREOP__SHIFT 0 +#define GEN7_MI_PREDICATE_DW0_COMPAREOP_TRUE 0x0 +#define GEN7_MI_PREDICATE_DW0_COMPAREOP_FALSE 0x1 +#define GEN7_MI_PREDICATE_DW0_COMPAREOP_SRCS_EQUAL 0x2 +#define GEN7_MI_PREDICATE_DW0_COMPAREOP_DELTAS_EQUAL 0x3 + +#define GEN7_MI_URB_CLEAR__SIZE 2 + +#define GEN7_MI_URB_CLEAR_DW1_LENGTH__MASK 0x3fff0000 +#define GEN7_MI_URB_CLEAR_DW1_LENGTH__SHIFT 16 +#define GEN7_MI_URB_CLEAR_DW1_OFFSET__MASK 0x00007fff +#define GEN7_MI_URB_CLEAR_DW1_OFFSET__SHIFT 0 + +#define GEN75_MI_MATH__SIZE 65 + +#define GEN75_MI_MATH_DW_OP__MASK 0xfff00000 +#define GEN75_MI_MATH_DW_OP__SHIFT 20 +#define GEN75_MI_MATH_DW_SRC1__MASK 0x000ffc00 +#define GEN75_MI_MATH_DW_SRC1__SHIFT 10 +#define GEN75_MI_MATH_DW_SRC2__MASK 0x000007ff +#define GEN75_MI_MATH_DW_SRC2__SHIFT 0 + +#define GEN6_MI_STORE_DATA_IMM__SIZE 6 #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22) + #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT 2 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR 2 + + #define GEN6_MI_LOAD_REGISTER_IMM__SIZE 3 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK 0x00000f00 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT 8 @@ -69,7 +166,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR 2 -#define GEN6_MI_STORE_REGISTER_MEM__SIZE 3 +#define GEN6_MI_STORE_REGISTER_MEM__SIZE 4 #define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) #define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE (0x1 << 21) @@ -81,18 +178,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT 2 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2 + #define GEN6_MI_FLUSH_DW__SIZE 4 + + + #define GEN6_MI_REPORT_PERF_COUNT__SIZE 3 +#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4) +#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0) #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK 0xffffffc0 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT 6 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR 6 -#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4) -#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0) -#define GEN7_MI_LOAD_REGISTER_MEM__SIZE 3 +#define GEN7_MI_LOAD_REGISTER_MEM__SIZE 4 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) #define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE (0x1 << 21) @@ -104,7 +205,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT 2 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR 2 -#define GEN6_MI_BATCH_BUFFER_START__SIZE 2 + +#define GEN75_MI_LOAD_REGISTER_REG__SIZE 3 + +#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__MASK 0x007ffffc +#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHIFT 2 +#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHR 2 + +#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__MASK 0x007ffffc +#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT 2 +#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR 2 + +#define GEN75_MI_LOAD_URB_MEM__SIZE 4 + +#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK 0x00007ffc +#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHIFT 2 +#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHR 2 + +#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__MASK 0xffffffc0 +#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHIFT 6 +#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHR 6 + + +#define GEN75_MI_STORE_URB_MEM__SIZE 4 + +#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__MASK 0x00007ffc +#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHIFT 2 +#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHR 2 + +#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__MASK 0xffffffc0 +#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHIFT 6 +#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR 6 + + +#define GEN6_MI_BATCH_BUFFER_START__SIZE 3 #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22) #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16) #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15) @@ -117,4 +251,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR 2 + #endif /* GEN_MI_XML */ |