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-rw-r--r--src/amd/common/ac_surface.c12
-rw-r--r--src/amd/common/ac_surface.h2
-rw-r--r--src/amd/vulkan/radv_device.c8
-rw-r--r--src/amd/vulkan/radv_formats.c4
-rw-r--r--src/amd/vulkan/radv_image.c4
5 files changed, 15 insertions, 15 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b47159f3b04..23ef5381e76 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -797,7 +797,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *
surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
dcc_level = &surf->u.legacy.dcc_level[level];
- surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
+ surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256;
surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
@@ -835,7 +835,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *
}
}
- surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
+ surf->surf_size = (uint64_t)surf_level->offset_256B * 256 + AddrSurfInfoOut->surfSize;
/* Clear DCC fields at the beginning. */
if (!AddrSurfInfoIn->flags.depth && !AddrSurfInfoIn->flags.stencil)
@@ -2721,7 +2721,7 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s
if (info->chip_class >= GFX9)
offset = surf->u.gfx9.surf_offset;
else
- offset = surf->u.legacy.level[0].offset;
+ offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256;
if (offset || /* Non-zero planes ignore metadata. */
size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */
@@ -2851,7 +2851,7 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_s
/* Dwords [10:..] contain the mipmap level offsets. */
if (info->chip_class <= GFX8) {
for (unsigned i = 0; i < num_mipmap_levels; i++)
- metadata[10 + i] = surf->u.legacy.level[i].offset >> 8;
+ metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
*size_metadata += num_mipmap_levels * 4;
}
@@ -2927,7 +2927,7 @@ bool ac_surface_override_offset_stride(const struct radeon_info *info, struct ra
if (offset) {
for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
- surf->u.legacy.level[i].offset += offset;
+ surf->u.legacy.level[i].offset_256B += offset / 256;
}
}
@@ -2970,7 +2970,7 @@ uint64_t ac_surface_get_plane_offset(enum chip_class chip_class,
return surf->u.gfx9.surf_offset +
layer * surf->u.gfx9.surf_slice_size;
} else {
- return surf->u.legacy.level[0].offset +
+ return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 +
layer * (uint64_t)surf->u.legacy.level[0].slice_size_dw * 4;
}
case 1:
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 7438c5ee7ad..f5a8508d85e 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -85,7 +85,7 @@ enum radeon_micro_mode
#define RADEON_SURF_PRT (1ull << 32)
struct legacy_surf_level {
- uint64_t offset;
+ uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */
uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */
unsigned nblk_x : 15;
unsigned nblk_y : 15;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 2800de4384d..0120a6e05f2 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4140,7 +4140,7 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem
offset = surface->u.gfx9.surf_slice_size * layer + surface->u.gfx9.prt_level_offset[level];
pitch = surface->u.gfx9.prt_level_pitch[level];
} else {
- offset = surface->u.legacy.level[level].offset +
+ offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 +
surface->u.legacy.level[level].slice_size_dw * 4 * layer;
pitch = surface->u.legacy.level[level].nblk_x;
}
@@ -6322,7 +6322,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
- cb->cb_color_base += level_info->offset >> 8;
+ cb->cb_color_base += level_info->offset_256B;
if (level_info->mode == RADEON_SURF_MODE_2D)
cb->cb_color_base |= surf->tile_swizzle;
@@ -6633,8 +6633,8 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
if (stencil_only)
level_info = &surf->u.legacy.stencil_level[level];
- z_offs += surf->u.legacy.level[level].offset;
- s_offs += surf->u.legacy.stencil_level[level].offset;
+ z_offs += (uint64_t)surf->u.legacy.level[level].offset_256B * 256;
+ s_offs += (uint64_t)surf->u.legacy.stencil_level[level].offset_256B * 256;
ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 925444d3fd0..5770e2789bb 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -1814,9 +1814,9 @@ radv_GetImageSparseMemoryRequirements2(VkDevice _device,
image->planes[0].surface.u.gfx9.surf_slice_size;
} else {
req->memoryRequirements.imageMipTailOffset =
- image->planes[0]
+ (uint64_t)image->planes[0]
.surface.u.legacy.level[req->memoryRequirements.imageMipTailFirstLod]
- .offset;
+ .offset_256B * 256;
req->memoryRequirements.imageMipTailSize =
image->size - req->memoryRequirements.imageMipTailOffset;
req->memoryRequirements.imageMipTailStride = 0;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index eb3b9ac47de..94a380d22ed 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -688,7 +688,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im
else
va += plane->surface.u.gfx9.surf_offset;
} else
- va += base_level_info->offset;
+ va += (uint64_t)base_level_info->offset_256B * 256;
state[0] = va >> 8;
if (chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
@@ -2126,7 +2126,7 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image,
if (image->type == VK_IMAGE_TYPE_3D)
pLayout->size *= u_minify(image->info.depth, level);
} else {
- pLayout->offset = surface->u.legacy.level[level].offset +
+ pLayout->offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 +
(uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 01:38:33 +0000