diff options
| -rw-r--r-- | src/freedreno/ir3/ir3.h | 11 | ||||
| -rw-r--r-- | src/freedreno/ir3/ir3_postsched.c | 2 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 487dd4b4b1a..f949ba32535 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -1006,6 +1006,17 @@ static inline bool writes_pred(struct ir3_instruction *instr) return false; } +/* Is it something other than a normal register. Shared regs, p0, and a0/a1 + * are considered special here. Special registers are always accessed with one + * size and never alias normal registers, even though a naive calculation + * would sometimes make it seem like e.g. r30.z aliases a0.x. + */ +static inline bool is_reg_special(const struct ir3_register *reg) +{ + return (reg->flags & IR3_REG_SHARED) || + (reg_num(reg) == REG_A0) || (reg_num(reg) == REG_P0); +} + /* returns defining instruction for reg */ /* TODO better name */ static inline struct ir3_instruction *ssa(struct ir3_register *reg) diff --git a/src/freedreno/ir3/ir3_postsched.c b/src/freedreno/ir3/ir3_postsched.c index 3b246ed0963..cf6bec512b5 100644 --- a/src/freedreno/ir3/ir3_postsched.c +++ b/src/freedreno/ir3/ir3_postsched.c @@ -422,7 +422,7 @@ add_reg_dep(struct ir3_postsched_deps_state *state, * half-registers don't alias random full registers by pretending that * they're full registers: */ - if ((reg->flags & IR3_REG_HALF) && num < regid(48, 0)) { + if ((reg->flags & IR3_REG_HALF) && !is_reg_special(reg)) { /* single conflict in half-reg space: */ add_single_reg_dep(state, node, num, src_n); } else { |