diff options
author | Alyssa Rosenzweig <alyssa@collabora.com> | 2021-06-11 18:48:09 -0400 |
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committer | Marge Bot <eric+marge@anholt.net> | 2021-08-23 20:54:33 +0000 |
commit | f45ceb818261859e623b45653b55347566c2b8f2 (patch) | |
tree | a27ebdd1c0869668e03c9f8a4d57fabf82170508 /src/panfrost/midgard/midgard_schedule.c | |
parent | 7cc3a7ff45ed8740e248bb8843272cbdc87974a8 (diff) |
pan/mdg: Insert moves before writeout when needed
Otherwise we end up accessing overwritten registers. Fixes
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_common.common_enable_buffer_enable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11383>
Diffstat (limited to 'src/panfrost/midgard/midgard_schedule.c')
-rw-r--r-- | src/panfrost/midgard/midgard_schedule.c | 42 |
1 files changed, 41 insertions, 1 deletions
diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index f987b7f17fd..a371f6eef05 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -1527,6 +1527,40 @@ mir_lower_ldst(compiler_context *ctx) } } +/* Insert moves to ensure we can register allocate blend writeout */ +static void +mir_lower_blend_input(compiler_context *ctx) +{ + mir_foreach_block(ctx, _blk) { + midgard_block *blk = (midgard_block *) _blk; + + if (list_is_empty(&blk->base.instructions)) + continue; + + midgard_instruction *I = mir_last_in_block(blk); + + if (!I || I->type != TAG_ALU_4 || !I->writeout) + continue; + + mir_foreach_src(I, s) { + unsigned src = I->src[s]; + + if (src >= ctx->temp_count) + continue; + + if (!_blk->live_out[src]) + continue; + + unsigned temp = make_compiler_temp(ctx); + midgard_instruction mov = v_mov(src, temp); + mov.mask = 0xF; + mov.dest_type = nir_type_uint32; + mir_insert_instruction_before(ctx, I, mov); + I->src[s] = mov.dest; + } + } +} + void midgard_schedule_program(compiler_context *ctx) { @@ -1536,6 +1570,13 @@ midgard_schedule_program(compiler_context *ctx) /* Must be lowered right before scheduling */ mir_squeeze_index(ctx); mir_lower_special_reads(ctx); + + if (ctx->stage == MESA_SHADER_FRAGMENT) { + mir_invalidate_liveness(ctx); + mir_compute_liveness(ctx); + mir_lower_blend_input(ctx); + } + mir_squeeze_index(ctx); /* Lowering can introduce some dead moves */ @@ -1545,5 +1586,4 @@ midgard_schedule_program(compiler_context *ctx) midgard_opt_dead_move_eliminate(ctx, block); schedule_block(ctx, block); } - } |